1 #ifndef DSI_XML 2 #define DSI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) 24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) 25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) 26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) 27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) 28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) 29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) 30 31 Copyright (C) 2013-2021 by the following authors: 32 - Rob Clark <robdclark@gmail.com> (robclark) 33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 34 35 Permission is hereby granted, free of charge, to any person obtaining 36 a copy of this software and associated documentation files (the 37 "Software"), to deal in the Software without restriction, including 38 without limitation the rights to use, copy, modify, merge, publish, 39 distribute, sublicense, and/or sell copies of the Software, and to 40 permit persons to whom the Software is furnished to do so, subject to 41 the following conditions: 42 43 The above copyright notice and this permission notice (including the 44 next paragraph) shall be included in all copies or substantial 45 portions of the Software. 46 47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 54 */ 55 56 57 enum dsi_traffic_mode { 58 NON_BURST_SYNCH_PULSE = 0, 59 NON_BURST_SYNCH_EVENT = 1, 60 BURST_MODE = 2, 61 }; 62 63 enum dsi_vid_dst_format { 64 VID_DST_FORMAT_RGB565 = 0, 65 VID_DST_FORMAT_RGB666 = 1, 66 VID_DST_FORMAT_RGB666_LOOSE = 2, 67 VID_DST_FORMAT_RGB888 = 3, 68 }; 69 70 enum dsi_rgb_swap { 71 SWAP_RGB = 0, 72 SWAP_RBG = 1, 73 SWAP_BGR = 2, 74 SWAP_BRG = 3, 75 SWAP_GRB = 4, 76 SWAP_GBR = 5, 77 }; 78 79 enum dsi_cmd_trigger { 80 TRIGGER_NONE = 0, 81 TRIGGER_SEOF = 1, 82 TRIGGER_TE = 2, 83 TRIGGER_SW = 4, 84 TRIGGER_SW_SEOF = 5, 85 TRIGGER_SW_TE = 6, 86 }; 87 88 enum dsi_cmd_dst_format { 89 CMD_DST_FORMAT_RGB111 = 0, 90 CMD_DST_FORMAT_RGB332 = 3, 91 CMD_DST_FORMAT_RGB444 = 4, 92 CMD_DST_FORMAT_RGB565 = 6, 93 CMD_DST_FORMAT_RGB666 = 7, 94 CMD_DST_FORMAT_RGB888 = 8, 95 }; 96 97 enum dsi_lane_swap { 98 LANE_SWAP_0123 = 0, 99 LANE_SWAP_3012 = 1, 100 LANE_SWAP_2301 = 2, 101 LANE_SWAP_1230 = 3, 102 LANE_SWAP_0321 = 4, 103 LANE_SWAP_1032 = 5, 104 LANE_SWAP_2103 = 6, 105 LANE_SWAP_3210 = 7, 106 }; 107 108 enum video_config_bpp { 109 VIDEO_CONFIG_18BPP = 0, 110 VIDEO_CONFIG_24BPP = 1, 111 }; 112 113 enum video_pattern_sel { 114 VID_PRBS = 0, 115 VID_INCREMENTAL = 1, 116 VID_FIXED = 2, 117 VID_MDSS_GENERAL_PATTERN = 3, 118 }; 119 120 enum cmd_mdp_stream0_pattern_sel { 121 CMD_MDP_PRBS = 0, 122 CMD_MDP_INCREMENTAL = 1, 123 CMD_MDP_FIXED = 2, 124 CMD_MDP_MDSS_GENERAL_PATTERN = 3, 125 }; 126 127 enum cmd_dma_pattern_sel { 128 CMD_DMA_PRBS = 0, 129 CMD_DMA_INCREMENTAL = 1, 130 CMD_DMA_FIXED = 2, 131 CMD_DMA_CUSTOM_PATTERN_DMA_FIFO = 3, 132 }; 133 134 #define DSI_IRQ_CMD_DMA_DONE 0x00000001 135 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 136 #define DSI_IRQ_CMD_MDP_DONE 0x00000100 137 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 138 #define DSI_IRQ_VIDEO_DONE 0x00010000 139 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 140 #define DSI_IRQ_BTA_DONE 0x00100000 141 #define DSI_IRQ_MASK_BTA_DONE 0x00200000 142 #define DSI_IRQ_ERROR 0x01000000 143 #define DSI_IRQ_MASK_ERROR 0x02000000 144 #define REG_DSI_6G_HW_VERSION 0x00000000 145 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 146 #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 147 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) 148 { 149 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; 150 } 151 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 152 #define DSI_6G_HW_VERSION_MINOR__SHIFT 16 153 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) 154 { 155 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; 156 } 157 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff 158 #define DSI_6G_HW_VERSION_STEP__SHIFT 0 159 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) 160 { 161 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; 162 } 163 164 #define REG_DSI_CTRL 0x00000000 165 #define DSI_CTRL_ENABLE 0x00000001 166 #define DSI_CTRL_VID_MODE_EN 0x00000002 167 #define DSI_CTRL_CMD_MODE_EN 0x00000004 168 #define DSI_CTRL_LANE0 0x00000010 169 #define DSI_CTRL_LANE1 0x00000020 170 #define DSI_CTRL_LANE2 0x00000040 171 #define DSI_CTRL_LANE3 0x00000080 172 #define DSI_CTRL_CLK_EN 0x00000100 173 #define DSI_CTRL_ECC_CHECK 0x00100000 174 #define DSI_CTRL_CRC_CHECK 0x01000000 175 176 #define REG_DSI_STATUS0 0x00000004 177 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 178 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 179 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 180 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 181 #define DSI_STATUS0_DSI_BUSY 0x00000010 182 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 183 184 #define REG_DSI_FIFO_STATUS 0x00000008 185 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001 186 #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008 187 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 188 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100 189 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200 190 #define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400 191 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000 192 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000 193 #define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000 194 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000 195 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000 196 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000 197 #define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000 198 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000 199 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000 200 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000 201 #define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000 202 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000 203 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000 204 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000 205 #define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000 206 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000 207 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000 208 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000 209 #define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000 210 211 #define REG_DSI_VID_CFG0 0x0000000c 212 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 213 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 214 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) 215 { 216 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; 217 } 218 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 219 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 220 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) 221 { 222 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; 223 } 224 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 225 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 226 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) 227 { 228 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; 229 } 230 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 231 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 232 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 233 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 234 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 235 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 236 237 #define REG_DSI_VID_CFG1 0x0000001c 238 #define DSI_VID_CFG1_R_SEL 0x00000001 239 #define DSI_VID_CFG1_G_SEL 0x00000010 240 #define DSI_VID_CFG1_B_SEL 0x00000100 241 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 242 #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 243 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) 244 { 245 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; 246 } 247 248 #define REG_DSI_ACTIVE_H 0x00000020 249 #define DSI_ACTIVE_H_START__MASK 0x00000fff 250 #define DSI_ACTIVE_H_START__SHIFT 0 251 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) 252 { 253 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; 254 } 255 #define DSI_ACTIVE_H_END__MASK 0x0fff0000 256 #define DSI_ACTIVE_H_END__SHIFT 16 257 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) 258 { 259 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; 260 } 261 262 #define REG_DSI_ACTIVE_V 0x00000024 263 #define DSI_ACTIVE_V_START__MASK 0x00000fff 264 #define DSI_ACTIVE_V_START__SHIFT 0 265 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) 266 { 267 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; 268 } 269 #define DSI_ACTIVE_V_END__MASK 0x0fff0000 270 #define DSI_ACTIVE_V_END__SHIFT 16 271 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) 272 { 273 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; 274 } 275 276 #define REG_DSI_TOTAL 0x00000028 277 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff 278 #define DSI_TOTAL_H_TOTAL__SHIFT 0 279 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) 280 { 281 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; 282 } 283 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 284 #define DSI_TOTAL_V_TOTAL__SHIFT 16 285 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) 286 { 287 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; 288 } 289 290 #define REG_DSI_ACTIVE_HSYNC 0x0000002c 291 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff 292 #define DSI_ACTIVE_HSYNC_START__SHIFT 0 293 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) 294 { 295 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; 296 } 297 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 298 #define DSI_ACTIVE_HSYNC_END__SHIFT 16 299 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) 300 { 301 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; 302 } 303 304 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 305 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff 306 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 307 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) 308 { 309 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; 310 } 311 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 312 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 313 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) 314 { 315 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; 316 } 317 318 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 319 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff 320 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 321 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) 322 { 323 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; 324 } 325 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 326 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 327 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) 328 { 329 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; 330 } 331 332 #define REG_DSI_CMD_DMA_CTRL 0x00000038 333 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 334 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 335 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 336 337 #define REG_DSI_CMD_CFG0 0x0000003c 338 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f 339 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 340 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) 341 { 342 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; 343 } 344 #define DSI_CMD_CFG0_R_SEL 0x00000010 345 #define DSI_CMD_CFG0_G_SEL 0x00000100 346 #define DSI_CMD_CFG0_B_SEL 0x00001000 347 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 348 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 349 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) 350 { 351 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; 352 } 353 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 354 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 355 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) 356 { 357 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; 358 } 359 360 #define REG_DSI_CMD_CFG1 0x00000040 361 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff 362 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 363 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) 364 { 365 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; 366 } 367 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 368 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 369 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) 370 { 371 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; 372 } 373 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 374 375 #define REG_DSI_DMA_BASE 0x00000044 376 377 #define REG_DSI_DMA_LEN 0x00000048 378 379 #define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054 380 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f 381 #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0 382 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val) 383 { 384 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK; 385 } 386 #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 387 #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8 388 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val) 389 { 390 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK; 391 } 392 #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000 393 #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16 394 static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val) 395 { 396 return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK; 397 } 398 399 #define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058 400 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff 401 #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0 402 static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val) 403 { 404 return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK; 405 } 406 #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000 407 #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16 408 static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val) 409 { 410 return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK; 411 } 412 413 #define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c 414 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f 415 #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0 416 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val) 417 { 418 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK; 419 } 420 #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 421 #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8 422 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val) 423 { 424 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK; 425 } 426 #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000 427 #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16 428 static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val) 429 { 430 return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK; 431 } 432 433 #define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060 434 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff 435 #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0 436 static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val) 437 { 438 return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK; 439 } 440 #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000 441 #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16 442 static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val) 443 { 444 return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK; 445 } 446 447 #define REG_DSI_ACK_ERR_STATUS 0x00000064 448 449 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } 450 451 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } 452 453 #define REG_DSI_TRIG_CTRL 0x00000080 454 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 455 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 456 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) 457 { 458 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; 459 } 460 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 461 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 462 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) 463 { 464 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; 465 } 466 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 467 #define DSI_TRIG_CTRL_STREAM__SHIFT 8 468 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) 469 { 470 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; 471 } 472 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 473 #define DSI_TRIG_CTRL_TE 0x80000000 474 475 #define REG_DSI_TRIG_DMA 0x0000008c 476 477 #define REG_DSI_DLN0_PHY_ERR 0x000000b0 478 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001 479 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010 480 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100 481 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 482 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 483 484 #define REG_DSI_LP_TIMER_CTRL 0x000000b4 485 #define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff 486 #define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0 487 static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val) 488 { 489 return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK; 490 } 491 #define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000 492 #define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16 493 static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val) 494 { 495 return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK; 496 } 497 498 #define REG_DSI_HS_TIMER_CTRL 0x000000b8 499 #define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff 500 #define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0 501 static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val) 502 { 503 return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK; 504 } 505 #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000 506 #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16 507 static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val) 508 { 509 return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK; 510 } 511 #define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000 512 513 #define REG_DSI_TIMEOUT_STATUS 0x000000bc 514 515 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 516 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f 517 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 518 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) 519 { 520 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; 521 } 522 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 523 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 524 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) 525 { 526 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; 527 } 528 529 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8 530 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 531 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 532 533 #define REG_DSI_LANE_STATUS 0x000000a4 534 #define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001 535 #define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002 536 #define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004 537 #define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008 538 #define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010 539 #define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100 540 #define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200 541 #define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400 542 #define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800 543 #define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000 544 #define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000 545 546 #define REG_DSI_LANE_CTRL 0x000000a8 547 #define DSI_LANE_CTRL_HS_REQ_SEL_PHY 0x01000000 548 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 549 550 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac 551 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 552 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 553 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) 554 { 555 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; 556 } 557 558 #define REG_DSI_ERR_INT_MASK0 0x00000108 559 560 #define REG_DSI_INTR_CTRL 0x0000010c 561 562 #define REG_DSI_RESET 0x00000114 563 564 #define REG_DSI_CLK_CTRL 0x00000118 565 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 566 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 567 #define DSI_CLK_CTRL_PCLK_ON 0x00000004 568 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008 569 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 570 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 571 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 572 573 #define REG_DSI_CLK_STATUS 0x0000011c 574 #define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001 575 #define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002 576 #define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004 577 #define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008 578 #define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010 579 #define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020 580 #define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040 581 #define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080 582 #define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100 583 #define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200 584 #define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400 585 #define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000 586 #define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000 587 #define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000 588 #define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000 589 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 590 591 #define REG_DSI_PHY_RESET 0x00000128 592 #define DSI_PHY_RESET_RESET 0x00000001 593 594 #define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160 595 596 #define REG_DSI_TPG_MAIN_CONTROL 0x00000198 597 #define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN 0x00000100 598 599 #define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0 600 #define DSI_TPG_VIDEO_CONFIG_BPP__MASK 0x00000003 601 #define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT 0 602 static inline uint32_t DSI_TPG_VIDEO_CONFIG_BPP(enum video_config_bpp val) 603 { 604 return ((val) << DSI_TPG_VIDEO_CONFIG_BPP__SHIFT) & DSI_TPG_VIDEO_CONFIG_BPP__MASK; 605 } 606 #define DSI_TPG_VIDEO_CONFIG_RGB 0x00000004 607 608 #define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158 609 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK 0x00030000 610 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT 16 611 static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL(enum cmd_dma_pattern_sel val) 612 { 613 return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK; 614 } 615 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK 0x00000300 616 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT 8 617 static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(enum cmd_mdp_stream0_pattern_sel val) 618 { 619 return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK; 620 } 621 #define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK 0x00000030 622 #define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT 4 623 static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(enum video_pattern_sel val) 624 { 625 return ((val) << DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK; 626 } 627 #define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE 0x00000004 628 #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN 0x00000002 629 #define DSI_TEST_PATTERN_GEN_CTRL_EN 0x00000001 630 631 #define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168 632 633 #define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180 634 #define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER 0x00000001 635 636 #define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c 637 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN 0x00000080 638 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN 0x00010000 639 #define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN 0x02000000 640 641 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c 642 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 643 644 #define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4 645 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f 646 #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0 647 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val) 648 { 649 return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK; 650 } 651 #define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010 652 #define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020 653 #define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040 654 #define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080 655 #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700 656 #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8 657 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val) 658 { 659 return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK; 660 } 661 #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000 662 #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12 663 static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val) 664 { 665 return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK; 666 } 667 #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000 668 669 #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8 670 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f 671 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0 672 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val) 673 { 674 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK; 675 } 676 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 677 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8 678 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val) 679 { 680 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK; 681 } 682 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000 683 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16 684 static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val) 685 { 686 return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK; 687 } 688 689 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0 690 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 691 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 692 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) 693 { 694 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; 695 } 696 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001 697 698 #define REG_DSI_VERSION 0x000001f0 699 #define DSI_VERSION_MAJOR__MASK 0xff000000 700 #define DSI_VERSION_MAJOR__SHIFT 24 701 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) 702 { 703 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; 704 } 705 706 #define REG_DSI_CPHY_MODE_CTRL 0x000002d4 707 708 709 #endif /* DSI_XML */ 710