1 #ifndef DSI_XML 2 #define DSI_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-01-12 09:09:22) 12 - /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54) 13 14 Copyright (C) 2013-2018 by the following authors: 15 - Rob Clark <robdclark@gmail.com> (robclark) 16 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 17 18 Permission is hereby granted, free of charge, to any person obtaining 19 a copy of this software and associated documentation files (the 20 "Software"), to deal in the Software without restriction, including 21 without limitation the rights to use, copy, modify, merge, publish, 22 distribute, sublicense, and/or sell copies of the Software, and to 23 permit persons to whom the Software is furnished to do so, subject to 24 the following conditions: 25 26 The above copyright notice and this permission notice (including the 27 next paragraph) shall be included in all copies or substantial 28 portions of the Software. 29 30 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 31 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 32 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 33 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 34 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 35 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 36 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 37 */ 38 39 40 enum dsi_traffic_mode { 41 NON_BURST_SYNCH_PULSE = 0, 42 NON_BURST_SYNCH_EVENT = 1, 43 BURST_MODE = 2, 44 }; 45 46 enum dsi_vid_dst_format { 47 VID_DST_FORMAT_RGB565 = 0, 48 VID_DST_FORMAT_RGB666 = 1, 49 VID_DST_FORMAT_RGB666_LOOSE = 2, 50 VID_DST_FORMAT_RGB888 = 3, 51 }; 52 53 enum dsi_rgb_swap { 54 SWAP_RGB = 0, 55 SWAP_RBG = 1, 56 SWAP_BGR = 2, 57 SWAP_BRG = 3, 58 SWAP_GRB = 4, 59 SWAP_GBR = 5, 60 }; 61 62 enum dsi_cmd_trigger { 63 TRIGGER_NONE = 0, 64 TRIGGER_SEOF = 1, 65 TRIGGER_TE = 2, 66 TRIGGER_SW = 4, 67 TRIGGER_SW_SEOF = 5, 68 TRIGGER_SW_TE = 6, 69 }; 70 71 enum dsi_cmd_dst_format { 72 CMD_DST_FORMAT_RGB111 = 0, 73 CMD_DST_FORMAT_RGB332 = 3, 74 CMD_DST_FORMAT_RGB444 = 4, 75 CMD_DST_FORMAT_RGB565 = 6, 76 CMD_DST_FORMAT_RGB666 = 7, 77 CMD_DST_FORMAT_RGB888 = 8, 78 }; 79 80 enum dsi_lane_swap { 81 LANE_SWAP_0123 = 0, 82 LANE_SWAP_3012 = 1, 83 LANE_SWAP_2301 = 2, 84 LANE_SWAP_1230 = 3, 85 LANE_SWAP_0321 = 4, 86 LANE_SWAP_1032 = 5, 87 LANE_SWAP_2103 = 6, 88 LANE_SWAP_3210 = 7, 89 }; 90 91 #define DSI_IRQ_CMD_DMA_DONE 0x00000001 92 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 93 #define DSI_IRQ_CMD_MDP_DONE 0x00000100 94 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 95 #define DSI_IRQ_VIDEO_DONE 0x00010000 96 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 97 #define DSI_IRQ_BTA_DONE 0x00100000 98 #define DSI_IRQ_MASK_BTA_DONE 0x00200000 99 #define DSI_IRQ_ERROR 0x01000000 100 #define DSI_IRQ_MASK_ERROR 0x02000000 101 #define REG_DSI_6G_HW_VERSION 0x00000000 102 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 103 #define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 104 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) 105 { 106 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; 107 } 108 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 109 #define DSI_6G_HW_VERSION_MINOR__SHIFT 16 110 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) 111 { 112 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; 113 } 114 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff 115 #define DSI_6G_HW_VERSION_STEP__SHIFT 0 116 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) 117 { 118 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; 119 } 120 121 #define REG_DSI_CTRL 0x00000000 122 #define DSI_CTRL_ENABLE 0x00000001 123 #define DSI_CTRL_VID_MODE_EN 0x00000002 124 #define DSI_CTRL_CMD_MODE_EN 0x00000004 125 #define DSI_CTRL_LANE0 0x00000010 126 #define DSI_CTRL_LANE1 0x00000020 127 #define DSI_CTRL_LANE2 0x00000040 128 #define DSI_CTRL_LANE3 0x00000080 129 #define DSI_CTRL_CLK_EN 0x00000100 130 #define DSI_CTRL_ECC_CHECK 0x00100000 131 #define DSI_CTRL_CRC_CHECK 0x01000000 132 133 #define REG_DSI_STATUS0 0x00000004 134 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 135 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 136 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 137 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 138 #define DSI_STATUS0_DSI_BUSY 0x00000010 139 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 140 141 #define REG_DSI_FIFO_STATUS 0x00000008 142 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 143 144 #define REG_DSI_VID_CFG0 0x0000000c 145 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 146 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0 147 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) 148 { 149 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; 150 } 151 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 152 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 153 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) 154 { 155 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; 156 } 157 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300 158 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8 159 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) 160 { 161 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; 162 } 163 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000 164 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000 165 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 166 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 167 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 168 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 169 170 #define REG_DSI_VID_CFG1 0x0000001c 171 #define DSI_VID_CFG1_R_SEL 0x00000001 172 #define DSI_VID_CFG1_G_SEL 0x00000010 173 #define DSI_VID_CFG1_B_SEL 0x00000100 174 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 175 #define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 176 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) 177 { 178 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; 179 } 180 181 #define REG_DSI_ACTIVE_H 0x00000020 182 #define DSI_ACTIVE_H_START__MASK 0x00000fff 183 #define DSI_ACTIVE_H_START__SHIFT 0 184 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) 185 { 186 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; 187 } 188 #define DSI_ACTIVE_H_END__MASK 0x0fff0000 189 #define DSI_ACTIVE_H_END__SHIFT 16 190 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) 191 { 192 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; 193 } 194 195 #define REG_DSI_ACTIVE_V 0x00000024 196 #define DSI_ACTIVE_V_START__MASK 0x00000fff 197 #define DSI_ACTIVE_V_START__SHIFT 0 198 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) 199 { 200 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; 201 } 202 #define DSI_ACTIVE_V_END__MASK 0x0fff0000 203 #define DSI_ACTIVE_V_END__SHIFT 16 204 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) 205 { 206 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; 207 } 208 209 #define REG_DSI_TOTAL 0x00000028 210 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff 211 #define DSI_TOTAL_H_TOTAL__SHIFT 0 212 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) 213 { 214 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; 215 } 216 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000 217 #define DSI_TOTAL_V_TOTAL__SHIFT 16 218 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) 219 { 220 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; 221 } 222 223 #define REG_DSI_ACTIVE_HSYNC 0x0000002c 224 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff 225 #define DSI_ACTIVE_HSYNC_START__SHIFT 0 226 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) 227 { 228 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; 229 } 230 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000 231 #define DSI_ACTIVE_HSYNC_END__SHIFT 16 232 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) 233 { 234 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; 235 } 236 237 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 238 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff 239 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 240 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) 241 { 242 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; 243 } 244 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 245 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 246 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) 247 { 248 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; 249 } 250 251 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 252 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff 253 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 254 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) 255 { 256 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; 257 } 258 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 259 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 260 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) 261 { 262 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; 263 } 264 265 #define REG_DSI_CMD_DMA_CTRL 0x00000038 266 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 267 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 268 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 269 270 #define REG_DSI_CMD_CFG0 0x0000003c 271 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f 272 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 273 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) 274 { 275 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; 276 } 277 #define DSI_CMD_CFG0_R_SEL 0x00000010 278 #define DSI_CMD_CFG0_G_SEL 0x00000100 279 #define DSI_CMD_CFG0_B_SEL 0x00001000 280 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 281 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 282 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) 283 { 284 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; 285 } 286 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 287 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 288 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) 289 { 290 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; 291 } 292 293 #define REG_DSI_CMD_CFG1 0x00000040 294 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff 295 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 296 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) 297 { 298 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; 299 } 300 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 301 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 302 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) 303 { 304 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; 305 } 306 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 307 308 #define REG_DSI_DMA_BASE 0x00000044 309 310 #define REG_DSI_DMA_LEN 0x00000048 311 312 #define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054 313 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f 314 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0 315 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) 316 { 317 return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK; 318 } 319 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 320 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8 321 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) 322 { 323 return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK; 324 } 325 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000 326 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16 327 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) 328 { 329 return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK; 330 } 331 332 #define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058 333 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff 334 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0 335 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) 336 { 337 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; 338 } 339 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000 340 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16 341 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) 342 { 343 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; 344 } 345 346 #define REG_DSI_ACK_ERR_STATUS 0x00000064 347 348 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } 349 350 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } 351 352 #define REG_DSI_TRIG_CTRL 0x00000080 353 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 354 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 355 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) 356 { 357 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; 358 } 359 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 360 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 361 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) 362 { 363 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; 364 } 365 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 366 #define DSI_TRIG_CTRL_STREAM__SHIFT 8 367 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) 368 { 369 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; 370 } 371 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 372 #define DSI_TRIG_CTRL_TE 0x80000000 373 374 #define REG_DSI_TRIG_DMA 0x0000008c 375 376 #define REG_DSI_DLN0_PHY_ERR 0x000000b0 377 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001 378 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010 379 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100 380 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 381 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 382 383 #define REG_DSI_TIMEOUT_STATUS 0x000000bc 384 385 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 386 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f 387 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0 388 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) 389 { 390 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; 391 } 392 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00 393 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8 394 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) 395 { 396 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK; 397 } 398 399 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8 400 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 401 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 402 403 #define REG_DSI_LANE_CTRL 0x000000a8 404 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 405 406 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac 407 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 408 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 409 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) 410 { 411 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; 412 } 413 414 #define REG_DSI_ERR_INT_MASK0 0x00000108 415 416 #define REG_DSI_INTR_CTRL 0x0000010c 417 418 #define REG_DSI_RESET 0x00000114 419 420 #define REG_DSI_CLK_CTRL 0x00000118 421 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 422 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 423 #define DSI_CLK_CTRL_PCLK_ON 0x00000004 424 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008 425 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 426 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 427 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 428 429 #define REG_DSI_CLK_STATUS 0x0000011c 430 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 431 432 #define REG_DSI_PHY_RESET 0x00000128 433 #define DSI_PHY_RESET_RESET 0x00000001 434 435 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c 436 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 437 438 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0 439 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 440 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 441 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) 442 { 443 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; 444 } 445 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001 446 447 #define REG_DSI_VERSION 0x000001f0 448 #define DSI_VERSION_MAJOR__MASK 0xff000000 449 #define DSI_VERSION_MAJOR__SHIFT 24 450 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) 451 { 452 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; 453 } 454 455 #define REG_DSI_PHY_PLL_CTRL_0 0x00000200 456 #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001 457 458 #define REG_DSI_PHY_PLL_CTRL_1 0x00000204 459 460 #define REG_DSI_PHY_PLL_CTRL_2 0x00000208 461 462 #define REG_DSI_PHY_PLL_CTRL_3 0x0000020c 463 464 #define REG_DSI_PHY_PLL_CTRL_4 0x00000210 465 466 #define REG_DSI_PHY_PLL_CTRL_5 0x00000214 467 468 #define REG_DSI_PHY_PLL_CTRL_6 0x00000218 469 470 #define REG_DSI_PHY_PLL_CTRL_7 0x0000021c 471 472 #define REG_DSI_PHY_PLL_CTRL_8 0x00000220 473 474 #define REG_DSI_PHY_PLL_CTRL_9 0x00000224 475 476 #define REG_DSI_PHY_PLL_CTRL_10 0x00000228 477 478 #define REG_DSI_PHY_PLL_CTRL_11 0x0000022c 479 480 #define REG_DSI_PHY_PLL_CTRL_12 0x00000230 481 482 #define REG_DSI_PHY_PLL_CTRL_13 0x00000234 483 484 #define REG_DSI_PHY_PLL_CTRL_14 0x00000238 485 486 #define REG_DSI_PHY_PLL_CTRL_15 0x0000023c 487 488 #define REG_DSI_PHY_PLL_CTRL_16 0x00000240 489 490 #define REG_DSI_PHY_PLL_CTRL_17 0x00000244 491 492 #define REG_DSI_PHY_PLL_CTRL_18 0x00000248 493 494 #define REG_DSI_PHY_PLL_CTRL_19 0x0000024c 495 496 #define REG_DSI_PHY_PLL_CTRL_20 0x00000250 497 498 #define REG_DSI_PHY_PLL_STATUS 0x00000280 499 #define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001 500 501 #define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258 502 503 #define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c 504 505 #define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260 506 507 #define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264 508 509 #define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268 510 511 #define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c 512 513 #define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270 514 515 #define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274 516 517 #define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278 518 519 #define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c 520 521 #define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280 522 523 #define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284 524 525 #define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288 526 527 #define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c 528 529 #define REG_DSI_8x60_PHY_CTRL_0 0x00000290 530 531 #define REG_DSI_8x60_PHY_CTRL_1 0x00000294 532 533 #define REG_DSI_8x60_PHY_CTRL_2 0x00000298 534 535 #define REG_DSI_8x60_PHY_CTRL_3 0x0000029c 536 537 #define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0 538 539 #define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4 540 541 #define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8 542 543 #define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac 544 545 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc 546 547 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0 548 549 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4 550 551 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8 552 553 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc 554 555 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0 556 557 #define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4 558 559 #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc 560 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000 561 562 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 563 564 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 565 566 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 567 568 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 569 570 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } 571 572 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } 573 574 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } 575 576 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100 577 578 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104 579 580 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108 581 582 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c 583 584 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114 585 586 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118 587 588 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140 589 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 590 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 591 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 592 { 593 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 594 } 595 596 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144 597 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 598 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 599 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 600 { 601 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 602 } 603 604 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148 605 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 606 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 607 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 608 { 609 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 610 } 611 612 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c 613 614 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150 615 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 616 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 617 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 618 { 619 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 620 } 621 622 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154 623 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 624 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 625 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 626 { 627 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 628 } 629 630 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158 631 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 632 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 633 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 634 { 635 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 636 } 637 638 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c 639 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 640 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 641 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 642 { 643 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 644 } 645 646 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160 647 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 648 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 649 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 650 { 651 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; 652 } 653 654 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164 655 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 656 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 657 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 658 { 659 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; 660 } 661 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 662 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 663 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 664 { 665 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; 666 } 667 668 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168 669 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 670 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 671 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 672 { 673 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; 674 } 675 676 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c 677 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 678 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 679 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 680 { 681 return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 682 } 683 684 #define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170 685 686 #define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174 687 688 #define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178 689 690 #define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c 691 692 #define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180 693 694 #define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184 695 696 #define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188 697 698 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c 699 700 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190 701 702 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194 703 704 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198 705 706 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c 707 708 #define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0 709 710 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000 711 712 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004 713 714 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008 715 716 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c 717 718 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010 719 720 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014 721 722 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018 723 724 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028 725 726 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c 727 728 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030 729 730 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034 731 732 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038 733 734 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c 735 736 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040 737 738 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044 739 740 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048 741 742 #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050 743 #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010 744 745 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000 746 #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001 747 748 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 749 750 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 751 752 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c 753 754 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010 755 756 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014 757 758 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018 759 760 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c 761 762 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 763 764 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024 765 766 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028 767 768 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c 769 770 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030 771 772 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034 773 774 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038 775 776 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c 777 778 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040 779 780 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044 781 782 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048 783 784 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c 785 786 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050 787 788 #define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080 789 #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001 790 791 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 792 793 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 794 795 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 796 797 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 798 799 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } 800 801 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } 802 803 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } 804 805 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } 806 807 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } 808 809 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } 810 811 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 812 813 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 814 815 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 816 817 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c 818 819 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 820 821 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 822 823 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 824 825 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c 826 827 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 828 829 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 830 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 831 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 832 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 833 { 834 return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 835 } 836 837 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 838 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 839 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 840 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 841 { 842 return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 843 } 844 845 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 846 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 847 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 848 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 849 { 850 return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 851 } 852 853 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c 854 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 855 856 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 857 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 858 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 859 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 860 { 861 return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 862 } 863 864 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 865 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 866 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 867 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 868 { 869 return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 870 } 871 872 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 873 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 874 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 875 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 876 { 877 return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 878 } 879 880 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c 881 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 882 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 883 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 884 { 885 return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 886 } 887 888 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 889 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 890 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 891 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 892 { 893 return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; 894 } 895 896 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 897 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 898 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 899 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 900 { 901 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; 902 } 903 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 904 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 905 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 906 { 907 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; 908 } 909 910 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 911 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 912 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 913 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 914 { 915 return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; 916 } 917 918 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c 919 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 920 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 921 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 922 { 923 return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 924 } 925 926 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170 927 928 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174 929 930 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178 931 932 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c 933 934 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180 935 936 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 937 938 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 939 940 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 941 942 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 943 944 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc 945 946 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 947 948 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 949 950 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 951 952 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 953 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 954 955 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc 956 957 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 958 959 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 960 961 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 962 963 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c 964 965 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 966 967 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 968 969 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 970 971 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 972 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 973 974 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 975 976 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 977 978 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c 979 980 #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 981 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 982 983 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 984 985 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 986 987 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c 988 989 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 990 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 991 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 992 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 993 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 994 995 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 996 997 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 998 999 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c 1000 1001 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 1002 1003 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 1004 1005 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 1006 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f 1007 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 1008 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) 1009 { 1010 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; 1011 } 1012 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 1013 1014 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c 1015 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f 1016 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 1017 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) 1018 { 1019 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; 1020 } 1021 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 1022 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 1023 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) 1024 { 1025 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; 1026 } 1027 1028 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 1029 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff 1030 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 1031 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) 1032 { 1033 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; 1034 } 1035 1036 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 1037 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff 1038 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 1039 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) 1040 { 1041 return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; 1042 } 1043 1044 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 1045 1046 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c 1047 1048 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 1049 1050 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 1051 1052 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 1053 1054 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c 1055 1056 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 1057 1058 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 1059 1060 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 1061 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 1062 1063 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c 1064 1065 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 1066 1067 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 1068 1069 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 1070 1071 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c 1072 1073 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 1074 1075 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 1076 1077 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 1078 1079 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c 1080 1081 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 1082 1083 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 1084 1085 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 1086 1087 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c 1088 1089 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 1090 1091 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 1092 1093 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 1094 1095 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac 1096 1097 #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 1098 1099 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 1100 1101 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 1102 1103 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc 1104 1105 #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 1106 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 1107 1108 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 1109 1110 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 1111 1112 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc 1113 1114 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 1115 1116 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 1117 1118 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } 1119 1120 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } 1121 1122 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } 1123 1124 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } 1125 1126 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } 1127 1128 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } 1129 1130 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } 1131 1132 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } 1133 1134 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } 1135 1136 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } 1137 1138 #define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100 1139 1140 #define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104 1141 1142 #define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108 1143 1144 #define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c 1145 1146 #define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110 1147 1148 #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114 1149 1150 #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118 1151 1152 #define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c 1153 1154 #define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120 1155 1156 #define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140 1157 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff 1158 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 1159 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) 1160 { 1161 return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; 1162 } 1163 1164 #define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144 1165 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff 1166 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 1167 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) 1168 { 1169 return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; 1170 } 1171 1172 #define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148 1173 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff 1174 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 1175 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) 1176 { 1177 return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; 1178 } 1179 1180 #define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c 1181 #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 1182 1183 #define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150 1184 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 1185 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 1186 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) 1187 { 1188 return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; 1189 } 1190 1191 #define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154 1192 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 1193 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 1194 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) 1195 { 1196 return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; 1197 } 1198 1199 #define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158 1200 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 1201 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 1202 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 1203 { 1204 return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; 1205 } 1206 1207 #define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c 1208 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 1209 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 1210 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 1211 { 1212 return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; 1213 } 1214 1215 #define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160 1216 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 1217 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 1218 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) 1219 { 1220 return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; 1221 } 1222 1223 #define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164 1224 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 1225 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 1226 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) 1227 { 1228 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; 1229 } 1230 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 1231 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 1232 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) 1233 { 1234 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; 1235 } 1236 1237 #define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168 1238 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 1239 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 1240 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) 1241 { 1242 return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK; 1243 } 1244 1245 #define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c 1246 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 1247 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 1248 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 1249 { 1250 return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; 1251 } 1252 1253 #define REG_DSI_20nm_PHY_CTRL_0 0x00000170 1254 1255 #define REG_DSI_20nm_PHY_CTRL_1 0x00000174 1256 1257 #define REG_DSI_20nm_PHY_CTRL_2 0x00000178 1258 1259 #define REG_DSI_20nm_PHY_CTRL_3 0x0000017c 1260 1261 #define REG_DSI_20nm_PHY_CTRL_4 0x00000180 1262 1263 #define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184 1264 1265 #define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188 1266 1267 #define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4 1268 1269 #define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8 1270 1271 #define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc 1272 1273 #define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0 1274 1275 #define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4 1276 1277 #define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8 1278 1279 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4 1280 #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 1281 1282 #define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc 1283 1284 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000 1285 1286 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004 1287 1288 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008 1289 1290 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c 1291 1292 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010 1293 1294 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014 1295 1296 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 1297 1298 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000 1299 1300 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004 1301 1302 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008 1303 1304 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c 1305 1306 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010 1307 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0 1308 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4 1309 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) 1310 { 1311 return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK; 1312 } 1313 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0 1314 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4 1315 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) 1316 { 1317 return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK; 1318 } 1319 1320 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014 1321 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001 1322 1323 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018 1324 #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004 1325 1326 #define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c 1327 1328 #define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020 1329 1330 #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024 1331 1332 #define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028 1333 1334 #define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c 1335 1336 #define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030 1337 1338 #define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034 1339 1340 #define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038 1341 1342 #define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c 1343 1344 #define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040 1345 1346 #define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044 1347 1348 #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048 1349 #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001 1350 1351 #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c 1352 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f 1353 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0 1354 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) 1355 { 1356 return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK; 1357 } 1358 1359 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } 1360 1361 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } 1362 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0 1363 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6 1364 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) 1365 { 1366 return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK; 1367 } 1368 1369 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } 1370 #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001 1371 1372 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } 1373 1374 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } 1375 1376 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } 1377 1378 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } 1379 1380 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; } 1381 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff 1382 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0 1383 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) 1384 { 1385 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK; 1386 } 1387 1388 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; } 1389 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff 1390 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0 1391 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) 1392 { 1393 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK; 1394 } 1395 1396 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; } 1397 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff 1398 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 1399 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) 1400 { 1401 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK; 1402 } 1403 1404 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; } 1405 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff 1406 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 1407 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) 1408 { 1409 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK; 1410 } 1411 1412 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; } 1413 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff 1414 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0 1415 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) 1416 { 1417 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK; 1418 } 1419 1420 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; } 1421 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007 1422 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0 1423 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) 1424 { 1425 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK; 1426 } 1427 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 1428 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4 1429 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) 1430 { 1431 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK; 1432 } 1433 1434 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; } 1435 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007 1436 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0 1437 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) 1438 { 1439 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK; 1440 } 1441 1442 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; } 1443 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff 1444 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 1445 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) 1446 { 1447 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK; 1448 } 1449 1450 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; } 1451 1452 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; } 1453 1454 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } 1455 1456 #define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000 1457 1458 #define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004 1459 1460 #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010 1461 1462 #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c 1463 1464 #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028 1465 1466 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c 1467 1468 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030 1469 1470 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034 1471 1472 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038 1473 1474 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c 1475 1476 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040 1477 1478 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044 1479 1480 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048 1481 1482 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c 1483 1484 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c 1485 1486 #define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058 1487 1488 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c 1489 1490 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070 1491 1492 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074 1493 1494 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078 1495 1496 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c 1497 1498 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080 1499 1500 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084 1501 1502 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088 1503 1504 #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c 1505 1506 #define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090 1507 1508 #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094 1509 1510 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098 1511 1512 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c 1513 1514 #define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0 1515 1516 #define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4 1517 1518 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8 1519 1520 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac 1521 1522 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4 1523 1524 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8 1525 1526 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc 1527 1528 #define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0 1529 1530 #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4 1531 1532 #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc 1533 1534 #define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8 1535 1536 #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0 1537 1538 #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4 1539 1540 #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8 1541 1542 #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc 1543 1544 #define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100 1545 1546 #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104 1547 1548 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108 1549 1550 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000 1551 1552 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004 1553 1554 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008 1555 1556 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c 1557 1558 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010 1559 1560 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014 1561 1562 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018 1563 1564 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c 1565 1566 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020 1567 1568 #define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024 1569 1570 #define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028 1571 1572 #define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c 1573 1574 #define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030 1575 1576 #define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034 1577 1578 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038 1579 1580 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098 1581 1582 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c 1583 1584 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0 1585 1586 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4 1587 1588 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8 1589 1590 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac 1591 1592 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0 1593 1594 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4 1595 1596 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8 1597 1598 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc 1599 1600 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0 1601 1602 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4 1603 1604 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8 1605 1606 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc 1607 1608 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0 1609 1610 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4 1611 1612 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8 1613 1614 #define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec 1615 1616 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4 1617 1618 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8 1619 1620 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } 1621 1622 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } 1623 1624 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } 1625 1626 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } 1627 1628 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } 1629 1630 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } 1631 1632 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } 1633 1634 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } 1635 1636 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } 1637 1638 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } 1639 1640 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; } 1641 1642 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } 1643 1644 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } 1645 1646 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 1647 1648 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 1649 1650 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 1651 1652 #define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c 1653 1654 #define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020 1655 1656 #define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024 1657 1658 #define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c 1659 1660 #define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030 1661 1662 #define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054 1663 1664 #define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064 1665 1666 #define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c 1667 1668 #define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080 1669 1670 #define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094 1671 1672 #define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4 1673 1674 #define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8 1675 1676 #define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4 1677 1678 #define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc 1679 1680 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0 1681 1682 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4 1683 1684 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8 1685 1686 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c 1687 1688 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110 1689 1690 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114 1691 1692 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118 1693 1694 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c 1695 1696 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120 1697 1698 #define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c 1699 1700 #define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140 1701 1702 #define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144 1703 1704 #define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c 1705 1706 #define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154 1707 1708 #define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c 1709 1710 #define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164 1711 1712 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180 1713 1714 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184 1715 1716 #define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c 1717 1718 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0 1719 1720 1721 #endif /* DSI_XML */ 1722