1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _DP_REG_H_ 7 #define _DP_REG_H_ 8 9 /* DP_TX Registers */ 10 #define REG_DP_HW_VERSION (0x00000000) 11 12 #define REG_DP_SW_RESET (0x00000010) 13 #define DP_SW_RESET (0x00000001) 14 15 #define REG_DP_PHY_CTRL (0x00000014) 16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001) 17 #define DP_PHY_CTRL_SW_RESET (0x00000004) 18 19 #define REG_DP_CLK_CTRL (0x00000018) 20 #define REG_DP_CLK_ACTIVE (0x0000001C) 21 #define REG_DP_INTR_STATUS (0x00000020) 22 #define REG_DP_INTR_STATUS2 (0x00000024) 23 #define REG_DP_INTR_STATUS3 (0x00000028) 24 25 #define REG_DP_DP_HPD_CTRL (0x00000000) 26 #define DP_DP_HPD_CTRL_HPD_EN (0x00000001) 27 28 #define REG_DP_DP_HPD_INT_STATUS (0x00000004) 29 30 #define REG_DP_DP_HPD_INT_ACK (0x00000008) 31 #define DP_DP_HPD_PLUG_INT_ACK (0x00000001) 32 #define DP_DP_IRQ_HPD_INT_ACK (0x00000002) 33 #define DP_DP_HPD_REPLUG_INT_ACK (0x00000004) 34 #define DP_DP_HPD_UNPLUG_INT_ACK (0x00000008) 35 36 #define REG_DP_DP_HPD_INT_MASK (0x0000000C) 37 #define DP_DP_HPD_PLUG_INT_MASK (0x00000001) 38 #define DP_DP_IRQ_HPD_INT_MASK (0x00000002) 39 #define DP_DP_HPD_REPLUG_INT_MASK (0x00000004) 40 #define DP_DP_HPD_UNPLUG_INT_MASK (0x00000008) 41 #define DP_DP_HPD_INT_MASK (DP_DP_HPD_PLUG_INT_MASK | \ 42 DP_DP_IRQ_HPD_INT_MASK | \ 43 DP_DP_HPD_REPLUG_INT_MASK | \ 44 DP_DP_HPD_UNPLUG_INT_MASK) 45 #define DP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000) 46 #define DP_DP_HPD_STATE_STATUS_PENDING (0x20000000) 47 #define DP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000) 48 #define DP_DP_HPD_STATE_STATUS_MASK (0xE0000000) 49 50 #define REG_DP_DP_HPD_REFTIMER (0x00000018) 51 #define DP_DP_HPD_REFTIMER_ENABLE (1 << 16) 52 53 #define REG_DP_DP_HPD_EVENT_TIME_0 (0x0000001C) 54 #define REG_DP_DP_HPD_EVENT_TIME_1 (0x00000020) 55 #define DP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA) 56 #define DP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0) 57 58 #define REG_DP_AUX_CTRL (0x00000030) 59 #define DP_AUX_CTRL_ENABLE (0x00000001) 60 #define DP_AUX_CTRL_RESET (0x00000002) 61 62 #define REG_DP_AUX_DATA (0x00000034) 63 #define DP_AUX_DATA_READ (0x00000001) 64 #define DP_AUX_DATA_WRITE (0x00000000) 65 #define DP_AUX_DATA_OFFSET (0x00000008) 66 #define DP_AUX_DATA_INDEX_OFFSET (0x00000010) 67 #define DP_AUX_DATA_MASK (0x0000ff00) 68 #define DP_AUX_DATA_INDEX_WRITE (0x80000000) 69 70 #define REG_DP_AUX_TRANS_CTRL (0x00000038) 71 #define DP_AUX_TRANS_CTRL_I2C (0x00000100) 72 #define DP_AUX_TRANS_CTRL_GO (0x00000200) 73 #define DP_AUX_TRANS_CTRL_NO_SEND_ADDR (0x00000400) 74 #define DP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800) 75 76 #define REG_DP_TIMEOUT_COUNT (0x0000003C) 77 #define REG_DP_AUX_LIMITS (0x00000040) 78 #define REG_DP_AUX_STATUS (0x00000044) 79 80 #define DP_DPCD_CP_IRQ (0x201) 81 #define DP_DPCD_RXSTATUS (0x69493) 82 83 #define DP_INTERRUPT_TRANS_NUM (0x000000A0) 84 85 #define REG_DP_MAINLINK_CTRL (0x00000000) 86 #define DP_MAINLINK_CTRL_ENABLE (0x00000001) 87 #define DP_MAINLINK_CTRL_RESET (0x00000002) 88 #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) 89 #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) 90 91 #define REG_DP_STATE_CTRL (0x00000004) 92 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) 93 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN2 (0x00000002) 94 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN3 (0x00000004) 95 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN4 (0x00000008) 96 #define DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE (0x00000010) 97 #define DP_STATE_CTRL_LINK_PRBS7 (0x00000020) 98 #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN (0x00000040) 99 #define DP_STATE_CTRL_SEND_VIDEO (0x00000080) 100 #define DP_STATE_CTRL_PUSH_IDLE (0x00000100) 101 102 #define REG_DP_CONFIGURATION_CTRL (0x00000008) 103 #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001) 104 #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002) 105 #define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004) 106 #define DP_CONFIGURATION_CTRL_INTERLACED_BTF (0x00000008) 107 #define DP_CONFIGURATION_CTRL_NUM_OF_LANES (0x00000010) 108 #define DP_CONFIGURATION_CTRL_ENHANCED_FRAMING (0x00000040) 109 #define DP_CONFIGURATION_CTRL_SEND_VSC (0x00000080) 110 #define DP_CONFIGURATION_CTRL_BPC (0x00000100) 111 #define DP_CONFIGURATION_CTRL_ASSR (0x00000400) 112 #define DP_CONFIGURATION_CTRL_RGB_YUV (0x00000800) 113 #define DP_CONFIGURATION_CTRL_LSCLK_DIV (0x00002000) 114 #define DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT (0x04) 115 #define DP_CONFIGURATION_CTRL_BPC_SHIFT (0x08) 116 #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT (0x0D) 117 118 #define REG_DP_SOFTWARE_MVID (0x00000010) 119 #define REG_DP_SOFTWARE_NVID (0x00000018) 120 #define REG_DP_TOTAL_HOR_VER (0x0000001C) 121 #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) 122 #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) 123 #define REG_DP_ACTIVE_HOR_VER (0x00000028) 124 125 #define REG_DP_MISC1_MISC0 (0x0000002C) 126 #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) 127 #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) 128 #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) 129 130 #define REG_DP_VALID_BOUNDARY (0x00000030) 131 #define REG_DP_VALID_BOUNDARY_2 (0x00000034) 132 133 #define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING (0x00000038) 134 #define LANE0_MAPPING_SHIFT (0x00000000) 135 #define LANE1_MAPPING_SHIFT (0x00000002) 136 #define LANE2_MAPPING_SHIFT (0x00000004) 137 #define LANE3_MAPPING_SHIFT (0x00000006) 138 139 #define REG_DP_MAINLINK_READY (0x00000040) 140 #define DP_MAINLINK_READY_FOR_VIDEO (0x00000001) 141 #define DP_MAINLINK_READY_LINK_TRAINING_SHIFT (0x00000003) 142 143 #define REG_DP_MAINLINK_LEVELS (0x00000044) 144 #define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 (0x00000002) 145 146 147 #define REG_DP_TU (0x0000004C) 148 149 #define REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET (0x00000054) 150 #define DP_HBR2_ERM_PATTERN (0x00010000) 151 152 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0 (0x000000C0) 153 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0x000000C4) 154 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2 (0x000000C8) 155 156 #define MMSS_DP_MISC1_MISC0 (0x0000002C) 157 #define MMSS_DP_AUDIO_TIMING_GEN (0x00000080) 158 #define MMSS_DP_AUDIO_TIMING_RBR_32 (0x00000084) 159 #define MMSS_DP_AUDIO_TIMING_HBR_32 (0x00000088) 160 #define MMSS_DP_AUDIO_TIMING_RBR_44 (0x0000008C) 161 #define MMSS_DP_AUDIO_TIMING_HBR_44 (0x00000090) 162 #define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094) 163 #define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098) 164 165 #define MMSS_DP_PSR_CRC_RG (0x00000154) 166 #define MMSS_DP_PSR_CRC_B (0x00000158) 167 168 #define REG_DP_COMPRESSION_MODE_CTRL (0x00000180) 169 170 #define MMSS_DP_AUDIO_CFG (0x00000200) 171 #define MMSS_DP_AUDIO_STATUS (0x00000204) 172 #define MMSS_DP_AUDIO_PKT_CTRL (0x00000208) 173 #define MMSS_DP_AUDIO_PKT_CTRL2 (0x0000020C) 174 #define MMSS_DP_AUDIO_ACR_CTRL (0x00000210) 175 #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214) 176 177 #define MMSS_DP_SDP_CFG (0x00000228) 178 #define MMSS_DP_SDP_CFG2 (0x0000022C) 179 #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230) 180 #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234) 181 182 #define MMSS_DP_AUDIO_STREAM_0 (0x00000240) 183 #define MMSS_DP_AUDIO_STREAM_1 (0x00000244) 184 185 #define MMSS_DP_EXTENSION_0 (0x00000250) 186 #define MMSS_DP_EXTENSION_1 (0x00000254) 187 #define MMSS_DP_EXTENSION_2 (0x00000258) 188 #define MMSS_DP_EXTENSION_3 (0x0000025C) 189 #define MMSS_DP_EXTENSION_4 (0x00000260) 190 #define MMSS_DP_EXTENSION_5 (0x00000264) 191 #define MMSS_DP_EXTENSION_6 (0x00000268) 192 #define MMSS_DP_EXTENSION_7 (0x0000026C) 193 #define MMSS_DP_EXTENSION_8 (0x00000270) 194 #define MMSS_DP_EXTENSION_9 (0x00000274) 195 #define MMSS_DP_AUDIO_COPYMANAGEMENT_0 (0x00000278) 196 #define MMSS_DP_AUDIO_COPYMANAGEMENT_1 (0x0000027C) 197 #define MMSS_DP_AUDIO_COPYMANAGEMENT_2 (0x00000280) 198 #define MMSS_DP_AUDIO_COPYMANAGEMENT_3 (0x00000284) 199 #define MMSS_DP_AUDIO_COPYMANAGEMENT_4 (0x00000288) 200 #define MMSS_DP_AUDIO_COPYMANAGEMENT_5 (0x0000028C) 201 #define MMSS_DP_AUDIO_ISRC_0 (0x00000290) 202 #define MMSS_DP_AUDIO_ISRC_1 (0x00000294) 203 #define MMSS_DP_AUDIO_ISRC_2 (0x00000298) 204 #define MMSS_DP_AUDIO_ISRC_3 (0x0000029C) 205 #define MMSS_DP_AUDIO_ISRC_4 (0x000002A0) 206 #define MMSS_DP_AUDIO_ISRC_5 (0x000002A4) 207 #define MMSS_DP_AUDIO_INFOFRAME_0 (0x000002A8) 208 #define MMSS_DP_AUDIO_INFOFRAME_1 (0x000002AC) 209 #define MMSS_DP_AUDIO_INFOFRAME_2 (0x000002B0) 210 211 #define MMSS_DP_GENERIC0_0 (0x00000300) 212 #define MMSS_DP_GENERIC0_1 (0x00000304) 213 #define MMSS_DP_GENERIC0_2 (0x00000308) 214 #define MMSS_DP_GENERIC0_3 (0x0000030C) 215 #define MMSS_DP_GENERIC0_4 (0x00000310) 216 #define MMSS_DP_GENERIC0_5 (0x00000314) 217 #define MMSS_DP_GENERIC0_6 (0x00000318) 218 #define MMSS_DP_GENERIC0_7 (0x0000031C) 219 #define MMSS_DP_GENERIC0_8 (0x00000320) 220 #define MMSS_DP_GENERIC0_9 (0x00000324) 221 #define MMSS_DP_GENERIC1_0 (0x00000328) 222 #define MMSS_DP_GENERIC1_1 (0x0000032C) 223 #define MMSS_DP_GENERIC1_2 (0x00000330) 224 #define MMSS_DP_GENERIC1_3 (0x00000334) 225 #define MMSS_DP_GENERIC1_4 (0x00000338) 226 #define MMSS_DP_GENERIC1_5 (0x0000033C) 227 #define MMSS_DP_GENERIC1_6 (0x00000340) 228 #define MMSS_DP_GENERIC1_7 (0x00000344) 229 #define MMSS_DP_GENERIC1_8 (0x00000348) 230 #define MMSS_DP_GENERIC1_9 (0x0000034C) 231 232 #define MMSS_DP_VSCEXT_0 (0x000002D0) 233 #define MMSS_DP_VSCEXT_1 (0x000002D4) 234 #define MMSS_DP_VSCEXT_2 (0x000002D8) 235 #define MMSS_DP_VSCEXT_3 (0x000002DC) 236 #define MMSS_DP_VSCEXT_4 (0x000002E0) 237 #define MMSS_DP_VSCEXT_5 (0x000002E4) 238 #define MMSS_DP_VSCEXT_6 (0x000002E8) 239 #define MMSS_DP_VSCEXT_7 (0x000002EC) 240 #define MMSS_DP_VSCEXT_8 (0x000002F0) 241 #define MMSS_DP_VSCEXT_9 (0x000002F4) 242 243 #define MMSS_DP_BIST_ENABLE (0x00000000) 244 #define DP_BIST_ENABLE_DPBIST_EN (0x00000001) 245 246 #define MMSS_DP_TIMING_ENGINE_EN (0x00000010) 247 #define DP_TIMING_ENGINE_EN_EN (0x00000001) 248 249 #define MMSS_DP_INTF_CONFIG (0x00000014) 250 #define MMSS_DP_INTF_HSYNC_CTL (0x00000018) 251 #define MMSS_DP_INTF_VSYNC_PERIOD_F0 (0x0000001C) 252 #define MMSS_DP_INTF_VSYNC_PERIOD_F1 (0x00000020) 253 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0 (0x00000024) 254 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1 (0x00000028) 255 #define MMSS_INTF_DISPLAY_V_START_F0 (0x0000002C) 256 #define MMSS_INTF_DISPLAY_V_START_F1 (0x00000030) 257 #define MMSS_DP_INTF_DISPLAY_V_END_F0 (0x00000034) 258 #define MMSS_DP_INTF_DISPLAY_V_END_F1 (0x00000038) 259 #define MMSS_DP_INTF_ACTIVE_V_START_F0 (0x0000003C) 260 #define MMSS_DP_INTF_ACTIVE_V_START_F1 (0x00000040) 261 #define MMSS_DP_INTF_ACTIVE_V_END_F0 (0x00000044) 262 #define MMSS_DP_INTF_ACTIVE_V_END_F1 (0x00000048) 263 #define MMSS_DP_INTF_DISPLAY_HCTL (0x0000004C) 264 #define MMSS_DP_INTF_ACTIVE_HCTL (0x00000050) 265 #define MMSS_DP_INTF_POLARITY_CTL (0x00000058) 266 267 #define MMSS_DP_TPG_MAIN_CONTROL (0x00000060) 268 #define MMSS_DP_DSC_DTO (0x0000007C) 269 #define DP_TPG_CHECKERED_RECT_PATTERN (0x00000100) 270 271 #define MMSS_DP_TPG_VIDEO_CONFIG (0x00000064) 272 #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) 273 #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) 274 275 #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) 276 277 #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) 278 #define REG_DP_PHY_AUX_BIST_CFG (0x00000050) 279 #define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC) 280 281 /* DP HDCP 1.3 registers */ 282 #define DP_HDCP_CTRL (0x0A0) 283 #define DP_HDCP_STATUS (0x0A4) 284 #define DP_HDCP_SW_UPPER_AKSV (0x098) 285 #define DP_HDCP_SW_LOWER_AKSV (0x09C) 286 #define DP_HDCP_ENTROPY_CTRL0 (0x350) 287 #define DP_HDCP_ENTROPY_CTRL1 (0x35C) 288 #define DP_HDCP_SHA_STATUS (0x0C8) 289 #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0) 290 #define DP_HDCP_RCVPORT_DATA3 (0x0A4) 291 #define DP_HDCP_RCVPORT_DATA4 (0x0A8) 292 #define DP_HDCP_RCVPORT_DATA5 (0x0C0) 293 #define DP_HDCP_RCVPORT_DATA6 (0x0C4) 294 295 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024) 296 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA (0x028) 297 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004) 298 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008) 299 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C) 300 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010) 301 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014) 302 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) 303 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) 304 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) 305 306 #endif /* _DP_REG_H_ */ 307