1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ 7 8 #include <linux/types.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/phy/phy.h> 12 #include <linux/phy/phy-dp.h> 13 #include <linux/pm_opp.h> 14 15 #include <drm/display/drm_dp_helper.h> 16 #include <drm/drm_fixed.h> 17 #include <drm/drm_print.h> 18 19 #include "dp_reg.h" 20 #include "dp_ctrl.h" 21 #include "dp_link.h" 22 23 #define DP_KHZ_TO_HZ 1000 24 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ 25 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) 26 27 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) 28 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) 29 30 #define MR_LINK_TRAINING1 0x8 31 #define MR_LINK_SYMBOL_ERM 0x80 32 #define MR_LINK_PRBS7 0x100 33 #define MR_LINK_CUSTOM80 0x200 34 #define MR_LINK_TRAINING4 0x40 35 36 enum { 37 DP_TRAINING_NONE, 38 DP_TRAINING_1, 39 DP_TRAINING_2, 40 }; 41 42 struct dp_tu_calc_input { 43 u64 lclk; /* 162, 270, 540 and 810 */ 44 u64 pclk_khz; /* in KHz */ 45 u64 hactive; /* active h-width */ 46 u64 hporch; /* bp + fp + pulse */ 47 int nlanes; /* no.of.lanes */ 48 int bpp; /* bits */ 49 int pixel_enc; /* 444, 420, 422 */ 50 int dsc_en; /* dsc on/off */ 51 int async_en; /* async mode */ 52 int fec_en; /* fec */ 53 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ 54 int num_of_dsc_slices; /* number of slices per line */ 55 }; 56 57 struct dp_vc_tu_mapping_table { 58 u32 vic; 59 u8 lanes; 60 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ 61 u8 bpp; 62 u8 valid_boundary_link; 63 u16 delay_start_link; 64 bool boundary_moderation_en; 65 u8 valid_lower_boundary_link; 66 u8 upper_boundary_count; 67 u8 lower_boundary_count; 68 u8 tu_size_minus1; 69 }; 70 71 struct dp_ctrl_private { 72 struct dp_ctrl dp_ctrl; 73 struct drm_device *drm_dev; 74 struct device *dev; 75 struct drm_dp_aux *aux; 76 struct dp_panel *panel; 77 struct dp_link *link; 78 struct dp_power *power; 79 struct dp_parser *parser; 80 struct dp_catalog *catalog; 81 82 struct completion idle_comp; 83 struct completion video_comp; 84 }; 85 86 static int dp_aux_link_configure(struct drm_dp_aux *aux, 87 struct dp_link_info *link) 88 { 89 u8 values[2]; 90 int err; 91 92 values[0] = drm_dp_link_rate_to_bw_code(link->rate); 93 values[1] = link->num_lanes; 94 95 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 96 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 97 98 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); 99 if (err < 0) 100 return err; 101 102 return 0; 103 } 104 105 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) 106 { 107 struct dp_ctrl_private *ctrl; 108 109 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 110 111 reinit_completion(&ctrl->idle_comp); 112 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); 113 114 if (!wait_for_completion_timeout(&ctrl->idle_comp, 115 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) 116 pr_warn("PUSH_IDLE pattern timedout\n"); 117 118 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); 119 } 120 121 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) 122 { 123 u32 config = 0, tbd; 124 const u8 *dpcd = ctrl->panel->dpcd; 125 126 /* Default-> LSCLK DIV: 1/4 LCLK */ 127 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); 128 129 /* Scrambler reset enable */ 130 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) 131 config |= DP_CONFIGURATION_CTRL_ASSR; 132 133 tbd = dp_link_get_test_bits_depth(ctrl->link, 134 ctrl->panel->dp_mode.bpp); 135 136 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) { 137 pr_debug("BIT_DEPTH not set. Configure default\n"); 138 tbd = DP_TEST_BIT_DEPTH_8; 139 } 140 141 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; 142 143 /* Num of Lanes */ 144 config |= ((ctrl->link->link_params.num_lanes - 1) 145 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); 146 147 if (drm_dp_enhanced_frame_cap(dpcd)) 148 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; 149 150 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ 151 152 /* sync clock & static Mvid */ 153 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; 154 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; 155 156 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); 157 } 158 159 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) 160 { 161 u32 cc, tb; 162 163 dp_catalog_ctrl_lane_mapping(ctrl->catalog); 164 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 165 166 dp_ctrl_config_ctrl(ctrl); 167 168 tb = dp_link_get_test_bits_depth(ctrl->link, 169 ctrl->panel->dp_mode.bpp); 170 cc = dp_link_get_colorimetry_config(ctrl->link); 171 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); 172 dp_panel_timing_cfg(ctrl->panel); 173 } 174 175 /* 176 * The structure and few functions present below are IP/Hardware 177 * specific implementation. Most of the implementation will not 178 * have coding comments 179 */ 180 struct tu_algo_data { 181 s64 lclk_fp; 182 s64 pclk_fp; 183 s64 lwidth; 184 s64 lwidth_fp; 185 s64 hbp_relative_to_pclk; 186 s64 hbp_relative_to_pclk_fp; 187 int nlanes; 188 int bpp; 189 int pixelEnc; 190 int dsc_en; 191 int async_en; 192 int bpc; 193 194 uint delay_start_link_extra_pixclk; 195 int extra_buffer_margin; 196 s64 ratio_fp; 197 s64 original_ratio_fp; 198 199 s64 err_fp; 200 s64 n_err_fp; 201 s64 n_n_err_fp; 202 int tu_size; 203 int tu_size_desired; 204 int tu_size_minus1; 205 206 int valid_boundary_link; 207 s64 resulting_valid_fp; 208 s64 total_valid_fp; 209 s64 effective_valid_fp; 210 s64 effective_valid_recorded_fp; 211 int n_tus; 212 int n_tus_per_lane; 213 int paired_tus; 214 int remainder_tus; 215 int remainder_tus_upper; 216 int remainder_tus_lower; 217 int extra_bytes; 218 int filler_size; 219 int delay_start_link; 220 221 int extra_pclk_cycles; 222 int extra_pclk_cycles_in_link_clk; 223 s64 ratio_by_tu_fp; 224 s64 average_valid2_fp; 225 int new_valid_boundary_link; 226 int remainder_symbols_exist; 227 int n_symbols; 228 s64 n_remainder_symbols_per_lane_fp; 229 s64 last_partial_tu_fp; 230 s64 TU_ratio_err_fp; 231 232 int n_tus_incl_last_incomplete_tu; 233 int extra_pclk_cycles_tmp; 234 int extra_pclk_cycles_in_link_clk_tmp; 235 int extra_required_bytes_new_tmp; 236 int filler_size_tmp; 237 int lower_filler_size_tmp; 238 int delay_start_link_tmp; 239 240 bool boundary_moderation_en; 241 int boundary_mod_lower_err; 242 int upper_boundary_count; 243 int lower_boundary_count; 244 int i_upper_boundary_count; 245 int i_lower_boundary_count; 246 int valid_lower_boundary_link; 247 int even_distribution_BF; 248 int even_distribution_legacy; 249 int even_distribution; 250 int min_hblank_violated; 251 s64 delay_start_time_fp; 252 s64 hbp_time_fp; 253 s64 hactive_time_fp; 254 s64 diff_abs_fp; 255 256 s64 ratio; 257 }; 258 259 static int _tu_param_compare(s64 a, s64 b) 260 { 261 u32 a_sign; 262 u32 b_sign; 263 s64 a_temp, b_temp, minus_1; 264 265 if (a == b) 266 return 0; 267 268 minus_1 = drm_fixp_from_fraction(-1, 1); 269 270 a_sign = (a >> 32) & 0x80000000 ? 1 : 0; 271 272 b_sign = (b >> 32) & 0x80000000 ? 1 : 0; 273 274 if (a_sign > b_sign) 275 return 2; 276 else if (b_sign > a_sign) 277 return 1; 278 279 if (!a_sign && !b_sign) { /* positive */ 280 if (a > b) 281 return 1; 282 else 283 return 2; 284 } else { /* negative */ 285 a_temp = drm_fixp_mul(a, minus_1); 286 b_temp = drm_fixp_mul(b, minus_1); 287 288 if (a_temp > b_temp) 289 return 2; 290 else 291 return 1; 292 } 293 } 294 295 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in, 296 struct tu_algo_data *tu) 297 { 298 int nlanes = in->nlanes; 299 int dsc_num_slices = in->num_of_dsc_slices; 300 int dsc_num_bytes = 0; 301 int numerator; 302 s64 pclk_dsc_fp; 303 s64 dwidth_dsc_fp; 304 s64 hbp_dsc_fp; 305 306 int tot_num_eoc_symbols = 0; 307 int tot_num_hor_bytes = 0; 308 int tot_num_dummy_bytes = 0; 309 int dwidth_dsc_bytes = 0; 310 int eoc_bytes = 0; 311 312 s64 temp1_fp, temp2_fp, temp3_fp; 313 314 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); 315 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); 316 tu->lwidth = in->hactive; 317 tu->hbp_relative_to_pclk = in->hporch; 318 tu->nlanes = in->nlanes; 319 tu->bpp = in->bpp; 320 tu->pixelEnc = in->pixel_enc; 321 tu->dsc_en = in->dsc_en; 322 tu->async_en = in->async_en; 323 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); 324 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); 325 326 if (tu->pixelEnc == 420) { 327 temp1_fp = drm_fixp_from_fraction(2, 1); 328 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); 329 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); 330 tu->hbp_relative_to_pclk_fp = 331 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); 332 } 333 334 if (tu->pixelEnc == 422) { 335 switch (tu->bpp) { 336 case 24: 337 tu->bpp = 16; 338 tu->bpc = 8; 339 break; 340 case 30: 341 tu->bpp = 20; 342 tu->bpc = 10; 343 break; 344 default: 345 tu->bpp = 16; 346 tu->bpc = 8; 347 break; 348 } 349 } else { 350 tu->bpc = tu->bpp/3; 351 } 352 353 if (!in->dsc_en) 354 goto fec_check; 355 356 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); 357 temp2_fp = drm_fixp_from_fraction(in->bpp, 1); 358 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 359 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); 360 361 temp1_fp = drm_fixp_from_fraction(8, 1); 362 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 363 364 numerator = drm_fixp2int(temp3_fp); 365 366 dsc_num_bytes = numerator / dsc_num_slices; 367 eoc_bytes = dsc_num_bytes % nlanes; 368 tot_num_eoc_symbols = nlanes * dsc_num_slices; 369 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; 370 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; 371 372 if (dsc_num_bytes == 0) 373 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); 374 375 dwidth_dsc_bytes = (tot_num_hor_bytes + 376 tot_num_eoc_symbols + 377 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); 378 379 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); 380 381 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); 382 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); 383 pclk_dsc_fp = temp1_fp; 384 385 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); 386 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); 387 hbp_dsc_fp = temp2_fp; 388 389 /* output */ 390 tu->pclk_fp = pclk_dsc_fp; 391 tu->lwidth_fp = dwidth_dsc_fp; 392 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; 393 394 fec_check: 395 if (in->fec_en) { 396 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ 397 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); 398 } 399 } 400 401 static void _tu_valid_boundary_calc(struct tu_algo_data *tu) 402 { 403 s64 temp1_fp, temp2_fp, temp, temp1, temp2; 404 int compare_result_1, compare_result_2, compare_result_3; 405 406 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 407 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 408 409 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 410 411 temp = (tu->i_upper_boundary_count * 412 tu->new_valid_boundary_link + 413 tu->i_lower_boundary_count * 414 (tu->new_valid_boundary_link-1)); 415 tu->average_valid2_fp = drm_fixp_from_fraction(temp, 416 (tu->i_upper_boundary_count + 417 tu->i_lower_boundary_count)); 418 419 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 420 temp2_fp = tu->lwidth_fp; 421 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 422 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 423 tu->n_tus = drm_fixp2int(temp2_fp); 424 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 425 tu->n_tus += 1; 426 427 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); 428 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); 429 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); 430 temp2_fp = temp1_fp - temp2_fp; 431 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 432 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 433 tu->n_remainder_symbols_per_lane_fp = temp2_fp; 434 435 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 436 tu->last_partial_tu_fp = 437 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, 438 temp1_fp); 439 440 if (tu->n_remainder_symbols_per_lane_fp != 0) 441 tu->remainder_symbols_exist = 1; 442 else 443 tu->remainder_symbols_exist = 0; 444 445 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); 446 tu->n_tus_per_lane = drm_fixp2int(temp1_fp); 447 448 tu->paired_tus = (int)((tu->n_tus_per_lane) / 449 (tu->i_upper_boundary_count + 450 tu->i_lower_boundary_count)); 451 452 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * 453 (tu->i_upper_boundary_count + 454 tu->i_lower_boundary_count); 455 456 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { 457 tu->remainder_tus_upper = tu->i_upper_boundary_count; 458 tu->remainder_tus_lower = tu->remainder_tus - 459 tu->i_upper_boundary_count; 460 } else { 461 tu->remainder_tus_upper = tu->remainder_tus; 462 tu->remainder_tus_lower = 0; 463 } 464 465 temp = tu->paired_tus * (tu->i_upper_boundary_count * 466 tu->new_valid_boundary_link + 467 tu->i_lower_boundary_count * 468 (tu->new_valid_boundary_link - 1)) + 469 (tu->remainder_tus_upper * 470 tu->new_valid_boundary_link) + 471 (tu->remainder_tus_lower * 472 (tu->new_valid_boundary_link - 1)); 473 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); 474 475 if (tu->remainder_symbols_exist) { 476 temp1_fp = tu->total_valid_fp + 477 tu->n_remainder_symbols_per_lane_fp; 478 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 479 temp2_fp = temp2_fp + tu->last_partial_tu_fp; 480 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); 481 } else { 482 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 483 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); 484 } 485 tu->effective_valid_fp = temp1_fp; 486 487 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 488 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 489 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; 490 491 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 492 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 493 tu->n_err_fp = tu->average_valid2_fp - temp2_fp; 494 495 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 496 497 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 498 temp2_fp = tu->lwidth_fp; 499 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 500 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 501 502 if (temp2_fp) 503 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); 504 else 505 tu->n_tus_incl_last_incomplete_tu = 0; 506 507 temp1 = 0; 508 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 509 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 510 temp1_fp = tu->average_valid2_fp - temp2_fp; 511 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); 512 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 513 514 if (temp1_fp) 515 temp1 = drm_fixp2int_ceil(temp1_fp); 516 517 temp = tu->i_upper_boundary_count * tu->nlanes; 518 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 519 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 520 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); 521 temp2_fp = temp1_fp - temp2_fp; 522 temp1_fp = drm_fixp_from_fraction(temp, 1); 523 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 524 525 if (temp2_fp) 526 temp2 = drm_fixp2int_ceil(temp2_fp); 527 else 528 temp2 = 0; 529 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); 530 531 temp1_fp = drm_fixp_from_fraction(8, tu->bpp); 532 temp2_fp = drm_fixp_from_fraction( 533 tu->extra_required_bytes_new_tmp, 1); 534 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 535 536 if (temp1_fp) 537 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); 538 else 539 tu->extra_pclk_cycles_tmp = 0; 540 541 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); 542 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 543 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 544 545 if (temp1_fp) 546 tu->extra_pclk_cycles_in_link_clk_tmp = 547 drm_fixp2int_ceil(temp1_fp); 548 else 549 tu->extra_pclk_cycles_in_link_clk_tmp = 0; 550 551 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; 552 553 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; 554 555 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + 556 tu->lower_filler_size_tmp + 557 tu->extra_buffer_margin; 558 559 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); 560 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 561 562 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); 563 if (compare_result_1 == 2) 564 compare_result_1 = 1; 565 else 566 compare_result_1 = 0; 567 568 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); 569 if (compare_result_2 == 2) 570 compare_result_2 = 1; 571 else 572 compare_result_2 = 0; 573 574 compare_result_3 = _tu_param_compare(tu->hbp_time_fp, 575 tu->delay_start_time_fp); 576 if (compare_result_3 == 2) 577 compare_result_3 = 0; 578 else 579 compare_result_3 = 1; 580 581 if (((tu->even_distribution == 1) || 582 ((tu->even_distribution_BF == 0) && 583 (tu->even_distribution_legacy == 0))) && 584 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && 585 compare_result_2 && 586 (compare_result_1 || (tu->min_hblank_violated == 1)) && 587 (tu->new_valid_boundary_link - 1) > 0 && 588 compare_result_3 && 589 (tu->delay_start_link_tmp <= 1023)) { 590 tu->upper_boundary_count = tu->i_upper_boundary_count; 591 tu->lower_boundary_count = tu->i_lower_boundary_count; 592 tu->err_fp = tu->n_n_err_fp; 593 tu->boundary_moderation_en = true; 594 tu->tu_size_desired = tu->tu_size; 595 tu->valid_boundary_link = tu->new_valid_boundary_link; 596 tu->effective_valid_recorded_fp = tu->effective_valid_fp; 597 tu->even_distribution_BF = 1; 598 tu->delay_start_link = tu->delay_start_link_tmp; 599 } else if (tu->boundary_mod_lower_err == 0) { 600 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, 601 tu->diff_abs_fp); 602 if (compare_result_1 == 2) 603 tu->boundary_mod_lower_err = 1; 604 } 605 } 606 607 static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl, 608 struct dp_tu_calc_input *in, 609 struct dp_vc_tu_mapping_table *tu_table) 610 { 611 struct tu_algo_data *tu; 612 int compare_result_1, compare_result_2; 613 u64 temp = 0; 614 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; 615 616 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ 617 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */ 618 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */ 619 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); 620 621 u8 DP_BRUTE_FORCE = 1; 622 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ 623 uint EXTRA_PIXCLK_CYCLE_DELAY = 4; 624 uint HBLANK_MARGIN = 4; 625 626 tu = kzalloc(sizeof(*tu), GFP_KERNEL); 627 if (!tu) 628 return; 629 630 dp_panel_update_tu_timings(in, tu); 631 632 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ 633 634 temp1_fp = drm_fixp_from_fraction(4, 1); 635 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); 636 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); 637 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp); 638 639 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 640 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp); 641 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 642 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 643 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp); 644 645 tu->original_ratio_fp = tu->ratio_fp; 646 tu->boundary_moderation_en = false; 647 tu->upper_boundary_count = 0; 648 tu->lower_boundary_count = 0; 649 tu->i_upper_boundary_count = 0; 650 tu->i_lower_boundary_count = 0; 651 tu->valid_lower_boundary_link = 0; 652 tu->even_distribution_BF = 0; 653 tu->even_distribution_legacy = 0; 654 tu->even_distribution = 0; 655 tu->delay_start_time_fp = 0; 656 657 tu->err_fp = drm_fixp_from_fraction(1000, 1); 658 tu->n_err_fp = 0; 659 tu->n_n_err_fp = 0; 660 661 tu->ratio = drm_fixp2int(tu->ratio_fp); 662 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 663 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp); 664 if (temp2_fp != 0 && 665 !tu->ratio && tu->dsc_en == 0) { 666 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp); 667 tu->ratio = drm_fixp2int(tu->ratio_fp); 668 if (tu->ratio) 669 tu->ratio_fp = drm_fixp_from_fraction(1, 1); 670 } 671 672 if (tu->ratio > 1) 673 tu->ratio = 1; 674 675 if (tu->ratio == 1) 676 goto tu_size_calc; 677 678 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp); 679 if (!compare_result_1 || compare_result_1 == 1) 680 compare_result_1 = 1; 681 else 682 compare_result_1 = 0; 683 684 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp); 685 if (!compare_result_2 || compare_result_2 == 2) 686 compare_result_2 = 1; 687 else 688 compare_result_2 = 0; 689 690 if (tu->dsc_en && compare_result_1 && compare_result_2) { 691 HBLANK_MARGIN += 4; 692 drm_dbg_dp(ctrl->drm_dev, 693 "increase HBLANK_MARGIN to %d\n", HBLANK_MARGIN); 694 } 695 696 tu_size_calc: 697 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 698 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 699 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 700 temp = drm_fixp2int_ceil(temp2_fp); 701 temp1_fp = drm_fixp_from_fraction(temp, 1); 702 tu->n_err_fp = temp1_fp - temp2_fp; 703 704 if (tu->n_err_fp < tu->err_fp) { 705 tu->err_fp = tu->n_err_fp; 706 tu->tu_size_desired = tu->tu_size; 707 } 708 } 709 710 tu->tu_size_minus1 = tu->tu_size_desired - 1; 711 712 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 713 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 714 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 715 716 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 717 temp2_fp = tu->lwidth_fp; 718 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); 719 720 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 721 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 722 tu->n_tus = drm_fixp2int(temp2_fp); 723 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 724 tu->n_tus += 1; 725 726 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 727 728 drm_dbg_dp(ctrl->drm_dev, 729 "n_sym = %d, num_of_tus = %d\n", 730 tu->valid_boundary_link, tu->n_tus); 731 732 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 733 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 734 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 735 temp2_fp = temp1_fp - temp2_fp; 736 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); 737 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 738 739 temp = drm_fixp2int(temp2_fp); 740 if (temp && temp2_fp) 741 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp); 742 else 743 tu->extra_bytes = 0; 744 745 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); 746 temp2_fp = drm_fixp_from_fraction(8, tu->bpp); 747 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 748 749 if (temp && temp1_fp) 750 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); 751 else 752 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp); 753 754 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 755 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); 756 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 757 758 if (temp1_fp) 759 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); 760 else 761 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); 762 763 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; 764 765 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 766 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 767 768 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + 769 tu->filler_size + tu->extra_buffer_margin; 770 771 tu->resulting_valid_fp = 772 drm_fixp_from_fraction(tu->valid_boundary_link, 1); 773 774 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 775 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 776 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 777 778 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1); 779 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; 780 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp); 781 782 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 783 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 784 785 compare_result_1 = _tu_param_compare(tu->hbp_time_fp, 786 tu->delay_start_time_fp); 787 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ 788 tu->min_hblank_violated = 1; 789 790 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp); 791 792 compare_result_2 = _tu_param_compare(tu->hactive_time_fp, 793 tu->delay_start_time_fp); 794 if (compare_result_2 == 2) 795 tu->min_hblank_violated = 1; 796 797 tu->delay_start_time_fp = 0; 798 799 /* brute force */ 800 801 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; 802 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; 803 804 temp = drm_fixp2int(tu->diff_abs_fp); 805 if (!temp && tu->diff_abs_fp <= 0xffff) 806 tu->diff_abs_fp = 0; 807 808 /* if(diff_abs < 0) diff_abs *= -1 */ 809 if (tu->diff_abs_fp < 0) 810 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1); 811 812 tu->boundary_mod_lower_err = 0; 813 if ((tu->diff_abs_fp != 0 && 814 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || 815 (tu->even_distribution_legacy == 0) || 816 (DP_BRUTE_FORCE == 1))) || 817 (tu->min_hblank_violated == 1)) { 818 do { 819 tu->err_fp = drm_fixp_from_fraction(1000, 1); 820 821 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 822 temp2_fp = drm_fixp_from_fraction( 823 tu->delay_start_link_extra_pixclk, 1); 824 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 825 826 if (temp1_fp) 827 tu->extra_buffer_margin = 828 drm_fixp2int_ceil(temp1_fp); 829 else 830 tu->extra_buffer_margin = 0; 831 832 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 833 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 834 835 if (temp1_fp) 836 tu->n_symbols = drm_fixp2int_ceil(temp1_fp); 837 else 838 tu->n_symbols = 0; 839 840 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 841 for (tu->i_upper_boundary_count = 1; 842 tu->i_upper_boundary_count <= 15; 843 tu->i_upper_boundary_count++) { 844 for (tu->i_lower_boundary_count = 1; 845 tu->i_lower_boundary_count <= 15; 846 tu->i_lower_boundary_count++) { 847 _tu_valid_boundary_calc(tu); 848 } 849 } 850 } 851 tu->delay_start_link_extra_pixclk--; 852 } while (tu->boundary_moderation_en != true && 853 tu->boundary_mod_lower_err == 1 && 854 tu->delay_start_link_extra_pixclk != 0); 855 856 if (tu->boundary_moderation_en == true) { 857 temp1_fp = drm_fixp_from_fraction( 858 (tu->upper_boundary_count * 859 tu->valid_boundary_link + 860 tu->lower_boundary_count * 861 (tu->valid_boundary_link - 1)), 1); 862 temp2_fp = drm_fixp_from_fraction( 863 (tu->upper_boundary_count + 864 tu->lower_boundary_count), 1); 865 tu->resulting_valid_fp = 866 drm_fixp_div(temp1_fp, temp2_fp); 867 868 temp1_fp = drm_fixp_from_fraction( 869 tu->tu_size_desired, 1); 870 tu->ratio_by_tu_fp = 871 drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 872 873 tu->valid_lower_boundary_link = 874 tu->valid_boundary_link - 1; 875 876 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 877 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 878 temp2_fp = drm_fixp_div(temp1_fp, 879 tu->resulting_valid_fp); 880 tu->n_tus = drm_fixp2int(temp2_fp); 881 882 tu->tu_size_minus1 = tu->tu_size_desired - 1; 883 tu->even_distribution_BF = 1; 884 885 temp1_fp = 886 drm_fixp_from_fraction(tu->tu_size_desired, 1); 887 temp2_fp = 888 drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 889 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 890 } 891 } 892 893 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp); 894 895 if (temp2_fp) 896 temp = drm_fixp2int_ceil(temp2_fp); 897 else 898 temp = 0; 899 900 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 901 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 902 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 903 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); 904 temp1_fp = drm_fixp_from_fraction(temp, 1); 905 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 906 temp = drm_fixp2int(temp2_fp); 907 908 if (tu->async_en) 909 tu->delay_start_link += (int)temp; 910 911 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 912 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 913 914 /* OUTPUTS */ 915 tu_table->valid_boundary_link = tu->valid_boundary_link; 916 tu_table->delay_start_link = tu->delay_start_link; 917 tu_table->boundary_moderation_en = tu->boundary_moderation_en; 918 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; 919 tu_table->upper_boundary_count = tu->upper_boundary_count; 920 tu_table->lower_boundary_count = tu->lower_boundary_count; 921 tu_table->tu_size_minus1 = tu->tu_size_minus1; 922 923 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n", 924 tu_table->valid_boundary_link); 925 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n", 926 tu_table->delay_start_link); 927 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n", 928 tu_table->boundary_moderation_en); 929 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n", 930 tu_table->valid_lower_boundary_link); 931 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n", 932 tu_table->upper_boundary_count); 933 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n", 934 tu_table->lower_boundary_count); 935 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n", 936 tu_table->tu_size_minus1); 937 938 kfree(tu); 939 } 940 941 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, 942 struct dp_vc_tu_mapping_table *tu_table) 943 { 944 struct dp_tu_calc_input in; 945 struct drm_display_mode *drm_mode; 946 947 drm_mode = &ctrl->panel->dp_mode.drm_mode; 948 949 in.lclk = ctrl->link->link_params.rate / 1000; 950 in.pclk_khz = drm_mode->clock; 951 in.hactive = drm_mode->hdisplay; 952 in.hporch = drm_mode->htotal - drm_mode->hdisplay; 953 in.nlanes = ctrl->link->link_params.num_lanes; 954 in.bpp = ctrl->panel->dp_mode.bpp; 955 in.pixel_enc = 444; 956 in.dsc_en = 0; 957 in.async_en = 0; 958 in.fec_en = 0; 959 in.num_of_dsc_slices = 0; 960 in.compress_ratio = 100; 961 962 _dp_ctrl_calc_tu(ctrl, &in, tu_table); 963 } 964 965 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl) 966 { 967 u32 dp_tu = 0x0; 968 u32 valid_boundary = 0x0; 969 u32 valid_boundary2 = 0x0; 970 struct dp_vc_tu_mapping_table tu_calc_table; 971 972 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); 973 974 dp_tu |= tu_calc_table.tu_size_minus1; 975 valid_boundary |= tu_calc_table.valid_boundary_link; 976 valid_boundary |= (tu_calc_table.delay_start_link << 16); 977 978 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); 979 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); 980 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); 981 982 if (tu_calc_table.boundary_moderation_en) 983 valid_boundary2 |= BIT(0); 984 985 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", 986 dp_tu, valid_boundary, valid_boundary2); 987 988 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, 989 dp_tu, valid_boundary, valid_boundary2); 990 } 991 992 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) 993 { 994 int ret = 0; 995 996 if (!wait_for_completion_timeout(&ctrl->video_comp, 997 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { 998 DRM_ERROR("wait4video timedout\n"); 999 ret = -ETIMEDOUT; 1000 } 1001 return ret; 1002 } 1003 1004 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) 1005 { 1006 struct dp_link *link = ctrl->link; 1007 int ret = 0, lane, lane_cnt; 1008 u8 buf[4]; 1009 u32 max_level_reached = 0; 1010 u32 voltage_swing_level = link->phy_params.v_level; 1011 u32 pre_emphasis_level = link->phy_params.p_level; 1012 1013 drm_dbg_dp(ctrl->drm_dev, 1014 "voltage level: %d emphasis level: %d\n", 1015 voltage_swing_level, pre_emphasis_level); 1016 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, 1017 voltage_swing_level, pre_emphasis_level); 1018 1019 if (ret) 1020 return ret; 1021 1022 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) { 1023 drm_dbg_dp(ctrl->drm_dev, 1024 "max. voltage swing level reached %d\n", 1025 voltage_swing_level); 1026 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; 1027 } 1028 1029 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) { 1030 drm_dbg_dp(ctrl->drm_dev, 1031 "max. pre-emphasis level reached %d\n", 1032 pre_emphasis_level); 1033 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1034 } 1035 1036 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; 1037 1038 lane_cnt = ctrl->link->link_params.num_lanes; 1039 for (lane = 0; lane < lane_cnt; lane++) 1040 buf[lane] = voltage_swing_level | pre_emphasis_level 1041 | max_level_reached; 1042 1043 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n", 1044 voltage_swing_level | pre_emphasis_level); 1045 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET, 1046 buf, lane_cnt); 1047 if (ret == lane_cnt) 1048 ret = 0; 1049 1050 return ret; 1051 } 1052 1053 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, 1054 u8 pattern) 1055 { 1056 u8 buf; 1057 int ret = 0; 1058 1059 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern); 1060 1061 buf = pattern; 1062 1063 if (pattern && pattern != DP_TRAINING_PATTERN_4) 1064 buf |= DP_LINK_SCRAMBLING_DISABLE; 1065 1066 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf); 1067 return ret == 1; 1068 } 1069 1070 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, 1071 u8 *link_status) 1072 { 1073 int ret = 0, len; 1074 1075 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 1076 if (len != DP_LINK_STATUS_SIZE) { 1077 DRM_ERROR("DP link status read failed, err: %d\n", len); 1078 ret = -EINVAL; 1079 } 1080 1081 return ret; 1082 } 1083 1084 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, 1085 int *training_step) 1086 { 1087 int tries, old_v_level, ret = 0; 1088 u8 link_status[DP_LINK_STATUS_SIZE]; 1089 int const maximum_retries = 4; 1090 1091 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1092 1093 *training_step = DP_TRAINING_1; 1094 1095 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); 1096 if (ret) 1097 return ret; 1098 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1099 DP_LINK_SCRAMBLING_DISABLE); 1100 1101 ret = dp_ctrl_update_vx_px(ctrl); 1102 if (ret) 1103 return ret; 1104 1105 tries = 0; 1106 old_v_level = ctrl->link->phy_params.v_level; 1107 for (tries = 0; tries < maximum_retries; tries++) { 1108 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); 1109 1110 ret = dp_ctrl_read_link_status(ctrl, link_status); 1111 if (ret) 1112 return ret; 1113 1114 if (drm_dp_clock_recovery_ok(link_status, 1115 ctrl->link->link_params.num_lanes)) { 1116 return 0; 1117 } 1118 1119 if (ctrl->link->phy_params.v_level >= 1120 DP_TRAIN_VOLTAGE_SWING_MAX) { 1121 DRM_ERROR_RATELIMITED("max v_level reached\n"); 1122 return -EAGAIN; 1123 } 1124 1125 if (old_v_level != ctrl->link->phy_params.v_level) { 1126 tries = 0; 1127 old_v_level = ctrl->link->phy_params.v_level; 1128 } 1129 1130 dp_link_adjust_levels(ctrl->link, link_status); 1131 ret = dp_ctrl_update_vx_px(ctrl); 1132 if (ret) 1133 return ret; 1134 } 1135 1136 DRM_ERROR("max tries reached\n"); 1137 return -ETIMEDOUT; 1138 } 1139 1140 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) 1141 { 1142 int ret = 0; 1143 1144 switch (ctrl->link->link_params.rate) { 1145 case 810000: 1146 ctrl->link->link_params.rate = 540000; 1147 break; 1148 case 540000: 1149 ctrl->link->link_params.rate = 270000; 1150 break; 1151 case 270000: 1152 ctrl->link->link_params.rate = 162000; 1153 break; 1154 case 162000: 1155 default: 1156 ret = -EINVAL; 1157 break; 1158 } 1159 1160 if (!ret) { 1161 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n", 1162 ctrl->link->link_params.rate); 1163 } 1164 1165 return ret; 1166 } 1167 1168 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) 1169 { 1170 1171 if (ctrl->link->link_params.num_lanes == 1) 1172 return -1; 1173 1174 ctrl->link->link_params.num_lanes /= 2; 1175 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; 1176 1177 ctrl->link->phy_params.p_level = 0; 1178 ctrl->link->phy_params.v_level = 0; 1179 1180 return 0; 1181 } 1182 1183 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) 1184 { 1185 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); 1186 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1187 } 1188 1189 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 1190 int *training_step) 1191 { 1192 int tries = 0, ret = 0; 1193 u8 pattern; 1194 u32 state_ctrl_bit; 1195 int const maximum_retries = 5; 1196 u8 link_status[DP_LINK_STATUS_SIZE]; 1197 1198 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1199 1200 *training_step = DP_TRAINING_2; 1201 1202 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { 1203 pattern = DP_TRAINING_PATTERN_4; 1204 state_ctrl_bit = 4; 1205 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { 1206 pattern = DP_TRAINING_PATTERN_3; 1207 state_ctrl_bit = 3; 1208 } else { 1209 pattern = DP_TRAINING_PATTERN_2; 1210 state_ctrl_bit = 2; 1211 } 1212 1213 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); 1214 if (ret) 1215 return ret; 1216 1217 dp_ctrl_train_pattern_set(ctrl, pattern); 1218 1219 for (tries = 0; tries <= maximum_retries; tries++) { 1220 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1221 1222 ret = dp_ctrl_read_link_status(ctrl, link_status); 1223 if (ret) 1224 return ret; 1225 1226 if (drm_dp_channel_eq_ok(link_status, 1227 ctrl->link->link_params.num_lanes)) { 1228 return 0; 1229 } 1230 1231 dp_link_adjust_levels(ctrl->link, link_status); 1232 ret = dp_ctrl_update_vx_px(ctrl); 1233 if (ret) 1234 return ret; 1235 1236 } 1237 1238 return -ETIMEDOUT; 1239 } 1240 1241 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 1242 int *training_step) 1243 { 1244 int ret = 0; 1245 const u8 *dpcd = ctrl->panel->dpcd; 1246 u8 encoding[] = { 0, DP_SET_ANSI_8B10B }; 1247 u8 assr; 1248 struct dp_link_info link_info = {0}; 1249 1250 dp_ctrl_config_ctrl(ctrl); 1251 1252 link_info.num_lanes = ctrl->link->link_params.num_lanes; 1253 link_info.rate = ctrl->link->link_params.rate; 1254 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; 1255 1256 dp_aux_link_configure(ctrl->aux, &link_info); 1257 1258 if (drm_dp_max_downspread(dpcd)) 1259 encoding[0] |= DP_SPREAD_AMP_0_5; 1260 1261 /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */ 1262 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2); 1263 1264 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { 1265 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 1266 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, 1267 &assr, 1); 1268 } 1269 1270 ret = dp_ctrl_link_train_1(ctrl, training_step); 1271 if (ret) { 1272 DRM_ERROR("link training #1 failed. ret=%d\n", ret); 1273 goto end; 1274 } 1275 1276 /* print success info as this is a result of user initiated action */ 1277 drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n"); 1278 1279 ret = dp_ctrl_link_train_2(ctrl, training_step); 1280 if (ret) { 1281 DRM_ERROR("link training #2 failed. ret=%d\n", ret); 1282 goto end; 1283 } 1284 1285 /* print success info as this is a result of user initiated action */ 1286 drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n"); 1287 1288 end: 1289 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1290 1291 return ret; 1292 } 1293 1294 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, 1295 int *training_step) 1296 { 1297 int ret = 0; 1298 1299 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 1300 1301 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1302 return ret; 1303 1304 /* 1305 * As part of previous calls, DP controller state might have 1306 * transitioned to PUSH_IDLE. In order to start transmitting 1307 * a link training pattern, we have to first do soft reset. 1308 */ 1309 1310 ret = dp_ctrl_link_train(ctrl, training_step); 1311 1312 return ret; 1313 } 1314 1315 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, 1316 enum dp_pm_type module, char *name, unsigned long rate) 1317 { 1318 u32 num = ctrl->parser->mp[module].num_clk; 1319 struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks; 1320 1321 while (num && strcmp(cfg->id, name)) { 1322 num--; 1323 cfg++; 1324 } 1325 1326 drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n", 1327 rate, name); 1328 1329 if (num) 1330 clk_set_rate(cfg->clk, rate); 1331 else 1332 DRM_ERROR("%s clock doesn't exit to set rate %lu\n", 1333 name, rate); 1334 } 1335 1336 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) 1337 { 1338 int ret = 0; 1339 struct dp_io *dp_io = &ctrl->parser->io; 1340 struct phy *phy = dp_io->phy; 1341 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; 1342 const u8 *dpcd = ctrl->panel->dpcd; 1343 1344 opts_dp->lanes = ctrl->link->link_params.num_lanes; 1345 opts_dp->link_rate = ctrl->link->link_params.rate / 100; 1346 opts_dp->ssc = drm_dp_max_downspread(dpcd); 1347 1348 phy_configure(phy, &dp_io->phy_opts); 1349 phy_power_on(phy); 1350 1351 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); 1352 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); 1353 if (ret) 1354 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); 1355 1356 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate); 1357 1358 return ret; 1359 } 1360 1361 void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable) 1362 { 1363 struct dp_ctrl_private *ctrl; 1364 1365 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1366 1367 dp_catalog_ctrl_reset(ctrl->catalog); 1368 1369 /* 1370 * all dp controller programmable registers will not 1371 * be reset to default value after DP_SW_RESET 1372 * therefore interrupt mask bits have to be updated 1373 * to enable/disable interrupts 1374 */ 1375 dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); 1376 } 1377 1378 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) 1379 { 1380 struct dp_ctrl_private *ctrl; 1381 struct dp_io *dp_io; 1382 struct phy *phy; 1383 1384 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1385 dp_io = &ctrl->parser->io; 1386 phy = dp_io->phy; 1387 1388 dp_catalog_ctrl_phy_reset(ctrl->catalog); 1389 phy_init(phy); 1390 1391 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1392 phy, phy->init_count, phy->power_count); 1393 } 1394 1395 void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl) 1396 { 1397 struct dp_ctrl_private *ctrl; 1398 struct dp_io *dp_io; 1399 struct phy *phy; 1400 1401 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1402 dp_io = &ctrl->parser->io; 1403 phy = dp_io->phy; 1404 1405 dp_catalog_ctrl_phy_reset(ctrl->catalog); 1406 phy_exit(phy); 1407 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1408 phy, phy->init_count, phy->power_count); 1409 } 1410 1411 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) 1412 { 1413 const u8 *dpcd = ctrl->panel->dpcd; 1414 1415 /* 1416 * For better interop experience, used a fixed NVID=0x8000 1417 * whenever connected to a VGA dongle downstream. 1418 */ 1419 if (drm_dp_is_branch(dpcd)) 1420 return (drm_dp_has_quirk(&ctrl->panel->desc, 1421 DP_DPCD_QUIRK_CONSTANT_N)); 1422 1423 return false; 1424 } 1425 1426 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) 1427 { 1428 int ret = 0; 1429 struct dp_io *dp_io = &ctrl->parser->io; 1430 struct phy *phy = dp_io->phy; 1431 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; 1432 1433 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1434 opts_dp->lanes = ctrl->link->link_params.num_lanes; 1435 phy_configure(phy, &dp_io->phy_opts); 1436 /* 1437 * Disable and re-enable the mainlink clock since the 1438 * link clock might have been adjusted as part of the 1439 * link maintenance. 1440 */ 1441 dev_pm_opp_set_rate(ctrl->dev, 0); 1442 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1443 if (ret) { 1444 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); 1445 return ret; 1446 } 1447 phy_power_off(phy); 1448 /* hw recommended delay before re-enabling clocks */ 1449 msleep(20); 1450 1451 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1452 if (ret) { 1453 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); 1454 return ret; 1455 } 1456 1457 return ret; 1458 } 1459 1460 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) 1461 { 1462 struct dp_io *dp_io; 1463 struct phy *phy; 1464 int ret; 1465 1466 dp_io = &ctrl->parser->io; 1467 phy = dp_io->phy; 1468 1469 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1470 1471 dp_catalog_ctrl_reset(ctrl->catalog); 1472 1473 dev_pm_opp_set_rate(ctrl->dev, 0); 1474 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1475 if (ret) { 1476 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1477 } 1478 1479 phy_power_off(phy); 1480 1481 /* aux channel down, reinit phy */ 1482 phy_exit(phy); 1483 phy_init(phy); 1484 1485 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1486 phy, phy->init_count, phy->power_count); 1487 return 0; 1488 } 1489 1490 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) 1491 { 1492 int ret = 0; 1493 int training_step = DP_TRAINING_NONE; 1494 1495 dp_ctrl_push_idle(&ctrl->dp_ctrl); 1496 1497 ctrl->link->phy_params.p_level = 0; 1498 ctrl->link->phy_params.v_level = 0; 1499 1500 ret = dp_ctrl_setup_main_link(ctrl, &training_step); 1501 if (ret) 1502 goto end; 1503 1504 dp_ctrl_clear_training_pattern(ctrl); 1505 1506 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1507 1508 ret = dp_ctrl_wait4video_ready(ctrl); 1509 end: 1510 return ret; 1511 } 1512 1513 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) 1514 { 1515 bool success = false; 1516 u32 pattern_sent = 0x0; 1517 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; 1518 1519 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); 1520 1521 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog, 1522 ctrl->link->phy_params.v_level, 1523 ctrl->link->phy_params.p_level)) { 1524 DRM_ERROR("Failed to set v/p levels\n"); 1525 return false; 1526 } 1527 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); 1528 dp_ctrl_update_vx_px(ctrl); 1529 dp_link_send_test_response(ctrl->link); 1530 1531 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); 1532 1533 switch (pattern_sent) { 1534 case MR_LINK_TRAINING1: 1535 success = (pattern_requested == 1536 DP_PHY_TEST_PATTERN_D10_2); 1537 break; 1538 case MR_LINK_SYMBOL_ERM: 1539 success = ((pattern_requested == 1540 DP_PHY_TEST_PATTERN_ERROR_COUNT) || 1541 (pattern_requested == 1542 DP_PHY_TEST_PATTERN_CP2520)); 1543 break; 1544 case MR_LINK_PRBS7: 1545 success = (pattern_requested == 1546 DP_PHY_TEST_PATTERN_PRBS7); 1547 break; 1548 case MR_LINK_CUSTOM80: 1549 success = (pattern_requested == 1550 DP_PHY_TEST_PATTERN_80BIT_CUSTOM); 1551 break; 1552 case MR_LINK_TRAINING4: 1553 success = (pattern_requested == 1554 DP_PHY_TEST_PATTERN_SEL_MASK); 1555 break; 1556 default: 1557 success = false; 1558 } 1559 1560 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n", 1561 success ? "success" : "failed", pattern_requested); 1562 return success; 1563 } 1564 1565 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) 1566 { 1567 int ret; 1568 unsigned long pixel_rate; 1569 1570 if (!ctrl->link->phy_params.phy_test_pattern_sel) { 1571 drm_dbg_dp(ctrl->drm_dev, 1572 "no test pattern selected by sink\n"); 1573 return 0; 1574 } 1575 1576 /* 1577 * The global reset will need DP link related clocks to be 1578 * running. Add the global reset just before disabling the 1579 * link clocks and core clocks. 1580 */ 1581 ret = dp_ctrl_off(&ctrl->dp_ctrl); 1582 if (ret) { 1583 DRM_ERROR("failed to disable DP controller\n"); 1584 return ret; 1585 } 1586 1587 ret = dp_ctrl_on_link(&ctrl->dp_ctrl); 1588 if (ret) { 1589 DRM_ERROR("failed to enable DP link controller\n"); 1590 return ret; 1591 } 1592 1593 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1594 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000); 1595 1596 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); 1597 if (ret) { 1598 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1599 return ret; 1600 } 1601 1602 dp_ctrl_send_phy_test_pattern(ctrl); 1603 1604 return 0; 1605 } 1606 1607 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) 1608 { 1609 struct dp_ctrl_private *ctrl; 1610 u32 sink_request = 0x0; 1611 1612 if (!dp_ctrl) { 1613 DRM_ERROR("invalid input\n"); 1614 return; 1615 } 1616 1617 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1618 sink_request = ctrl->link->sink_request; 1619 1620 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1621 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); 1622 if (dp_ctrl_process_phy_test_request(ctrl)) { 1623 DRM_ERROR("process phy_test_req failed\n"); 1624 return; 1625 } 1626 } 1627 1628 if (sink_request & DP_LINK_STATUS_UPDATED) { 1629 if (dp_ctrl_link_maintenance(ctrl)) { 1630 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1631 return; 1632 } 1633 } 1634 1635 if (sink_request & DP_TEST_LINK_TRAINING) { 1636 dp_link_send_test_response(ctrl->link); 1637 if (dp_ctrl_link_maintenance(ctrl)) { 1638 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1639 return; 1640 } 1641 } 1642 } 1643 1644 static bool dp_ctrl_clock_recovery_any_ok( 1645 const u8 link_status[DP_LINK_STATUS_SIZE], 1646 int lane_count) 1647 { 1648 int reduced_cnt; 1649 1650 if (lane_count <= 1) 1651 return false; 1652 1653 /* 1654 * only interested in the lane number after reduced 1655 * lane_count = 4, then only interested in 2 lanes 1656 * lane_count = 2, then only interested in 1 lane 1657 */ 1658 reduced_cnt = lane_count >> 1; 1659 1660 return drm_dp_clock_recovery_ok(link_status, reduced_cnt); 1661 } 1662 1663 static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl) 1664 { 1665 u8 link_status[DP_LINK_STATUS_SIZE]; 1666 int num_lanes = ctrl->link->link_params.num_lanes; 1667 1668 dp_ctrl_read_link_status(ctrl, link_status); 1669 1670 return drm_dp_channel_eq_ok(link_status, num_lanes); 1671 } 1672 1673 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 1674 { 1675 int rc = 0; 1676 struct dp_ctrl_private *ctrl; 1677 u32 rate; 1678 int link_train_max_retries = 5; 1679 u32 const phy_cts_pixel_clk_khz = 148500; 1680 u8 link_status[DP_LINK_STATUS_SIZE]; 1681 unsigned int training_step; 1682 unsigned long pixel_rate; 1683 1684 if (!dp_ctrl) 1685 return -EINVAL; 1686 1687 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1688 1689 rate = ctrl->panel->link_info.rate; 1690 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1691 1692 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); 1693 1694 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1695 drm_dbg_dp(ctrl->drm_dev, 1696 "using phy test link parameters\n"); 1697 if (!pixel_rate) 1698 pixel_rate = phy_cts_pixel_clk_khz; 1699 } else { 1700 ctrl->link->link_params.rate = rate; 1701 ctrl->link->link_params.num_lanes = 1702 ctrl->panel->link_info.num_lanes; 1703 } 1704 1705 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", 1706 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, 1707 pixel_rate); 1708 1709 rc = dp_ctrl_enable_mainlink_clocks(ctrl); 1710 if (rc) 1711 return rc; 1712 1713 while (--link_train_max_retries) { 1714 rc = dp_ctrl_reinitialize_mainlink(ctrl); 1715 if (rc) { 1716 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", 1717 rc); 1718 break; 1719 } 1720 1721 training_step = DP_TRAINING_NONE; 1722 rc = dp_ctrl_setup_main_link(ctrl, &training_step); 1723 if (rc == 0) { 1724 /* training completed successfully */ 1725 break; 1726 } else if (training_step == DP_TRAINING_1) { 1727 /* link train_1 failed */ 1728 if (!dp_catalog_link_is_connected(ctrl->catalog)) 1729 break; 1730 1731 dp_ctrl_read_link_status(ctrl, link_status); 1732 1733 rc = dp_ctrl_link_rate_down_shift(ctrl); 1734 if (rc < 0) { /* already in RBR = 1.6G */ 1735 if (dp_ctrl_clock_recovery_any_ok(link_status, 1736 ctrl->link->link_params.num_lanes)) { 1737 /* 1738 * some lanes are ready, 1739 * reduce lane number 1740 */ 1741 rc = dp_ctrl_link_lane_down_shift(ctrl); 1742 if (rc < 0) { /* lane == 1 already */ 1743 /* end with failure */ 1744 break; 1745 } 1746 } else { 1747 /* end with failure */ 1748 break; /* lane == 1 already */ 1749 } 1750 } 1751 } else if (training_step == DP_TRAINING_2) { 1752 /* link train_2 failed */ 1753 if (!dp_catalog_link_is_connected(ctrl->catalog)) 1754 break; 1755 1756 dp_ctrl_read_link_status(ctrl, link_status); 1757 1758 if (!drm_dp_clock_recovery_ok(link_status, 1759 ctrl->link->link_params.num_lanes)) 1760 rc = dp_ctrl_link_rate_down_shift(ctrl); 1761 else 1762 rc = dp_ctrl_link_lane_down_shift(ctrl); 1763 1764 if (rc < 0) { 1765 /* end with failure */ 1766 break; /* lane == 1 already */ 1767 } 1768 1769 /* stop link training before start re training */ 1770 dp_ctrl_clear_training_pattern(ctrl); 1771 } 1772 } 1773 1774 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1775 return rc; 1776 1777 if (rc == 0) { /* link train successfully */ 1778 /* 1779 * do not stop train pattern here 1780 * stop link training at on_stream 1781 * to pass compliance test 1782 */ 1783 } else { 1784 /* 1785 * link training failed 1786 * end txing train pattern here 1787 */ 1788 dp_ctrl_clear_training_pattern(ctrl); 1789 1790 dp_ctrl_deinitialize_mainlink(ctrl); 1791 rc = -ECONNRESET; 1792 } 1793 1794 return rc; 1795 } 1796 1797 static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl) 1798 { 1799 int training_step = DP_TRAINING_NONE; 1800 1801 return dp_ctrl_setup_main_link(ctrl, &training_step); 1802 } 1803 1804 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train) 1805 { 1806 int ret = 0; 1807 bool mainlink_ready = false; 1808 struct dp_ctrl_private *ctrl; 1809 unsigned long pixel_rate; 1810 unsigned long pixel_rate_orig; 1811 1812 if (!dp_ctrl) 1813 return -EINVAL; 1814 1815 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1816 1817 pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock; 1818 1819 if (dp_ctrl->wide_bus_en) 1820 pixel_rate >>= 1; 1821 1822 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", 1823 ctrl->link->link_params.rate, 1824 ctrl->link->link_params.num_lanes, pixel_rate); 1825 1826 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */ 1827 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1828 if (ret) { 1829 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); 1830 goto end; 1831 } 1832 } 1833 1834 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000); 1835 1836 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); 1837 if (ret) { 1838 DRM_ERROR("Unable to start pixel clocks. ret=%d\n", ret); 1839 goto end; 1840 } 1841 1842 if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl)) 1843 dp_ctrl_link_retrain(ctrl); 1844 1845 /* stop txing train pattern to end link training */ 1846 dp_ctrl_clear_training_pattern(ctrl); 1847 1848 /* 1849 * Set up transfer unit values and set controller state to send 1850 * video. 1851 */ 1852 reinit_completion(&ctrl->video_comp); 1853 1854 dp_ctrl_configure_source_params(ctrl); 1855 1856 dp_catalog_ctrl_config_msa(ctrl->catalog, 1857 ctrl->link->link_params.rate, 1858 pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl)); 1859 1860 dp_ctrl_setup_tr_unit(ctrl); 1861 1862 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1863 1864 ret = dp_ctrl_wait4video_ready(ctrl); 1865 if (ret) 1866 return ret; 1867 1868 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); 1869 drm_dbg_dp(ctrl->drm_dev, 1870 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); 1871 1872 end: 1873 return ret; 1874 } 1875 1876 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) 1877 { 1878 struct dp_ctrl_private *ctrl; 1879 struct dp_io *dp_io; 1880 struct phy *phy; 1881 int ret; 1882 1883 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1884 dp_io = &ctrl->parser->io; 1885 phy = dp_io->phy; 1886 1887 /* set dongle to D3 (power off) mode */ 1888 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); 1889 1890 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1891 1892 if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) { 1893 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); 1894 if (ret) { 1895 DRM_ERROR("Failed to disable pclk. ret=%d\n", ret); 1896 return ret; 1897 } 1898 } 1899 1900 dev_pm_opp_set_rate(ctrl->dev, 0); 1901 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1902 if (ret) { 1903 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1904 return ret; 1905 } 1906 1907 phy_power_off(phy); 1908 1909 /* aux channel down, reinit phy */ 1910 phy_exit(phy); 1911 phy_init(phy); 1912 1913 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1914 phy, phy->init_count, phy->power_count); 1915 return ret; 1916 } 1917 1918 int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl) 1919 { 1920 struct dp_ctrl_private *ctrl; 1921 struct dp_io *dp_io; 1922 struct phy *phy; 1923 int ret; 1924 1925 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1926 dp_io = &ctrl->parser->io; 1927 phy = dp_io->phy; 1928 1929 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1930 1931 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1932 if (ret) { 1933 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1934 } 1935 1936 DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n", 1937 phy, phy->init_count, phy->power_count); 1938 1939 phy_power_off(phy); 1940 1941 DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n", 1942 phy, phy->init_count, phy->power_count); 1943 1944 return ret; 1945 } 1946 1947 int dp_ctrl_off(struct dp_ctrl *dp_ctrl) 1948 { 1949 struct dp_ctrl_private *ctrl; 1950 struct dp_io *dp_io; 1951 struct phy *phy; 1952 int ret = 0; 1953 1954 if (!dp_ctrl) 1955 return -EINVAL; 1956 1957 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1958 dp_io = &ctrl->parser->io; 1959 phy = dp_io->phy; 1960 1961 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1962 1963 dp_catalog_ctrl_reset(ctrl->catalog); 1964 1965 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); 1966 if (ret) 1967 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); 1968 1969 dev_pm_opp_set_rate(ctrl->dev, 0); 1970 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1971 if (ret) { 1972 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1973 } 1974 1975 phy_power_off(phy); 1976 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1977 phy, phy->init_count, phy->power_count); 1978 1979 return ret; 1980 } 1981 1982 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl) 1983 { 1984 struct dp_ctrl_private *ctrl; 1985 u32 isr; 1986 1987 if (!dp_ctrl) 1988 return; 1989 1990 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1991 1992 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog); 1993 1994 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { 1995 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); 1996 complete(&ctrl->video_comp); 1997 } 1998 1999 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { 2000 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n"); 2001 complete(&ctrl->idle_comp); 2002 } 2003 } 2004 2005 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, 2006 struct dp_panel *panel, struct drm_dp_aux *aux, 2007 struct dp_power *power, struct dp_catalog *catalog, 2008 struct dp_parser *parser) 2009 { 2010 struct dp_ctrl_private *ctrl; 2011 int ret; 2012 2013 if (!dev || !panel || !aux || 2014 !link || !catalog) { 2015 DRM_ERROR("invalid input\n"); 2016 return ERR_PTR(-EINVAL); 2017 } 2018 2019 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 2020 if (!ctrl) { 2021 DRM_ERROR("Mem allocation failure\n"); 2022 return ERR_PTR(-ENOMEM); 2023 } 2024 2025 ret = devm_pm_opp_set_clkname(dev, "ctrl_link"); 2026 if (ret) { 2027 dev_err(dev, "invalid DP OPP table in device tree\n"); 2028 /* caller do PTR_ERR(opp_table) */ 2029 return (struct dp_ctrl *)ERR_PTR(ret); 2030 } 2031 2032 /* OPP table is optional */ 2033 ret = devm_pm_opp_of_add_table(dev); 2034 if (ret) 2035 dev_err(dev, "failed to add DP OPP table\n"); 2036 2037 init_completion(&ctrl->idle_comp); 2038 init_completion(&ctrl->video_comp); 2039 2040 /* in parameters */ 2041 ctrl->parser = parser; 2042 ctrl->panel = panel; 2043 ctrl->power = power; 2044 ctrl->aux = aux; 2045 ctrl->link = link; 2046 ctrl->catalog = catalog; 2047 ctrl->dev = dev; 2048 2049 return &ctrl->dp_ctrl; 2050 } 2051