1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ 7 8 #include <linux/types.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/phy/phy.h> 12 #include <linux/phy/phy-dp.h> 13 #include <linux/pm_opp.h> 14 #include <drm/drm_fixed.h> 15 #include <drm/drm_dp_helper.h> 16 #include <drm/drm_print.h> 17 18 #include "dp_reg.h" 19 #include "dp_ctrl.h" 20 #include "dp_link.h" 21 22 #define DP_KHZ_TO_HZ 1000 23 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ 24 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) 25 26 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) 27 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) 28 29 #define MR_LINK_TRAINING1 0x8 30 #define MR_LINK_SYMBOL_ERM 0x80 31 #define MR_LINK_PRBS7 0x100 32 #define MR_LINK_CUSTOM80 0x200 33 #define MR_LINK_TRAINING4 0x40 34 35 enum { 36 DP_TRAINING_NONE, 37 DP_TRAINING_1, 38 DP_TRAINING_2, 39 }; 40 41 struct dp_tu_calc_input { 42 u64 lclk; /* 162, 270, 540 and 810 */ 43 u64 pclk_khz; /* in KHz */ 44 u64 hactive; /* active h-width */ 45 u64 hporch; /* bp + fp + pulse */ 46 int nlanes; /* no.of.lanes */ 47 int bpp; /* bits */ 48 int pixel_enc; /* 444, 420, 422 */ 49 int dsc_en; /* dsc on/off */ 50 int async_en; /* async mode */ 51 int fec_en; /* fec */ 52 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ 53 int num_of_dsc_slices; /* number of slices per line */ 54 }; 55 56 struct dp_vc_tu_mapping_table { 57 u32 vic; 58 u8 lanes; 59 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ 60 u8 bpp; 61 u8 valid_boundary_link; 62 u16 delay_start_link; 63 bool boundary_moderation_en; 64 u8 valid_lower_boundary_link; 65 u8 upper_boundary_count; 66 u8 lower_boundary_count; 67 u8 tu_size_minus1; 68 }; 69 70 struct dp_ctrl_private { 71 struct dp_ctrl dp_ctrl; 72 struct device *dev; 73 struct drm_dp_aux *aux; 74 struct dp_panel *panel; 75 struct dp_link *link; 76 struct dp_power *power; 77 struct dp_parser *parser; 78 struct dp_catalog *catalog; 79 80 struct opp_table *opp_table; 81 82 struct completion idle_comp; 83 struct completion video_comp; 84 }; 85 86 struct dp_cr_status { 87 u8 lane_0_1; 88 u8 lane_2_3; 89 }; 90 91 #define DP_LANE0_1_CR_DONE 0x11 92 93 static int dp_aux_link_configure(struct drm_dp_aux *aux, 94 struct dp_link_info *link) 95 { 96 u8 values[2]; 97 int err; 98 99 values[0] = drm_dp_link_rate_to_bw_code(link->rate); 100 values[1] = link->num_lanes; 101 102 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 103 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 104 105 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); 106 if (err < 0) 107 return err; 108 109 return 0; 110 } 111 112 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) 113 { 114 struct dp_ctrl_private *ctrl; 115 116 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 117 118 reinit_completion(&ctrl->idle_comp); 119 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); 120 121 if (!wait_for_completion_timeout(&ctrl->idle_comp, 122 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) 123 pr_warn("PUSH_IDLE pattern timedout\n"); 124 125 pr_debug("mainlink off done\n"); 126 } 127 128 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) 129 { 130 u32 config = 0, tbd; 131 u8 *dpcd = ctrl->panel->dpcd; 132 133 /* Default-> LSCLK DIV: 1/4 LCLK */ 134 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); 135 136 /* Scrambler reset enable */ 137 if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) 138 config |= DP_CONFIGURATION_CTRL_ASSR; 139 140 tbd = dp_link_get_test_bits_depth(ctrl->link, 141 ctrl->panel->dp_mode.bpp); 142 143 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) { 144 pr_debug("BIT_DEPTH not set. Configure default\n"); 145 tbd = DP_TEST_BIT_DEPTH_8; 146 } 147 148 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; 149 150 /* Num of Lanes */ 151 config |= ((ctrl->link->link_params.num_lanes - 1) 152 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); 153 154 if (drm_dp_enhanced_frame_cap(dpcd)) 155 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; 156 157 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ 158 159 /* sync clock & static Mvid */ 160 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; 161 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; 162 163 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); 164 } 165 166 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) 167 { 168 u32 cc, tb; 169 170 dp_catalog_ctrl_lane_mapping(ctrl->catalog); 171 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 172 173 dp_ctrl_config_ctrl(ctrl); 174 175 tb = dp_link_get_test_bits_depth(ctrl->link, 176 ctrl->panel->dp_mode.bpp); 177 cc = dp_link_get_colorimetry_config(ctrl->link); 178 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); 179 dp_panel_timing_cfg(ctrl->panel); 180 } 181 182 /* 183 * The structure and few functions present below are IP/Hardware 184 * specific implementation. Most of the implementation will not 185 * have coding comments 186 */ 187 struct tu_algo_data { 188 s64 lclk_fp; 189 s64 pclk_fp; 190 s64 lwidth; 191 s64 lwidth_fp; 192 s64 hbp_relative_to_pclk; 193 s64 hbp_relative_to_pclk_fp; 194 int nlanes; 195 int bpp; 196 int pixelEnc; 197 int dsc_en; 198 int async_en; 199 int bpc; 200 201 uint delay_start_link_extra_pixclk; 202 int extra_buffer_margin; 203 s64 ratio_fp; 204 s64 original_ratio_fp; 205 206 s64 err_fp; 207 s64 n_err_fp; 208 s64 n_n_err_fp; 209 int tu_size; 210 int tu_size_desired; 211 int tu_size_minus1; 212 213 int valid_boundary_link; 214 s64 resulting_valid_fp; 215 s64 total_valid_fp; 216 s64 effective_valid_fp; 217 s64 effective_valid_recorded_fp; 218 int n_tus; 219 int n_tus_per_lane; 220 int paired_tus; 221 int remainder_tus; 222 int remainder_tus_upper; 223 int remainder_tus_lower; 224 int extra_bytes; 225 int filler_size; 226 int delay_start_link; 227 228 int extra_pclk_cycles; 229 int extra_pclk_cycles_in_link_clk; 230 s64 ratio_by_tu_fp; 231 s64 average_valid2_fp; 232 int new_valid_boundary_link; 233 int remainder_symbols_exist; 234 int n_symbols; 235 s64 n_remainder_symbols_per_lane_fp; 236 s64 last_partial_tu_fp; 237 s64 TU_ratio_err_fp; 238 239 int n_tus_incl_last_incomplete_tu; 240 int extra_pclk_cycles_tmp; 241 int extra_pclk_cycles_in_link_clk_tmp; 242 int extra_required_bytes_new_tmp; 243 int filler_size_tmp; 244 int lower_filler_size_tmp; 245 int delay_start_link_tmp; 246 247 bool boundary_moderation_en; 248 int boundary_mod_lower_err; 249 int upper_boundary_count; 250 int lower_boundary_count; 251 int i_upper_boundary_count; 252 int i_lower_boundary_count; 253 int valid_lower_boundary_link; 254 int even_distribution_BF; 255 int even_distribution_legacy; 256 int even_distribution; 257 int min_hblank_violated; 258 s64 delay_start_time_fp; 259 s64 hbp_time_fp; 260 s64 hactive_time_fp; 261 s64 diff_abs_fp; 262 263 s64 ratio; 264 }; 265 266 static int _tu_param_compare(s64 a, s64 b) 267 { 268 u32 a_sign; 269 u32 b_sign; 270 s64 a_temp, b_temp, minus_1; 271 272 if (a == b) 273 return 0; 274 275 minus_1 = drm_fixp_from_fraction(-1, 1); 276 277 a_sign = (a >> 32) & 0x80000000 ? 1 : 0; 278 279 b_sign = (b >> 32) & 0x80000000 ? 1 : 0; 280 281 if (a_sign > b_sign) 282 return 2; 283 else if (b_sign > a_sign) 284 return 1; 285 286 if (!a_sign && !b_sign) { /* positive */ 287 if (a > b) 288 return 1; 289 else 290 return 2; 291 } else { /* negative */ 292 a_temp = drm_fixp_mul(a, minus_1); 293 b_temp = drm_fixp_mul(b, minus_1); 294 295 if (a_temp > b_temp) 296 return 2; 297 else 298 return 1; 299 } 300 } 301 302 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in, 303 struct tu_algo_data *tu) 304 { 305 int nlanes = in->nlanes; 306 int dsc_num_slices = in->num_of_dsc_slices; 307 int dsc_num_bytes = 0; 308 int numerator; 309 s64 pclk_dsc_fp; 310 s64 dwidth_dsc_fp; 311 s64 hbp_dsc_fp; 312 313 int tot_num_eoc_symbols = 0; 314 int tot_num_hor_bytes = 0; 315 int tot_num_dummy_bytes = 0; 316 int dwidth_dsc_bytes = 0; 317 int eoc_bytes = 0; 318 319 s64 temp1_fp, temp2_fp, temp3_fp; 320 321 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); 322 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); 323 tu->lwidth = in->hactive; 324 tu->hbp_relative_to_pclk = in->hporch; 325 tu->nlanes = in->nlanes; 326 tu->bpp = in->bpp; 327 tu->pixelEnc = in->pixel_enc; 328 tu->dsc_en = in->dsc_en; 329 tu->async_en = in->async_en; 330 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); 331 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); 332 333 if (tu->pixelEnc == 420) { 334 temp1_fp = drm_fixp_from_fraction(2, 1); 335 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); 336 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); 337 tu->hbp_relative_to_pclk_fp = 338 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); 339 } 340 341 if (tu->pixelEnc == 422) { 342 switch (tu->bpp) { 343 case 24: 344 tu->bpp = 16; 345 tu->bpc = 8; 346 break; 347 case 30: 348 tu->bpp = 20; 349 tu->bpc = 10; 350 break; 351 default: 352 tu->bpp = 16; 353 tu->bpc = 8; 354 break; 355 } 356 } else { 357 tu->bpc = tu->bpp/3; 358 } 359 360 if (!in->dsc_en) 361 goto fec_check; 362 363 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); 364 temp2_fp = drm_fixp_from_fraction(in->bpp, 1); 365 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 366 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); 367 368 temp1_fp = drm_fixp_from_fraction(8, 1); 369 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 370 371 numerator = drm_fixp2int(temp3_fp); 372 373 dsc_num_bytes = numerator / dsc_num_slices; 374 eoc_bytes = dsc_num_bytes % nlanes; 375 tot_num_eoc_symbols = nlanes * dsc_num_slices; 376 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; 377 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; 378 379 if (dsc_num_bytes == 0) 380 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); 381 382 dwidth_dsc_bytes = (tot_num_hor_bytes + 383 tot_num_eoc_symbols + 384 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); 385 386 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); 387 388 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); 389 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); 390 pclk_dsc_fp = temp1_fp; 391 392 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); 393 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); 394 hbp_dsc_fp = temp2_fp; 395 396 /* output */ 397 tu->pclk_fp = pclk_dsc_fp; 398 tu->lwidth_fp = dwidth_dsc_fp; 399 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; 400 401 fec_check: 402 if (in->fec_en) { 403 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ 404 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); 405 } 406 } 407 408 static void _tu_valid_boundary_calc(struct tu_algo_data *tu) 409 { 410 s64 temp1_fp, temp2_fp, temp, temp1, temp2; 411 int compare_result_1, compare_result_2, compare_result_3; 412 413 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 414 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 415 416 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 417 418 temp = (tu->i_upper_boundary_count * 419 tu->new_valid_boundary_link + 420 tu->i_lower_boundary_count * 421 (tu->new_valid_boundary_link-1)); 422 tu->average_valid2_fp = drm_fixp_from_fraction(temp, 423 (tu->i_upper_boundary_count + 424 tu->i_lower_boundary_count)); 425 426 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 427 temp2_fp = tu->lwidth_fp; 428 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 429 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 430 tu->n_tus = drm_fixp2int(temp2_fp); 431 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 432 tu->n_tus += 1; 433 434 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); 435 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); 436 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); 437 temp2_fp = temp1_fp - temp2_fp; 438 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 439 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 440 tu->n_remainder_symbols_per_lane_fp = temp2_fp; 441 442 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 443 tu->last_partial_tu_fp = 444 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, 445 temp1_fp); 446 447 if (tu->n_remainder_symbols_per_lane_fp != 0) 448 tu->remainder_symbols_exist = 1; 449 else 450 tu->remainder_symbols_exist = 0; 451 452 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); 453 tu->n_tus_per_lane = drm_fixp2int(temp1_fp); 454 455 tu->paired_tus = (int)((tu->n_tus_per_lane) / 456 (tu->i_upper_boundary_count + 457 tu->i_lower_boundary_count)); 458 459 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * 460 (tu->i_upper_boundary_count + 461 tu->i_lower_boundary_count); 462 463 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { 464 tu->remainder_tus_upper = tu->i_upper_boundary_count; 465 tu->remainder_tus_lower = tu->remainder_tus - 466 tu->i_upper_boundary_count; 467 } else { 468 tu->remainder_tus_upper = tu->remainder_tus; 469 tu->remainder_tus_lower = 0; 470 } 471 472 temp = tu->paired_tus * (tu->i_upper_boundary_count * 473 tu->new_valid_boundary_link + 474 tu->i_lower_boundary_count * 475 (tu->new_valid_boundary_link - 1)) + 476 (tu->remainder_tus_upper * 477 tu->new_valid_boundary_link) + 478 (tu->remainder_tus_lower * 479 (tu->new_valid_boundary_link - 1)); 480 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); 481 482 if (tu->remainder_symbols_exist) { 483 temp1_fp = tu->total_valid_fp + 484 tu->n_remainder_symbols_per_lane_fp; 485 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 486 temp2_fp = temp2_fp + tu->last_partial_tu_fp; 487 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); 488 } else { 489 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 490 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); 491 } 492 tu->effective_valid_fp = temp1_fp; 493 494 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 495 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 496 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; 497 498 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 499 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 500 tu->n_err_fp = tu->average_valid2_fp - temp2_fp; 501 502 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 503 504 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 505 temp2_fp = tu->lwidth_fp; 506 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 507 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 508 509 if (temp2_fp) 510 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); 511 else 512 tu->n_tus_incl_last_incomplete_tu = 0; 513 514 temp1 = 0; 515 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 516 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 517 temp1_fp = tu->average_valid2_fp - temp2_fp; 518 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); 519 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 520 521 if (temp1_fp) 522 temp1 = drm_fixp2int_ceil(temp1_fp); 523 524 temp = tu->i_upper_boundary_count * tu->nlanes; 525 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 526 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 527 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); 528 temp2_fp = temp1_fp - temp2_fp; 529 temp1_fp = drm_fixp_from_fraction(temp, 1); 530 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 531 532 if (temp2_fp) 533 temp2 = drm_fixp2int_ceil(temp2_fp); 534 else 535 temp2 = 0; 536 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); 537 538 temp1_fp = drm_fixp_from_fraction(8, tu->bpp); 539 temp2_fp = drm_fixp_from_fraction( 540 tu->extra_required_bytes_new_tmp, 1); 541 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 542 543 if (temp1_fp) 544 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); 545 else 546 tu->extra_pclk_cycles_tmp = 0; 547 548 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); 549 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 550 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 551 552 if (temp1_fp) 553 tu->extra_pclk_cycles_in_link_clk_tmp = 554 drm_fixp2int_ceil(temp1_fp); 555 else 556 tu->extra_pclk_cycles_in_link_clk_tmp = 0; 557 558 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; 559 560 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; 561 562 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + 563 tu->lower_filler_size_tmp + 564 tu->extra_buffer_margin; 565 566 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); 567 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 568 569 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); 570 if (compare_result_1 == 2) 571 compare_result_1 = 1; 572 else 573 compare_result_1 = 0; 574 575 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); 576 if (compare_result_2 == 2) 577 compare_result_2 = 1; 578 else 579 compare_result_2 = 0; 580 581 compare_result_3 = _tu_param_compare(tu->hbp_time_fp, 582 tu->delay_start_time_fp); 583 if (compare_result_3 == 2) 584 compare_result_3 = 0; 585 else 586 compare_result_3 = 1; 587 588 if (((tu->even_distribution == 1) || 589 ((tu->even_distribution_BF == 0) && 590 (tu->even_distribution_legacy == 0))) && 591 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && 592 compare_result_2 && 593 (compare_result_1 || (tu->min_hblank_violated == 1)) && 594 (tu->new_valid_boundary_link - 1) > 0 && 595 compare_result_3 && 596 (tu->delay_start_link_tmp <= 1023)) { 597 tu->upper_boundary_count = tu->i_upper_boundary_count; 598 tu->lower_boundary_count = tu->i_lower_boundary_count; 599 tu->err_fp = tu->n_n_err_fp; 600 tu->boundary_moderation_en = true; 601 tu->tu_size_desired = tu->tu_size; 602 tu->valid_boundary_link = tu->new_valid_boundary_link; 603 tu->effective_valid_recorded_fp = tu->effective_valid_fp; 604 tu->even_distribution_BF = 1; 605 tu->delay_start_link = tu->delay_start_link_tmp; 606 } else if (tu->boundary_mod_lower_err == 0) { 607 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, 608 tu->diff_abs_fp); 609 if (compare_result_1 == 2) 610 tu->boundary_mod_lower_err = 1; 611 } 612 } 613 614 static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in, 615 struct dp_vc_tu_mapping_table *tu_table) 616 { 617 struct tu_algo_data *tu; 618 int compare_result_1, compare_result_2; 619 u64 temp = 0; 620 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; 621 622 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ 623 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */ 624 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */ 625 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); 626 627 u8 DP_BRUTE_FORCE = 1; 628 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ 629 uint EXTRA_PIXCLK_CYCLE_DELAY = 4; 630 uint HBLANK_MARGIN = 4; 631 632 tu = kzalloc(sizeof(*tu), GFP_KERNEL); 633 if (!tu) 634 return 635 636 dp_panel_update_tu_timings(in, tu); 637 638 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ 639 640 temp1_fp = drm_fixp_from_fraction(4, 1); 641 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); 642 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); 643 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp); 644 645 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 646 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp); 647 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 648 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 649 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp); 650 651 tu->original_ratio_fp = tu->ratio_fp; 652 tu->boundary_moderation_en = false; 653 tu->upper_boundary_count = 0; 654 tu->lower_boundary_count = 0; 655 tu->i_upper_boundary_count = 0; 656 tu->i_lower_boundary_count = 0; 657 tu->valid_lower_boundary_link = 0; 658 tu->even_distribution_BF = 0; 659 tu->even_distribution_legacy = 0; 660 tu->even_distribution = 0; 661 tu->delay_start_time_fp = 0; 662 663 tu->err_fp = drm_fixp_from_fraction(1000, 1); 664 tu->n_err_fp = 0; 665 tu->n_n_err_fp = 0; 666 667 tu->ratio = drm_fixp2int(tu->ratio_fp); 668 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 669 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp); 670 if (temp2_fp != 0 && 671 !tu->ratio && tu->dsc_en == 0) { 672 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp); 673 tu->ratio = drm_fixp2int(tu->ratio_fp); 674 if (tu->ratio) 675 tu->ratio_fp = drm_fixp_from_fraction(1, 1); 676 } 677 678 if (tu->ratio > 1) 679 tu->ratio = 1; 680 681 if (tu->ratio == 1) 682 goto tu_size_calc; 683 684 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp); 685 if (!compare_result_1 || compare_result_1 == 1) 686 compare_result_1 = 1; 687 else 688 compare_result_1 = 0; 689 690 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp); 691 if (!compare_result_2 || compare_result_2 == 2) 692 compare_result_2 = 1; 693 else 694 compare_result_2 = 0; 695 696 if (tu->dsc_en && compare_result_1 && compare_result_2) { 697 HBLANK_MARGIN += 4; 698 DRM_DEBUG_DP("Info: increase HBLANK_MARGIN to %d\n", 699 HBLANK_MARGIN); 700 } 701 702 tu_size_calc: 703 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 704 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 705 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 706 temp = drm_fixp2int_ceil(temp2_fp); 707 temp1_fp = drm_fixp_from_fraction(temp, 1); 708 tu->n_err_fp = temp1_fp - temp2_fp; 709 710 if (tu->n_err_fp < tu->err_fp) { 711 tu->err_fp = tu->n_err_fp; 712 tu->tu_size_desired = tu->tu_size; 713 } 714 } 715 716 tu->tu_size_minus1 = tu->tu_size_desired - 1; 717 718 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 719 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 720 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 721 722 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 723 temp2_fp = tu->lwidth_fp; 724 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); 725 726 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 727 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 728 tu->n_tus = drm_fixp2int(temp2_fp); 729 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 730 tu->n_tus += 1; 731 732 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 733 DRM_DEBUG_DP("Info: n_sym = %d, num_of_tus = %d\n", 734 tu->valid_boundary_link, tu->n_tus); 735 736 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 737 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 738 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 739 temp2_fp = temp1_fp - temp2_fp; 740 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); 741 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 742 743 temp = drm_fixp2int(temp2_fp); 744 if (temp && temp2_fp) 745 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp); 746 else 747 tu->extra_bytes = 0; 748 749 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); 750 temp2_fp = drm_fixp_from_fraction(8, tu->bpp); 751 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 752 753 if (temp && temp1_fp) 754 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); 755 else 756 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp); 757 758 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 759 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); 760 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 761 762 if (temp1_fp) 763 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); 764 else 765 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); 766 767 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; 768 769 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 770 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 771 772 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + 773 tu->filler_size + tu->extra_buffer_margin; 774 775 tu->resulting_valid_fp = 776 drm_fixp_from_fraction(tu->valid_boundary_link, 1); 777 778 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 779 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 780 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 781 782 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1); 783 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; 784 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp); 785 786 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 787 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 788 789 compare_result_1 = _tu_param_compare(tu->hbp_time_fp, 790 tu->delay_start_time_fp); 791 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ 792 tu->min_hblank_violated = 1; 793 794 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp); 795 796 compare_result_2 = _tu_param_compare(tu->hactive_time_fp, 797 tu->delay_start_time_fp); 798 if (compare_result_2 == 2) 799 tu->min_hblank_violated = 1; 800 801 tu->delay_start_time_fp = 0; 802 803 /* brute force */ 804 805 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; 806 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; 807 808 temp = drm_fixp2int(tu->diff_abs_fp); 809 if (!temp && tu->diff_abs_fp <= 0xffff) 810 tu->diff_abs_fp = 0; 811 812 /* if(diff_abs < 0) diff_abs *= -1 */ 813 if (tu->diff_abs_fp < 0) 814 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1); 815 816 tu->boundary_mod_lower_err = 0; 817 if ((tu->diff_abs_fp != 0 && 818 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || 819 (tu->even_distribution_legacy == 0) || 820 (DP_BRUTE_FORCE == 1))) || 821 (tu->min_hblank_violated == 1)) { 822 do { 823 tu->err_fp = drm_fixp_from_fraction(1000, 1); 824 825 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 826 temp2_fp = drm_fixp_from_fraction( 827 tu->delay_start_link_extra_pixclk, 1); 828 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 829 830 if (temp1_fp) 831 tu->extra_buffer_margin = 832 drm_fixp2int_ceil(temp1_fp); 833 else 834 tu->extra_buffer_margin = 0; 835 836 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 837 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 838 839 if (temp1_fp) 840 tu->n_symbols = drm_fixp2int_ceil(temp1_fp); 841 else 842 tu->n_symbols = 0; 843 844 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 845 for (tu->i_upper_boundary_count = 1; 846 tu->i_upper_boundary_count <= 15; 847 tu->i_upper_boundary_count++) { 848 for (tu->i_lower_boundary_count = 1; 849 tu->i_lower_boundary_count <= 15; 850 tu->i_lower_boundary_count++) { 851 _tu_valid_boundary_calc(tu); 852 } 853 } 854 } 855 tu->delay_start_link_extra_pixclk--; 856 } while (tu->boundary_moderation_en != true && 857 tu->boundary_mod_lower_err == 1 && 858 tu->delay_start_link_extra_pixclk != 0); 859 860 if (tu->boundary_moderation_en == true) { 861 temp1_fp = drm_fixp_from_fraction( 862 (tu->upper_boundary_count * 863 tu->valid_boundary_link + 864 tu->lower_boundary_count * 865 (tu->valid_boundary_link - 1)), 1); 866 temp2_fp = drm_fixp_from_fraction( 867 (tu->upper_boundary_count + 868 tu->lower_boundary_count), 1); 869 tu->resulting_valid_fp = 870 drm_fixp_div(temp1_fp, temp2_fp); 871 872 temp1_fp = drm_fixp_from_fraction( 873 tu->tu_size_desired, 1); 874 tu->ratio_by_tu_fp = 875 drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 876 877 tu->valid_lower_boundary_link = 878 tu->valid_boundary_link - 1; 879 880 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 881 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 882 temp2_fp = drm_fixp_div(temp1_fp, 883 tu->resulting_valid_fp); 884 tu->n_tus = drm_fixp2int(temp2_fp); 885 886 tu->tu_size_minus1 = tu->tu_size_desired - 1; 887 tu->even_distribution_BF = 1; 888 889 temp1_fp = 890 drm_fixp_from_fraction(tu->tu_size_desired, 1); 891 temp2_fp = 892 drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 893 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 894 } 895 } 896 897 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp); 898 899 if (temp2_fp) 900 temp = drm_fixp2int_ceil(temp2_fp); 901 else 902 temp = 0; 903 904 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 905 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 906 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 907 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); 908 temp1_fp = drm_fixp_from_fraction(temp, 1); 909 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 910 temp = drm_fixp2int(temp2_fp); 911 912 if (tu->async_en) 913 tu->delay_start_link += (int)temp; 914 915 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 916 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 917 918 /* OUTPUTS */ 919 tu_table->valid_boundary_link = tu->valid_boundary_link; 920 tu_table->delay_start_link = tu->delay_start_link; 921 tu_table->boundary_moderation_en = tu->boundary_moderation_en; 922 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; 923 tu_table->upper_boundary_count = tu->upper_boundary_count; 924 tu_table->lower_boundary_count = tu->lower_boundary_count; 925 tu_table->tu_size_minus1 = tu->tu_size_minus1; 926 927 DRM_DEBUG_DP("TU: valid_boundary_link: %d\n", 928 tu_table->valid_boundary_link); 929 DRM_DEBUG_DP("TU: delay_start_link: %d\n", 930 tu_table->delay_start_link); 931 DRM_DEBUG_DP("TU: boundary_moderation_en: %d\n", 932 tu_table->boundary_moderation_en); 933 DRM_DEBUG_DP("TU: valid_lower_boundary_link: %d\n", 934 tu_table->valid_lower_boundary_link); 935 DRM_DEBUG_DP("TU: upper_boundary_count: %d\n", 936 tu_table->upper_boundary_count); 937 DRM_DEBUG_DP("TU: lower_boundary_count: %d\n", 938 tu_table->lower_boundary_count); 939 DRM_DEBUG_DP("TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1); 940 941 kfree(tu); 942 } 943 944 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, 945 struct dp_vc_tu_mapping_table *tu_table) 946 { 947 struct dp_tu_calc_input in; 948 struct drm_display_mode *drm_mode; 949 950 drm_mode = &ctrl->panel->dp_mode.drm_mode; 951 952 in.lclk = ctrl->link->link_params.rate / 1000; 953 in.pclk_khz = drm_mode->clock; 954 in.hactive = drm_mode->hdisplay; 955 in.hporch = drm_mode->htotal - drm_mode->hdisplay; 956 in.nlanes = ctrl->link->link_params.num_lanes; 957 in.bpp = ctrl->panel->dp_mode.bpp; 958 in.pixel_enc = 444; 959 in.dsc_en = 0; 960 in.async_en = 0; 961 in.fec_en = 0; 962 in.num_of_dsc_slices = 0; 963 in.compress_ratio = 100; 964 965 _dp_ctrl_calc_tu(&in, tu_table); 966 } 967 968 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl) 969 { 970 u32 dp_tu = 0x0; 971 u32 valid_boundary = 0x0; 972 u32 valid_boundary2 = 0x0; 973 struct dp_vc_tu_mapping_table tu_calc_table; 974 975 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); 976 977 dp_tu |= tu_calc_table.tu_size_minus1; 978 valid_boundary |= tu_calc_table.valid_boundary_link; 979 valid_boundary |= (tu_calc_table.delay_start_link << 16); 980 981 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); 982 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); 983 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); 984 985 if (tu_calc_table.boundary_moderation_en) 986 valid_boundary2 |= BIT(0); 987 988 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", 989 dp_tu, valid_boundary, valid_boundary2); 990 991 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, 992 dp_tu, valid_boundary, valid_boundary2); 993 } 994 995 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) 996 { 997 int ret = 0; 998 999 if (!wait_for_completion_timeout(&ctrl->video_comp, 1000 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { 1001 DRM_ERROR("wait4video timedout\n"); 1002 ret = -ETIMEDOUT; 1003 } 1004 return ret; 1005 } 1006 1007 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) 1008 { 1009 struct dp_link *link = ctrl->link; 1010 int ret = 0, lane, lane_cnt; 1011 u8 buf[4]; 1012 u32 max_level_reached = 0; 1013 u32 voltage_swing_level = link->phy_params.v_level; 1014 u32 pre_emphasis_level = link->phy_params.p_level; 1015 1016 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, 1017 voltage_swing_level, pre_emphasis_level); 1018 1019 if (ret) 1020 return ret; 1021 1022 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) { 1023 DRM_DEBUG_DP("max. voltage swing level reached %d\n", 1024 voltage_swing_level); 1025 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; 1026 } 1027 1028 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) { 1029 DRM_DEBUG_DP("max. pre-emphasis level reached %d\n", 1030 pre_emphasis_level); 1031 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1032 } 1033 1034 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; 1035 1036 lane_cnt = ctrl->link->link_params.num_lanes; 1037 for (lane = 0; lane < lane_cnt; lane++) 1038 buf[lane] = voltage_swing_level | pre_emphasis_level 1039 | max_level_reached; 1040 1041 DRM_DEBUG_DP("sink: p|v=0x%x\n", voltage_swing_level 1042 | pre_emphasis_level); 1043 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET, 1044 buf, lane_cnt); 1045 if (ret == lane_cnt) 1046 ret = 0; 1047 1048 return ret; 1049 } 1050 1051 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, 1052 u8 pattern) 1053 { 1054 u8 buf; 1055 int ret = 0; 1056 1057 DRM_DEBUG_DP("sink: pattern=%x\n", pattern); 1058 1059 buf = pattern; 1060 1061 if (pattern && pattern != DP_TRAINING_PATTERN_4) 1062 buf |= DP_LINK_SCRAMBLING_DISABLE; 1063 1064 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf); 1065 return ret == 1; 1066 } 1067 1068 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, 1069 u8 *link_status) 1070 { 1071 int ret = 0, len; 1072 1073 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 1074 if (len != DP_LINK_STATUS_SIZE) { 1075 DRM_ERROR("DP link status read failed, err: %d\n", len); 1076 ret = -EINVAL; 1077 } 1078 1079 return ret; 1080 } 1081 1082 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, 1083 struct dp_cr_status *cr, int *training_step) 1084 { 1085 int tries, old_v_level, ret = 0; 1086 u8 link_status[DP_LINK_STATUS_SIZE]; 1087 int const maximum_retries = 4; 1088 1089 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1090 1091 *training_step = DP_TRAINING_1; 1092 1093 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); 1094 if (ret) 1095 return ret; 1096 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1097 DP_LINK_SCRAMBLING_DISABLE); 1098 1099 ret = dp_ctrl_update_vx_px(ctrl); 1100 if (ret) 1101 return ret; 1102 1103 tries = 0; 1104 old_v_level = ctrl->link->phy_params.v_level; 1105 for (tries = 0; tries < maximum_retries; tries++) { 1106 drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd); 1107 1108 ret = dp_ctrl_read_link_status(ctrl, link_status); 1109 if (ret) 1110 return ret; 1111 1112 cr->lane_0_1 = link_status[0]; 1113 cr->lane_2_3 = link_status[1]; 1114 1115 if (drm_dp_clock_recovery_ok(link_status, 1116 ctrl->link->link_params.num_lanes)) { 1117 return 0; 1118 } 1119 1120 if (ctrl->link->phy_params.v_level >= 1121 DP_TRAIN_VOLTAGE_SWING_MAX) { 1122 DRM_ERROR_RATELIMITED("max v_level reached\n"); 1123 return -EAGAIN; 1124 } 1125 1126 if (old_v_level != ctrl->link->phy_params.v_level) { 1127 tries = 0; 1128 old_v_level = ctrl->link->phy_params.v_level; 1129 } 1130 1131 DRM_DEBUG_DP("clock recovery not done, adjusting vx px\n"); 1132 1133 dp_link_adjust_levels(ctrl->link, link_status); 1134 ret = dp_ctrl_update_vx_px(ctrl); 1135 if (ret) 1136 return ret; 1137 } 1138 1139 DRM_ERROR("max tries reached\n"); 1140 return -ETIMEDOUT; 1141 } 1142 1143 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) 1144 { 1145 int ret = 0; 1146 1147 switch (ctrl->link->link_params.rate) { 1148 case 810000: 1149 ctrl->link->link_params.rate = 540000; 1150 break; 1151 case 540000: 1152 ctrl->link->link_params.rate = 270000; 1153 break; 1154 case 270000: 1155 ctrl->link->link_params.rate = 162000; 1156 break; 1157 case 162000: 1158 default: 1159 ret = -EINVAL; 1160 break; 1161 }; 1162 1163 if (!ret) 1164 DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate); 1165 1166 return ret; 1167 } 1168 1169 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) 1170 { 1171 1172 if (ctrl->link->link_params.num_lanes == 1) 1173 return -1; 1174 1175 ctrl->link->link_params.num_lanes /= 2; 1176 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; 1177 1178 ctrl->link->phy_params.p_level = 0; 1179 ctrl->link->phy_params.v_level = 0; 1180 1181 return 0; 1182 } 1183 1184 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) 1185 { 1186 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); 1187 drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); 1188 } 1189 1190 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 1191 struct dp_cr_status *cr, int *training_step) 1192 { 1193 int tries = 0, ret = 0; 1194 char pattern; 1195 int const maximum_retries = 5; 1196 u8 link_status[DP_LINK_STATUS_SIZE]; 1197 1198 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1199 1200 *training_step = DP_TRAINING_2; 1201 1202 if (drm_dp_tps3_supported(ctrl->panel->dpcd)) 1203 pattern = DP_TRAINING_PATTERN_3; 1204 else 1205 pattern = DP_TRAINING_PATTERN_2; 1206 1207 ret = dp_ctrl_update_vx_px(ctrl); 1208 if (ret) 1209 return ret; 1210 1211 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); 1212 if (ret) 1213 return ret; 1214 1215 dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); 1216 1217 for (tries = 0; tries <= maximum_retries; tries++) { 1218 drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); 1219 1220 ret = dp_ctrl_read_link_status(ctrl, link_status); 1221 if (ret) 1222 return ret; 1223 cr->lane_0_1 = link_status[0]; 1224 cr->lane_2_3 = link_status[1]; 1225 1226 if (drm_dp_channel_eq_ok(link_status, 1227 ctrl->link->link_params.num_lanes)) { 1228 return 0; 1229 } 1230 1231 dp_link_adjust_levels(ctrl->link, link_status); 1232 ret = dp_ctrl_update_vx_px(ctrl); 1233 if (ret) 1234 return ret; 1235 1236 } 1237 1238 return -ETIMEDOUT; 1239 } 1240 1241 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl); 1242 1243 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 1244 struct dp_cr_status *cr, int *training_step) 1245 { 1246 int ret = 0; 1247 u8 encoding = DP_SET_ANSI_8B10B; 1248 struct dp_link_info link_info = {0}; 1249 1250 dp_ctrl_config_ctrl(ctrl); 1251 1252 link_info.num_lanes = ctrl->link->link_params.num_lanes; 1253 link_info.rate = ctrl->link->link_params.rate; 1254 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; 1255 1256 dp_aux_link_configure(ctrl->aux, &link_info); 1257 drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, 1258 &encoding, 1); 1259 1260 ret = dp_ctrl_link_train_1(ctrl, cr, training_step); 1261 if (ret) { 1262 DRM_ERROR("link training #1 failed. ret=%d\n", ret); 1263 goto end; 1264 } 1265 1266 /* print success info as this is a result of user initiated action */ 1267 DRM_DEBUG_DP("link training #1 successful\n"); 1268 1269 ret = dp_ctrl_link_train_2(ctrl, cr, training_step); 1270 if (ret) { 1271 DRM_ERROR("link training #2 failed. ret=%d\n", ret); 1272 goto end; 1273 } 1274 1275 /* print success info as this is a result of user initiated action */ 1276 DRM_DEBUG_DP("link training #2 successful\n"); 1277 1278 end: 1279 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1280 1281 return ret; 1282 } 1283 1284 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, 1285 struct dp_cr_status *cr, int *training_step) 1286 { 1287 int ret = 0; 1288 1289 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 1290 1291 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1292 return ret; 1293 1294 /* 1295 * As part of previous calls, DP controller state might have 1296 * transitioned to PUSH_IDLE. In order to start transmitting 1297 * a link training pattern, we have to first do soft reset. 1298 */ 1299 dp_catalog_ctrl_reset(ctrl->catalog); 1300 1301 ret = dp_ctrl_link_train(ctrl, cr, training_step); 1302 1303 return ret; 1304 } 1305 1306 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, 1307 enum dp_pm_type module, char *name, unsigned long rate) 1308 { 1309 u32 num = ctrl->parser->mp[module].num_clk; 1310 struct dss_clk *cfg = ctrl->parser->mp[module].clk_config; 1311 1312 while (num && strcmp(cfg->clk_name, name)) { 1313 num--; 1314 cfg++; 1315 } 1316 1317 DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name); 1318 1319 if (num) 1320 cfg->rate = rate; 1321 else 1322 DRM_ERROR("%s clock doesn't exit to set rate %lu\n", 1323 name, rate); 1324 } 1325 1326 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) 1327 { 1328 int ret = 0; 1329 struct dp_io *dp_io = &ctrl->parser->io; 1330 struct phy *phy = dp_io->phy; 1331 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; 1332 1333 opts_dp->lanes = ctrl->link->link_params.num_lanes; 1334 opts_dp->link_rate = ctrl->link->link_params.rate / 100; 1335 dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", 1336 ctrl->link->link_params.rate * 1000); 1337 1338 phy_configure(phy, &dp_io->phy_opts); 1339 phy_power_on(phy); 1340 1341 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); 1342 if (ret) 1343 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); 1344 1345 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n", 1346 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); 1347 1348 return ret; 1349 } 1350 1351 static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) 1352 { 1353 int ret = 0; 1354 1355 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", 1356 ctrl->dp_ctrl.pixel_rate * 1000); 1357 1358 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); 1359 if (ret) 1360 DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret); 1361 1362 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n", 1363 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); 1364 1365 return ret; 1366 } 1367 1368 int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip) 1369 { 1370 struct dp_ctrl_private *ctrl; 1371 struct dp_io *dp_io; 1372 struct phy *phy; 1373 1374 if (!dp_ctrl) { 1375 DRM_ERROR("Invalid input data\n"); 1376 return -EINVAL; 1377 } 1378 1379 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1380 dp_io = &ctrl->parser->io; 1381 phy = dp_io->phy; 1382 1383 ctrl->dp_ctrl.orientation = flip; 1384 1385 dp_catalog_ctrl_phy_reset(ctrl->catalog); 1386 phy_init(phy); 1387 dp_catalog_ctrl_enable_irq(ctrl->catalog, true); 1388 1389 return 0; 1390 } 1391 1392 /** 1393 * dp_ctrl_host_deinit() - Uninitialize DP controller 1394 * @dp_ctrl: Display Port Driver data 1395 * 1396 * Perform required steps to uninitialize DP controller 1397 * and its resources. 1398 */ 1399 void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl) 1400 { 1401 struct dp_ctrl_private *ctrl; 1402 struct dp_io *dp_io; 1403 struct phy *phy; 1404 1405 if (!dp_ctrl) { 1406 DRM_ERROR("Invalid input data\n"); 1407 return; 1408 } 1409 1410 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1411 dp_io = &ctrl->parser->io; 1412 phy = dp_io->phy; 1413 1414 dp_catalog_ctrl_enable_irq(ctrl->catalog, false); 1415 phy_exit(phy); 1416 1417 DRM_DEBUG_DP("Host deinitialized successfully\n"); 1418 } 1419 1420 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) 1421 { 1422 u8 *dpcd = ctrl->panel->dpcd; 1423 1424 /* 1425 * For better interop experience, used a fixed NVID=0x8000 1426 * whenever connected to a VGA dongle downstream. 1427 */ 1428 if (drm_dp_is_branch(dpcd)) 1429 return (drm_dp_has_quirk(&ctrl->panel->desc, 1430 DP_DPCD_QUIRK_CONSTANT_N)); 1431 1432 return false; 1433 } 1434 1435 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) 1436 { 1437 int ret = 0; 1438 struct dp_io *dp_io = &ctrl->parser->io; 1439 struct phy *phy = dp_io->phy; 1440 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; 1441 1442 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1443 opts_dp->lanes = ctrl->link->link_params.num_lanes; 1444 phy_configure(phy, &dp_io->phy_opts); 1445 /* 1446 * Disable and re-enable the mainlink clock since the 1447 * link clock might have been adjusted as part of the 1448 * link maintenance. 1449 */ 1450 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1451 if (ret) { 1452 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); 1453 return ret; 1454 } 1455 phy_power_off(phy); 1456 /* hw recommended delay before re-enabling clocks */ 1457 msleep(20); 1458 1459 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1460 if (ret) { 1461 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); 1462 return ret; 1463 } 1464 1465 return ret; 1466 } 1467 1468 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) 1469 { 1470 struct dp_io *dp_io; 1471 struct phy *phy; 1472 int ret; 1473 1474 dp_io = &ctrl->parser->io; 1475 phy = dp_io->phy; 1476 1477 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1478 1479 dp_catalog_ctrl_reset(ctrl->catalog); 1480 1481 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1482 if (ret) { 1483 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1484 } 1485 1486 phy_power_off(phy); 1487 phy_exit(phy); 1488 1489 return 0; 1490 } 1491 1492 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) 1493 { 1494 int ret = 0; 1495 struct dp_cr_status cr; 1496 int training_step = DP_TRAINING_NONE; 1497 1498 dp_ctrl_push_idle(&ctrl->dp_ctrl); 1499 dp_catalog_ctrl_reset(ctrl->catalog); 1500 1501 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1502 1503 ret = dp_ctrl_setup_main_link(ctrl, &cr, &training_step); 1504 if (ret) 1505 goto end; 1506 1507 dp_ctrl_clear_training_pattern(ctrl); 1508 1509 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1510 1511 ret = dp_ctrl_wait4video_ready(ctrl); 1512 end: 1513 return ret; 1514 } 1515 1516 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) 1517 { 1518 int ret = 0; 1519 1520 if (!ctrl->link->phy_params.phy_test_pattern_sel) { 1521 DRM_DEBUG_DP("no test pattern selected by sink\n"); 1522 return ret; 1523 } 1524 1525 /* 1526 * The global reset will need DP link related clocks to be 1527 * running. Add the global reset just before disabling the 1528 * link clocks and core clocks. 1529 */ 1530 ret = dp_ctrl_off(&ctrl->dp_ctrl); 1531 if (ret) { 1532 DRM_ERROR("failed to disable DP controller\n"); 1533 return ret; 1534 } 1535 1536 ret = dp_ctrl_on_link(&ctrl->dp_ctrl); 1537 if (!ret) 1538 ret = dp_ctrl_on_stream(&ctrl->dp_ctrl); 1539 else 1540 DRM_ERROR("failed to enable DP link controller\n"); 1541 1542 return ret; 1543 } 1544 1545 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) 1546 { 1547 bool success = false; 1548 u32 pattern_sent = 0x0; 1549 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; 1550 1551 DRM_DEBUG_DP("request: 0x%x\n", pattern_requested); 1552 1553 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog, 1554 ctrl->link->phy_params.v_level, 1555 ctrl->link->phy_params.p_level)) { 1556 DRM_ERROR("Failed to set v/p levels\n"); 1557 return false; 1558 } 1559 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); 1560 dp_ctrl_update_vx_px(ctrl); 1561 dp_link_send_test_response(ctrl->link); 1562 1563 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); 1564 1565 switch (pattern_sent) { 1566 case MR_LINK_TRAINING1: 1567 success = (pattern_requested == 1568 DP_PHY_TEST_PATTERN_D10_2); 1569 break; 1570 case MR_LINK_SYMBOL_ERM: 1571 success = ((pattern_requested == 1572 DP_PHY_TEST_PATTERN_ERROR_COUNT) || 1573 (pattern_requested == 1574 DP_PHY_TEST_PATTERN_CP2520)); 1575 break; 1576 case MR_LINK_PRBS7: 1577 success = (pattern_requested == 1578 DP_PHY_TEST_PATTERN_PRBS7); 1579 break; 1580 case MR_LINK_CUSTOM80: 1581 success = (pattern_requested == 1582 DP_PHY_TEST_PATTERN_80BIT_CUSTOM); 1583 break; 1584 case MR_LINK_TRAINING4: 1585 success = (pattern_requested == 1586 DP_PHY_TEST_PATTERN_SEL_MASK); 1587 break; 1588 default: 1589 success = false; 1590 } 1591 1592 DRM_DEBUG_DP("%s: test->0x%x\n", success ? "success" : "failed", 1593 pattern_requested); 1594 return success; 1595 } 1596 1597 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) 1598 { 1599 struct dp_ctrl_private *ctrl; 1600 u32 sink_request = 0x0; 1601 1602 if (!dp_ctrl) { 1603 DRM_ERROR("invalid input\n"); 1604 return; 1605 } 1606 1607 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1608 sink_request = ctrl->link->sink_request; 1609 1610 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1611 DRM_DEBUG_DP("PHY_TEST_PATTERN request\n"); 1612 if (dp_ctrl_process_phy_test_request(ctrl)) { 1613 DRM_ERROR("process phy_test_req failed\n"); 1614 return; 1615 } 1616 } 1617 1618 if (sink_request & DP_LINK_STATUS_UPDATED) { 1619 if (dp_ctrl_link_maintenance(ctrl)) { 1620 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1621 return; 1622 } 1623 } 1624 1625 if (sink_request & DP_TEST_LINK_TRAINING) { 1626 dp_link_send_test_response(ctrl->link); 1627 if (dp_ctrl_link_maintenance(ctrl)) { 1628 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1629 return; 1630 } 1631 } 1632 } 1633 1634 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 1635 { 1636 int rc = 0; 1637 struct dp_ctrl_private *ctrl; 1638 u32 rate = 0; 1639 int link_train_max_retries = 5; 1640 u32 const phy_cts_pixel_clk_khz = 148500; 1641 struct dp_cr_status cr; 1642 unsigned int training_step; 1643 1644 if (!dp_ctrl) 1645 return -EINVAL; 1646 1647 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1648 1649 rate = ctrl->panel->link_info.rate; 1650 1651 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); 1652 1653 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1654 DRM_DEBUG_DP("using phy test link parameters\n"); 1655 if (!ctrl->panel->dp_mode.drm_mode.clock) 1656 ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz; 1657 } else { 1658 ctrl->link->link_params.rate = rate; 1659 ctrl->link->link_params.num_lanes = 1660 ctrl->panel->link_info.num_lanes; 1661 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1662 } 1663 1664 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", 1665 ctrl->link->link_params.rate, 1666 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); 1667 1668 rc = dp_ctrl_enable_mainlink_clocks(ctrl); 1669 if (rc) 1670 return rc; 1671 1672 while (--link_train_max_retries) { 1673 rc = dp_ctrl_reinitialize_mainlink(ctrl); 1674 if (rc) { 1675 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", 1676 rc); 1677 break; 1678 } 1679 1680 training_step = DP_TRAINING_NONE; 1681 rc = dp_ctrl_setup_main_link(ctrl, &cr, &training_step); 1682 if (rc == 0) { 1683 /* training completed successfully */ 1684 break; 1685 } else if (training_step == DP_TRAINING_1) { 1686 /* link train_1 failed */ 1687 if (!dp_catalog_link_is_connected(ctrl->catalog)) { 1688 break; 1689 } 1690 1691 rc = dp_ctrl_link_rate_down_shift(ctrl); 1692 if (rc < 0) { /* already in RBR = 1.6G */ 1693 if (cr.lane_0_1 & DP_LANE0_1_CR_DONE) { 1694 /* 1695 * some lanes are ready, 1696 * reduce lane number 1697 */ 1698 rc = dp_ctrl_link_lane_down_shift(ctrl); 1699 if (rc < 0) { /* lane == 1 already */ 1700 /* end with failure */ 1701 break; 1702 } 1703 } else { 1704 /* end with failure */ 1705 break; /* lane == 1 already */ 1706 } 1707 } 1708 } else if (training_step == DP_TRAINING_2) { 1709 /* link train_2 failed, lower lane rate */ 1710 if (!dp_catalog_link_is_connected(ctrl->catalog)) { 1711 break; 1712 } 1713 1714 rc = dp_ctrl_link_lane_down_shift(ctrl); 1715 if (rc < 0) { 1716 /* end with failure */ 1717 break; /* lane == 1 already */ 1718 } 1719 } 1720 } 1721 1722 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1723 return rc; 1724 1725 /* stop txing train pattern */ 1726 dp_ctrl_clear_training_pattern(ctrl); 1727 1728 /* 1729 * keep transmitting idle pattern until video ready 1730 * to avoid main link from loss of sync 1731 */ 1732 if (rc == 0) /* link train successfully */ 1733 dp_ctrl_push_idle(dp_ctrl); 1734 else { 1735 /* link training failed */ 1736 dp_ctrl_deinitialize_mainlink(ctrl); 1737 rc = -ECONNRESET; 1738 } 1739 1740 return rc; 1741 } 1742 1743 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) 1744 { 1745 u32 rate = 0; 1746 int ret = 0; 1747 bool mainlink_ready = false; 1748 struct dp_ctrl_private *ctrl; 1749 1750 if (!dp_ctrl) 1751 return -EINVAL; 1752 1753 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1754 1755 rate = ctrl->panel->link_info.rate; 1756 1757 ctrl->link->link_params.rate = rate; 1758 ctrl->link->link_params.num_lanes = ctrl->panel->link_info.num_lanes; 1759 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1760 1761 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", 1762 ctrl->link->link_params.rate, 1763 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); 1764 1765 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */ 1766 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1767 if (ret) { 1768 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); 1769 goto end; 1770 } 1771 } 1772 1773 ret = dp_ctrl_enable_stream_clocks(ctrl); 1774 if (ret) { 1775 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1776 goto end; 1777 } 1778 1779 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1780 dp_ctrl_send_phy_test_pattern(ctrl); 1781 return 0; 1782 } 1783 1784 /* 1785 * Set up transfer unit values and set controller state to send 1786 * video. 1787 */ 1788 dp_ctrl_configure_source_params(ctrl); 1789 1790 dp_catalog_ctrl_config_msa(ctrl->catalog, 1791 ctrl->link->link_params.rate, 1792 ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl)); 1793 1794 reinit_completion(&ctrl->video_comp); 1795 1796 dp_ctrl_setup_tr_unit(ctrl); 1797 1798 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1799 1800 ret = dp_ctrl_wait4video_ready(ctrl); 1801 if (ret) 1802 return ret; 1803 1804 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); 1805 DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); 1806 1807 end: 1808 return ret; 1809 } 1810 1811 int dp_ctrl_off(struct dp_ctrl *dp_ctrl) 1812 { 1813 struct dp_ctrl_private *ctrl; 1814 struct dp_io *dp_io; 1815 struct phy *phy; 1816 int ret = 0; 1817 1818 if (!dp_ctrl) 1819 return -EINVAL; 1820 1821 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1822 dp_io = &ctrl->parser->io; 1823 phy = dp_io->phy; 1824 1825 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1826 1827 dp_catalog_ctrl_reset(ctrl->catalog); 1828 1829 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); 1830 if (ret) 1831 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); 1832 1833 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1834 if (ret) { 1835 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1836 } 1837 1838 phy_power_off(phy); 1839 phy_exit(phy); 1840 1841 DRM_DEBUG_DP("DP off done\n"); 1842 return ret; 1843 } 1844 1845 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl) 1846 { 1847 struct dp_ctrl_private *ctrl; 1848 u32 isr; 1849 1850 if (!dp_ctrl) 1851 return; 1852 1853 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1854 1855 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog); 1856 1857 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { 1858 DRM_DEBUG_DP("dp_video_ready\n"); 1859 complete(&ctrl->video_comp); 1860 } 1861 1862 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { 1863 DRM_DEBUG_DP("idle_patterns_sent\n"); 1864 complete(&ctrl->idle_comp); 1865 } 1866 } 1867 1868 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, 1869 struct dp_panel *panel, struct drm_dp_aux *aux, 1870 struct dp_power *power, struct dp_catalog *catalog, 1871 struct dp_parser *parser) 1872 { 1873 struct dp_ctrl_private *ctrl; 1874 int ret; 1875 1876 if (!dev || !panel || !aux || 1877 !link || !catalog) { 1878 DRM_ERROR("invalid input\n"); 1879 return ERR_PTR(-EINVAL); 1880 } 1881 1882 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1883 if (!ctrl) { 1884 DRM_ERROR("Mem allocation failure\n"); 1885 return ERR_PTR(-ENOMEM); 1886 } 1887 1888 ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link"); 1889 if (IS_ERR(ctrl->opp_table)) { 1890 dev_err(dev, "invalid DP OPP table in device tree\n"); 1891 /* caller do PTR_ERR(ctrl->opp_table) */ 1892 return (struct dp_ctrl *)ctrl->opp_table; 1893 } 1894 1895 /* OPP table is optional */ 1896 ret = dev_pm_opp_of_add_table(dev); 1897 if (ret) { 1898 dev_err(dev, "failed to add DP OPP table\n"); 1899 dev_pm_opp_put_clkname(ctrl->opp_table); 1900 ctrl->opp_table = NULL; 1901 } 1902 1903 init_completion(&ctrl->idle_comp); 1904 init_completion(&ctrl->video_comp); 1905 1906 /* in parameters */ 1907 ctrl->parser = parser; 1908 ctrl->panel = panel; 1909 ctrl->power = power; 1910 ctrl->aux = aux; 1911 ctrl->link = link; 1912 ctrl->catalog = catalog; 1913 ctrl->dev = dev; 1914 1915 return &ctrl->dp_ctrl; 1916 } 1917 1918 void dp_ctrl_put(struct dp_ctrl *dp_ctrl) 1919 { 1920 struct dp_ctrl_private *ctrl; 1921 1922 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1923 1924 if (ctrl->opp_table) { 1925 dev_pm_opp_of_remove_table(ctrl->dev); 1926 dev_pm_opp_put_clkname(ctrl->opp_table); 1927 ctrl->opp_table = NULL; 1928 } 1929 } 1930