1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ 7 8 #include <linux/types.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/phy/phy.h> 12 #include <linux/phy/phy-dp.h> 13 #include <linux/pm_opp.h> 14 #include <drm/drm_fixed.h> 15 #include <drm/drm_dp_helper.h> 16 #include <drm/drm_print.h> 17 18 #include "dp_reg.h" 19 #include "dp_ctrl.h" 20 #include "dp_link.h" 21 22 #define DP_KHZ_TO_HZ 1000 23 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ 24 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) 25 26 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) 27 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) 28 29 #define MR_LINK_TRAINING1 0x8 30 #define MR_LINK_SYMBOL_ERM 0x80 31 #define MR_LINK_PRBS7 0x100 32 #define MR_LINK_CUSTOM80 0x200 33 #define MR_LINK_TRAINING4 0x40 34 35 enum { 36 DP_TRAINING_NONE, 37 DP_TRAINING_1, 38 DP_TRAINING_2, 39 }; 40 41 struct dp_tu_calc_input { 42 u64 lclk; /* 162, 270, 540 and 810 */ 43 u64 pclk_khz; /* in KHz */ 44 u64 hactive; /* active h-width */ 45 u64 hporch; /* bp + fp + pulse */ 46 int nlanes; /* no.of.lanes */ 47 int bpp; /* bits */ 48 int pixel_enc; /* 444, 420, 422 */ 49 int dsc_en; /* dsc on/off */ 50 int async_en; /* async mode */ 51 int fec_en; /* fec */ 52 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ 53 int num_of_dsc_slices; /* number of slices per line */ 54 }; 55 56 struct dp_vc_tu_mapping_table { 57 u32 vic; 58 u8 lanes; 59 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ 60 u8 bpp; 61 u8 valid_boundary_link; 62 u16 delay_start_link; 63 bool boundary_moderation_en; 64 u8 valid_lower_boundary_link; 65 u8 upper_boundary_count; 66 u8 lower_boundary_count; 67 u8 tu_size_minus1; 68 }; 69 70 struct dp_ctrl_private { 71 struct dp_ctrl dp_ctrl; 72 struct device *dev; 73 struct drm_dp_aux *aux; 74 struct dp_panel *panel; 75 struct dp_link *link; 76 struct dp_power *power; 77 struct dp_parser *parser; 78 struct dp_catalog *catalog; 79 80 struct completion idle_comp; 81 struct completion video_comp; 82 }; 83 84 struct dp_cr_status { 85 u8 lane_0_1; 86 u8 lane_2_3; 87 }; 88 89 #define DP_LANE0_1_CR_DONE 0x11 90 91 static int dp_aux_link_configure(struct drm_dp_aux *aux, 92 struct dp_link_info *link) 93 { 94 u8 values[2]; 95 int err; 96 97 values[0] = drm_dp_link_rate_to_bw_code(link->rate); 98 values[1] = link->num_lanes; 99 100 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 101 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 102 103 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); 104 if (err < 0) 105 return err; 106 107 return 0; 108 } 109 110 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) 111 { 112 struct dp_ctrl_private *ctrl; 113 114 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 115 116 reinit_completion(&ctrl->idle_comp); 117 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); 118 119 if (!wait_for_completion_timeout(&ctrl->idle_comp, 120 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) 121 pr_warn("PUSH_IDLE pattern timedout\n"); 122 123 pr_debug("mainlink off done\n"); 124 } 125 126 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) 127 { 128 u32 config = 0, tbd; 129 u8 *dpcd = ctrl->panel->dpcd; 130 131 /* Default-> LSCLK DIV: 1/4 LCLK */ 132 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); 133 134 /* Scrambler reset enable */ 135 if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) 136 config |= DP_CONFIGURATION_CTRL_ASSR; 137 138 tbd = dp_link_get_test_bits_depth(ctrl->link, 139 ctrl->panel->dp_mode.bpp); 140 141 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) { 142 pr_debug("BIT_DEPTH not set. Configure default\n"); 143 tbd = DP_TEST_BIT_DEPTH_8; 144 } 145 146 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; 147 148 /* Num of Lanes */ 149 config |= ((ctrl->link->link_params.num_lanes - 1) 150 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); 151 152 if (drm_dp_enhanced_frame_cap(dpcd)) 153 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; 154 155 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ 156 157 /* sync clock & static Mvid */ 158 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; 159 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; 160 161 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); 162 } 163 164 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) 165 { 166 u32 cc, tb; 167 168 dp_catalog_ctrl_lane_mapping(ctrl->catalog); 169 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 170 171 dp_ctrl_config_ctrl(ctrl); 172 173 tb = dp_link_get_test_bits_depth(ctrl->link, 174 ctrl->panel->dp_mode.bpp); 175 cc = dp_link_get_colorimetry_config(ctrl->link); 176 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); 177 dp_panel_timing_cfg(ctrl->panel); 178 } 179 180 /* 181 * The structure and few functions present below are IP/Hardware 182 * specific implementation. Most of the implementation will not 183 * have coding comments 184 */ 185 struct tu_algo_data { 186 s64 lclk_fp; 187 s64 pclk_fp; 188 s64 lwidth; 189 s64 lwidth_fp; 190 s64 hbp_relative_to_pclk; 191 s64 hbp_relative_to_pclk_fp; 192 int nlanes; 193 int bpp; 194 int pixelEnc; 195 int dsc_en; 196 int async_en; 197 int bpc; 198 199 uint delay_start_link_extra_pixclk; 200 int extra_buffer_margin; 201 s64 ratio_fp; 202 s64 original_ratio_fp; 203 204 s64 err_fp; 205 s64 n_err_fp; 206 s64 n_n_err_fp; 207 int tu_size; 208 int tu_size_desired; 209 int tu_size_minus1; 210 211 int valid_boundary_link; 212 s64 resulting_valid_fp; 213 s64 total_valid_fp; 214 s64 effective_valid_fp; 215 s64 effective_valid_recorded_fp; 216 int n_tus; 217 int n_tus_per_lane; 218 int paired_tus; 219 int remainder_tus; 220 int remainder_tus_upper; 221 int remainder_tus_lower; 222 int extra_bytes; 223 int filler_size; 224 int delay_start_link; 225 226 int extra_pclk_cycles; 227 int extra_pclk_cycles_in_link_clk; 228 s64 ratio_by_tu_fp; 229 s64 average_valid2_fp; 230 int new_valid_boundary_link; 231 int remainder_symbols_exist; 232 int n_symbols; 233 s64 n_remainder_symbols_per_lane_fp; 234 s64 last_partial_tu_fp; 235 s64 TU_ratio_err_fp; 236 237 int n_tus_incl_last_incomplete_tu; 238 int extra_pclk_cycles_tmp; 239 int extra_pclk_cycles_in_link_clk_tmp; 240 int extra_required_bytes_new_tmp; 241 int filler_size_tmp; 242 int lower_filler_size_tmp; 243 int delay_start_link_tmp; 244 245 bool boundary_moderation_en; 246 int boundary_mod_lower_err; 247 int upper_boundary_count; 248 int lower_boundary_count; 249 int i_upper_boundary_count; 250 int i_lower_boundary_count; 251 int valid_lower_boundary_link; 252 int even_distribution_BF; 253 int even_distribution_legacy; 254 int even_distribution; 255 int min_hblank_violated; 256 s64 delay_start_time_fp; 257 s64 hbp_time_fp; 258 s64 hactive_time_fp; 259 s64 diff_abs_fp; 260 261 s64 ratio; 262 }; 263 264 static int _tu_param_compare(s64 a, s64 b) 265 { 266 u32 a_sign; 267 u32 b_sign; 268 s64 a_temp, b_temp, minus_1; 269 270 if (a == b) 271 return 0; 272 273 minus_1 = drm_fixp_from_fraction(-1, 1); 274 275 a_sign = (a >> 32) & 0x80000000 ? 1 : 0; 276 277 b_sign = (b >> 32) & 0x80000000 ? 1 : 0; 278 279 if (a_sign > b_sign) 280 return 2; 281 else if (b_sign > a_sign) 282 return 1; 283 284 if (!a_sign && !b_sign) { /* positive */ 285 if (a > b) 286 return 1; 287 else 288 return 2; 289 } else { /* negative */ 290 a_temp = drm_fixp_mul(a, minus_1); 291 b_temp = drm_fixp_mul(b, minus_1); 292 293 if (a_temp > b_temp) 294 return 2; 295 else 296 return 1; 297 } 298 } 299 300 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in, 301 struct tu_algo_data *tu) 302 { 303 int nlanes = in->nlanes; 304 int dsc_num_slices = in->num_of_dsc_slices; 305 int dsc_num_bytes = 0; 306 int numerator; 307 s64 pclk_dsc_fp; 308 s64 dwidth_dsc_fp; 309 s64 hbp_dsc_fp; 310 311 int tot_num_eoc_symbols = 0; 312 int tot_num_hor_bytes = 0; 313 int tot_num_dummy_bytes = 0; 314 int dwidth_dsc_bytes = 0; 315 int eoc_bytes = 0; 316 317 s64 temp1_fp, temp2_fp, temp3_fp; 318 319 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1); 320 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000); 321 tu->lwidth = in->hactive; 322 tu->hbp_relative_to_pclk = in->hporch; 323 tu->nlanes = in->nlanes; 324 tu->bpp = in->bpp; 325 tu->pixelEnc = in->pixel_enc; 326 tu->dsc_en = in->dsc_en; 327 tu->async_en = in->async_en; 328 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1); 329 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1); 330 331 if (tu->pixelEnc == 420) { 332 temp1_fp = drm_fixp_from_fraction(2, 1); 333 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp); 334 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp); 335 tu->hbp_relative_to_pclk_fp = 336 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2); 337 } 338 339 if (tu->pixelEnc == 422) { 340 switch (tu->bpp) { 341 case 24: 342 tu->bpp = 16; 343 tu->bpc = 8; 344 break; 345 case 30: 346 tu->bpp = 20; 347 tu->bpc = 10; 348 break; 349 default: 350 tu->bpp = 16; 351 tu->bpc = 8; 352 break; 353 } 354 } else { 355 tu->bpc = tu->bpp/3; 356 } 357 358 if (!in->dsc_en) 359 goto fec_check; 360 361 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100); 362 temp2_fp = drm_fixp_from_fraction(in->bpp, 1); 363 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 364 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp); 365 366 temp1_fp = drm_fixp_from_fraction(8, 1); 367 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp); 368 369 numerator = drm_fixp2int(temp3_fp); 370 371 dsc_num_bytes = numerator / dsc_num_slices; 372 eoc_bytes = dsc_num_bytes % nlanes; 373 tot_num_eoc_symbols = nlanes * dsc_num_slices; 374 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; 375 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; 376 377 if (dsc_num_bytes == 0) 378 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes); 379 380 dwidth_dsc_bytes = (tot_num_hor_bytes + 381 tot_num_eoc_symbols + 382 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); 383 384 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3); 385 386 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp); 387 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp); 388 pclk_dsc_fp = temp1_fp; 389 390 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp); 391 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp); 392 hbp_dsc_fp = temp2_fp; 393 394 /* output */ 395 tu->pclk_fp = pclk_dsc_fp; 396 tu->lwidth_fp = dwidth_dsc_fp; 397 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; 398 399 fec_check: 400 if (in->fec_en) { 401 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */ 402 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp); 403 } 404 } 405 406 static void _tu_valid_boundary_calc(struct tu_algo_data *tu) 407 { 408 s64 temp1_fp, temp2_fp, temp, temp1, temp2; 409 int compare_result_1, compare_result_2, compare_result_3; 410 411 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 412 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 413 414 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 415 416 temp = (tu->i_upper_boundary_count * 417 tu->new_valid_boundary_link + 418 tu->i_lower_boundary_count * 419 (tu->new_valid_boundary_link-1)); 420 tu->average_valid2_fp = drm_fixp_from_fraction(temp, 421 (tu->i_upper_boundary_count + 422 tu->i_lower_boundary_count)); 423 424 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 425 temp2_fp = tu->lwidth_fp; 426 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 427 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 428 tu->n_tus = drm_fixp2int(temp2_fp); 429 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 430 tu->n_tus += 1; 431 432 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1); 433 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp); 434 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1); 435 temp2_fp = temp1_fp - temp2_fp; 436 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 437 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 438 tu->n_remainder_symbols_per_lane_fp = temp2_fp; 439 440 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 441 tu->last_partial_tu_fp = 442 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp, 443 temp1_fp); 444 445 if (tu->n_remainder_symbols_per_lane_fp != 0) 446 tu->remainder_symbols_exist = 1; 447 else 448 tu->remainder_symbols_exist = 0; 449 450 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes); 451 tu->n_tus_per_lane = drm_fixp2int(temp1_fp); 452 453 tu->paired_tus = (int)((tu->n_tus_per_lane) / 454 (tu->i_upper_boundary_count + 455 tu->i_lower_boundary_count)); 456 457 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * 458 (tu->i_upper_boundary_count + 459 tu->i_lower_boundary_count); 460 461 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { 462 tu->remainder_tus_upper = tu->i_upper_boundary_count; 463 tu->remainder_tus_lower = tu->remainder_tus - 464 tu->i_upper_boundary_count; 465 } else { 466 tu->remainder_tus_upper = tu->remainder_tus; 467 tu->remainder_tus_lower = 0; 468 } 469 470 temp = tu->paired_tus * (tu->i_upper_boundary_count * 471 tu->new_valid_boundary_link + 472 tu->i_lower_boundary_count * 473 (tu->new_valid_boundary_link - 1)) + 474 (tu->remainder_tus_upper * 475 tu->new_valid_boundary_link) + 476 (tu->remainder_tus_lower * 477 (tu->new_valid_boundary_link - 1)); 478 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1); 479 480 if (tu->remainder_symbols_exist) { 481 temp1_fp = tu->total_valid_fp + 482 tu->n_remainder_symbols_per_lane_fp; 483 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 484 temp2_fp = temp2_fp + tu->last_partial_tu_fp; 485 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp); 486 } else { 487 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1); 488 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp); 489 } 490 tu->effective_valid_fp = temp1_fp; 491 492 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 493 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 494 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; 495 496 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 497 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 498 tu->n_err_fp = tu->average_valid2_fp - temp2_fp; 499 500 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 501 502 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 503 temp2_fp = tu->lwidth_fp; 504 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 505 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp); 506 507 if (temp2_fp) 508 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp); 509 else 510 tu->n_tus_incl_last_incomplete_tu = 0; 511 512 temp1 = 0; 513 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 514 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 515 temp1_fp = tu->average_valid2_fp - temp2_fp; 516 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1); 517 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 518 519 if (temp1_fp) 520 temp1 = drm_fixp2int_ceil(temp1_fp); 521 522 temp = tu->i_upper_boundary_count * tu->nlanes; 523 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 524 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 525 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1); 526 temp2_fp = temp1_fp - temp2_fp; 527 temp1_fp = drm_fixp_from_fraction(temp, 1); 528 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 529 530 if (temp2_fp) 531 temp2 = drm_fixp2int_ceil(temp2_fp); 532 else 533 temp2 = 0; 534 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); 535 536 temp1_fp = drm_fixp_from_fraction(8, tu->bpp); 537 temp2_fp = drm_fixp_from_fraction( 538 tu->extra_required_bytes_new_tmp, 1); 539 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 540 541 if (temp1_fp) 542 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp); 543 else 544 tu->extra_pclk_cycles_tmp = 0; 545 546 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1); 547 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 548 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 549 550 if (temp1_fp) 551 tu->extra_pclk_cycles_in_link_clk_tmp = 552 drm_fixp2int_ceil(temp1_fp); 553 else 554 tu->extra_pclk_cycles_in_link_clk_tmp = 0; 555 556 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; 557 558 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; 559 560 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + 561 tu->lower_filler_size_tmp + 562 tu->extra_buffer_margin; 563 564 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1); 565 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 566 567 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp); 568 if (compare_result_1 == 2) 569 compare_result_1 = 1; 570 else 571 compare_result_1 = 0; 572 573 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp); 574 if (compare_result_2 == 2) 575 compare_result_2 = 1; 576 else 577 compare_result_2 = 0; 578 579 compare_result_3 = _tu_param_compare(tu->hbp_time_fp, 580 tu->delay_start_time_fp); 581 if (compare_result_3 == 2) 582 compare_result_3 = 0; 583 else 584 compare_result_3 = 1; 585 586 if (((tu->even_distribution == 1) || 587 ((tu->even_distribution_BF == 0) && 588 (tu->even_distribution_legacy == 0))) && 589 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && 590 compare_result_2 && 591 (compare_result_1 || (tu->min_hblank_violated == 1)) && 592 (tu->new_valid_boundary_link - 1) > 0 && 593 compare_result_3 && 594 (tu->delay_start_link_tmp <= 1023)) { 595 tu->upper_boundary_count = tu->i_upper_boundary_count; 596 tu->lower_boundary_count = tu->i_lower_boundary_count; 597 tu->err_fp = tu->n_n_err_fp; 598 tu->boundary_moderation_en = true; 599 tu->tu_size_desired = tu->tu_size; 600 tu->valid_boundary_link = tu->new_valid_boundary_link; 601 tu->effective_valid_recorded_fp = tu->effective_valid_fp; 602 tu->even_distribution_BF = 1; 603 tu->delay_start_link = tu->delay_start_link_tmp; 604 } else if (tu->boundary_mod_lower_err == 0) { 605 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, 606 tu->diff_abs_fp); 607 if (compare_result_1 == 2) 608 tu->boundary_mod_lower_err = 1; 609 } 610 } 611 612 static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in, 613 struct dp_vc_tu_mapping_table *tu_table) 614 { 615 struct tu_algo_data *tu; 616 int compare_result_1, compare_result_2; 617 u64 temp = 0; 618 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; 619 620 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */ 621 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */ 622 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */ 623 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000); 624 625 u8 DP_BRUTE_FORCE = 1; 626 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */ 627 uint EXTRA_PIXCLK_CYCLE_DELAY = 4; 628 uint HBLANK_MARGIN = 4; 629 630 tu = kzalloc(sizeof(*tu), GFP_KERNEL); 631 if (!tu) 632 return; 633 634 dp_panel_update_tu_timings(in, tu); 635 636 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ 637 638 temp1_fp = drm_fixp_from_fraction(4, 1); 639 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp); 640 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp); 641 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp); 642 643 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 644 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp); 645 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 646 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 647 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp); 648 649 tu->original_ratio_fp = tu->ratio_fp; 650 tu->boundary_moderation_en = false; 651 tu->upper_boundary_count = 0; 652 tu->lower_boundary_count = 0; 653 tu->i_upper_boundary_count = 0; 654 tu->i_lower_boundary_count = 0; 655 tu->valid_lower_boundary_link = 0; 656 tu->even_distribution_BF = 0; 657 tu->even_distribution_legacy = 0; 658 tu->even_distribution = 0; 659 tu->delay_start_time_fp = 0; 660 661 tu->err_fp = drm_fixp_from_fraction(1000, 1); 662 tu->n_err_fp = 0; 663 tu->n_n_err_fp = 0; 664 665 tu->ratio = drm_fixp2int(tu->ratio_fp); 666 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 667 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp); 668 if (temp2_fp != 0 && 669 !tu->ratio && tu->dsc_en == 0) { 670 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp); 671 tu->ratio = drm_fixp2int(tu->ratio_fp); 672 if (tu->ratio) 673 tu->ratio_fp = drm_fixp_from_fraction(1, 1); 674 } 675 676 if (tu->ratio > 1) 677 tu->ratio = 1; 678 679 if (tu->ratio == 1) 680 goto tu_size_calc; 681 682 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp); 683 if (!compare_result_1 || compare_result_1 == 1) 684 compare_result_1 = 1; 685 else 686 compare_result_1 = 0; 687 688 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp); 689 if (!compare_result_2 || compare_result_2 == 2) 690 compare_result_2 = 1; 691 else 692 compare_result_2 = 0; 693 694 if (tu->dsc_en && compare_result_1 && compare_result_2) { 695 HBLANK_MARGIN += 4; 696 DRM_DEBUG_DP("Info: increase HBLANK_MARGIN to %d\n", 697 HBLANK_MARGIN); 698 } 699 700 tu_size_calc: 701 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 702 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1); 703 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 704 temp = drm_fixp2int_ceil(temp2_fp); 705 temp1_fp = drm_fixp_from_fraction(temp, 1); 706 tu->n_err_fp = temp1_fp - temp2_fp; 707 708 if (tu->n_err_fp < tu->err_fp) { 709 tu->err_fp = tu->n_err_fp; 710 tu->tu_size_desired = tu->tu_size; 711 } 712 } 713 714 tu->tu_size_minus1 = tu->tu_size_desired - 1; 715 716 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 717 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 718 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp); 719 720 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 721 temp2_fp = tu->lwidth_fp; 722 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp); 723 724 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 725 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp); 726 tu->n_tus = drm_fixp2int(temp2_fp); 727 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) 728 tu->n_tus += 1; 729 730 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; 731 DRM_DEBUG_DP("Info: n_sym = %d, num_of_tus = %d\n", 732 tu->valid_boundary_link, tu->n_tus); 733 734 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 735 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 736 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1); 737 temp2_fp = temp1_fp - temp2_fp; 738 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1); 739 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 740 741 temp = drm_fixp2int(temp2_fp); 742 if (temp && temp2_fp) 743 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp); 744 else 745 tu->extra_bytes = 0; 746 747 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1); 748 temp2_fp = drm_fixp_from_fraction(8, tu->bpp); 749 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp); 750 751 if (temp && temp1_fp) 752 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp); 753 else 754 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp); 755 756 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 757 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1); 758 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 759 760 if (temp1_fp) 761 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp); 762 else 763 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp); 764 765 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; 766 767 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 768 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp); 769 770 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + 771 tu->filler_size + tu->extra_buffer_margin; 772 773 tu->resulting_valid_fp = 774 drm_fixp_from_fraction(tu->valid_boundary_link, 1); 775 776 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1); 777 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 778 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 779 780 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1); 781 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; 782 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp); 783 784 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 785 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 786 787 compare_result_1 = _tu_param_compare(tu->hbp_time_fp, 788 tu->delay_start_time_fp); 789 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ 790 tu->min_hblank_violated = 1; 791 792 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp); 793 794 compare_result_2 = _tu_param_compare(tu->hactive_time_fp, 795 tu->delay_start_time_fp); 796 if (compare_result_2 == 2) 797 tu->min_hblank_violated = 1; 798 799 tu->delay_start_time_fp = 0; 800 801 /* brute force */ 802 803 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; 804 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; 805 806 temp = drm_fixp2int(tu->diff_abs_fp); 807 if (!temp && tu->diff_abs_fp <= 0xffff) 808 tu->diff_abs_fp = 0; 809 810 /* if(diff_abs < 0) diff_abs *= -1 */ 811 if (tu->diff_abs_fp < 0) 812 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1); 813 814 tu->boundary_mod_lower_err = 0; 815 if ((tu->diff_abs_fp != 0 && 816 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || 817 (tu->even_distribution_legacy == 0) || 818 (DP_BRUTE_FORCE == 1))) || 819 (tu->min_hblank_violated == 1)) { 820 do { 821 tu->err_fp = drm_fixp_from_fraction(1000, 1); 822 823 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp); 824 temp2_fp = drm_fixp_from_fraction( 825 tu->delay_start_link_extra_pixclk, 1); 826 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp); 827 828 if (temp1_fp) 829 tu->extra_buffer_margin = 830 drm_fixp2int_ceil(temp1_fp); 831 else 832 tu->extra_buffer_margin = 0; 833 834 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 835 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 836 837 if (temp1_fp) 838 tu->n_symbols = drm_fixp2int_ceil(temp1_fp); 839 else 840 tu->n_symbols = 0; 841 842 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { 843 for (tu->i_upper_boundary_count = 1; 844 tu->i_upper_boundary_count <= 15; 845 tu->i_upper_boundary_count++) { 846 for (tu->i_lower_boundary_count = 1; 847 tu->i_lower_boundary_count <= 15; 848 tu->i_lower_boundary_count++) { 849 _tu_valid_boundary_calc(tu); 850 } 851 } 852 } 853 tu->delay_start_link_extra_pixclk--; 854 } while (tu->boundary_moderation_en != true && 855 tu->boundary_mod_lower_err == 1 && 856 tu->delay_start_link_extra_pixclk != 0); 857 858 if (tu->boundary_moderation_en == true) { 859 temp1_fp = drm_fixp_from_fraction( 860 (tu->upper_boundary_count * 861 tu->valid_boundary_link + 862 tu->lower_boundary_count * 863 (tu->valid_boundary_link - 1)), 1); 864 temp2_fp = drm_fixp_from_fraction( 865 (tu->upper_boundary_count + 866 tu->lower_boundary_count), 1); 867 tu->resulting_valid_fp = 868 drm_fixp_div(temp1_fp, temp2_fp); 869 870 temp1_fp = drm_fixp_from_fraction( 871 tu->tu_size_desired, 1); 872 tu->ratio_by_tu_fp = 873 drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 874 875 tu->valid_lower_boundary_link = 876 tu->valid_boundary_link - 1; 877 878 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 879 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp); 880 temp2_fp = drm_fixp_div(temp1_fp, 881 tu->resulting_valid_fp); 882 tu->n_tus = drm_fixp2int(temp2_fp); 883 884 tu->tu_size_minus1 = tu->tu_size_desired - 1; 885 tu->even_distribution_BF = 1; 886 887 temp1_fp = 888 drm_fixp_from_fraction(tu->tu_size_desired, 1); 889 temp2_fp = 890 drm_fixp_div(tu->resulting_valid_fp, temp1_fp); 891 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; 892 } 893 } 894 895 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp); 896 897 if (temp2_fp) 898 temp = drm_fixp2int_ceil(temp2_fp); 899 else 900 temp = 0; 901 902 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1); 903 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp); 904 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8); 905 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp); 906 temp1_fp = drm_fixp_from_fraction(temp, 1); 907 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp); 908 temp = drm_fixp2int(temp2_fp); 909 910 if (tu->async_en) 911 tu->delay_start_link += (int)temp; 912 913 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1); 914 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp); 915 916 /* OUTPUTS */ 917 tu_table->valid_boundary_link = tu->valid_boundary_link; 918 tu_table->delay_start_link = tu->delay_start_link; 919 tu_table->boundary_moderation_en = tu->boundary_moderation_en; 920 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; 921 tu_table->upper_boundary_count = tu->upper_boundary_count; 922 tu_table->lower_boundary_count = tu->lower_boundary_count; 923 tu_table->tu_size_minus1 = tu->tu_size_minus1; 924 925 DRM_DEBUG_DP("TU: valid_boundary_link: %d\n", 926 tu_table->valid_boundary_link); 927 DRM_DEBUG_DP("TU: delay_start_link: %d\n", 928 tu_table->delay_start_link); 929 DRM_DEBUG_DP("TU: boundary_moderation_en: %d\n", 930 tu_table->boundary_moderation_en); 931 DRM_DEBUG_DP("TU: valid_lower_boundary_link: %d\n", 932 tu_table->valid_lower_boundary_link); 933 DRM_DEBUG_DP("TU: upper_boundary_count: %d\n", 934 tu_table->upper_boundary_count); 935 DRM_DEBUG_DP("TU: lower_boundary_count: %d\n", 936 tu_table->lower_boundary_count); 937 DRM_DEBUG_DP("TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1); 938 939 kfree(tu); 940 } 941 942 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, 943 struct dp_vc_tu_mapping_table *tu_table) 944 { 945 struct dp_tu_calc_input in; 946 struct drm_display_mode *drm_mode; 947 948 drm_mode = &ctrl->panel->dp_mode.drm_mode; 949 950 in.lclk = ctrl->link->link_params.rate / 1000; 951 in.pclk_khz = drm_mode->clock; 952 in.hactive = drm_mode->hdisplay; 953 in.hporch = drm_mode->htotal - drm_mode->hdisplay; 954 in.nlanes = ctrl->link->link_params.num_lanes; 955 in.bpp = ctrl->panel->dp_mode.bpp; 956 in.pixel_enc = 444; 957 in.dsc_en = 0; 958 in.async_en = 0; 959 in.fec_en = 0; 960 in.num_of_dsc_slices = 0; 961 in.compress_ratio = 100; 962 963 _dp_ctrl_calc_tu(&in, tu_table); 964 } 965 966 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl) 967 { 968 u32 dp_tu = 0x0; 969 u32 valid_boundary = 0x0; 970 u32 valid_boundary2 = 0x0; 971 struct dp_vc_tu_mapping_table tu_calc_table; 972 973 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); 974 975 dp_tu |= tu_calc_table.tu_size_minus1; 976 valid_boundary |= tu_calc_table.valid_boundary_link; 977 valid_boundary |= (tu_calc_table.delay_start_link << 16); 978 979 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); 980 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); 981 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); 982 983 if (tu_calc_table.boundary_moderation_en) 984 valid_boundary2 |= BIT(0); 985 986 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", 987 dp_tu, valid_boundary, valid_boundary2); 988 989 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, 990 dp_tu, valid_boundary, valid_boundary2); 991 } 992 993 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) 994 { 995 int ret = 0; 996 997 if (!wait_for_completion_timeout(&ctrl->video_comp, 998 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { 999 DRM_ERROR("wait4video timedout\n"); 1000 ret = -ETIMEDOUT; 1001 } 1002 return ret; 1003 } 1004 1005 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) 1006 { 1007 struct dp_link *link = ctrl->link; 1008 int ret = 0, lane, lane_cnt; 1009 u8 buf[4]; 1010 u32 max_level_reached = 0; 1011 u32 voltage_swing_level = link->phy_params.v_level; 1012 u32 pre_emphasis_level = link->phy_params.p_level; 1013 1014 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, 1015 voltage_swing_level, pre_emphasis_level); 1016 1017 if (ret) 1018 return ret; 1019 1020 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) { 1021 DRM_DEBUG_DP("max. voltage swing level reached %d\n", 1022 voltage_swing_level); 1023 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; 1024 } 1025 1026 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) { 1027 DRM_DEBUG_DP("max. pre-emphasis level reached %d\n", 1028 pre_emphasis_level); 1029 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1030 } 1031 1032 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; 1033 1034 lane_cnt = ctrl->link->link_params.num_lanes; 1035 for (lane = 0; lane < lane_cnt; lane++) 1036 buf[lane] = voltage_swing_level | pre_emphasis_level 1037 | max_level_reached; 1038 1039 DRM_DEBUG_DP("sink: p|v=0x%x\n", voltage_swing_level 1040 | pre_emphasis_level); 1041 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET, 1042 buf, lane_cnt); 1043 if (ret == lane_cnt) 1044 ret = 0; 1045 1046 return ret; 1047 } 1048 1049 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, 1050 u8 pattern) 1051 { 1052 u8 buf; 1053 int ret = 0; 1054 1055 DRM_DEBUG_DP("sink: pattern=%x\n", pattern); 1056 1057 buf = pattern; 1058 1059 if (pattern && pattern != DP_TRAINING_PATTERN_4) 1060 buf |= DP_LINK_SCRAMBLING_DISABLE; 1061 1062 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf); 1063 return ret == 1; 1064 } 1065 1066 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, 1067 u8 *link_status) 1068 { 1069 int ret = 0, len; 1070 1071 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status); 1072 if (len != DP_LINK_STATUS_SIZE) { 1073 DRM_ERROR("DP link status read failed, err: %d\n", len); 1074 ret = -EINVAL; 1075 } 1076 1077 return ret; 1078 } 1079 1080 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, 1081 struct dp_cr_status *cr, int *training_step) 1082 { 1083 int tries, old_v_level, ret = 0; 1084 u8 link_status[DP_LINK_STATUS_SIZE]; 1085 int const maximum_retries = 4; 1086 1087 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1088 1089 *training_step = DP_TRAINING_1; 1090 1091 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); 1092 if (ret) 1093 return ret; 1094 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1095 DP_LINK_SCRAMBLING_DISABLE); 1096 1097 ret = dp_ctrl_update_vx_px(ctrl); 1098 if (ret) 1099 return ret; 1100 1101 tries = 0; 1102 old_v_level = ctrl->link->phy_params.v_level; 1103 for (tries = 0; tries < maximum_retries; tries++) { 1104 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); 1105 1106 ret = dp_ctrl_read_link_status(ctrl, link_status); 1107 if (ret) 1108 return ret; 1109 1110 cr->lane_0_1 = link_status[0]; 1111 cr->lane_2_3 = link_status[1]; 1112 1113 if (drm_dp_clock_recovery_ok(link_status, 1114 ctrl->link->link_params.num_lanes)) { 1115 return 0; 1116 } 1117 1118 if (ctrl->link->phy_params.v_level >= 1119 DP_TRAIN_VOLTAGE_SWING_MAX) { 1120 DRM_ERROR_RATELIMITED("max v_level reached\n"); 1121 return -EAGAIN; 1122 } 1123 1124 if (old_v_level != ctrl->link->phy_params.v_level) { 1125 tries = 0; 1126 old_v_level = ctrl->link->phy_params.v_level; 1127 } 1128 1129 DRM_DEBUG_DP("clock recovery not done, adjusting vx px\n"); 1130 1131 dp_link_adjust_levels(ctrl->link, link_status); 1132 ret = dp_ctrl_update_vx_px(ctrl); 1133 if (ret) 1134 return ret; 1135 } 1136 1137 DRM_ERROR("max tries reached\n"); 1138 return -ETIMEDOUT; 1139 } 1140 1141 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) 1142 { 1143 int ret = 0; 1144 1145 switch (ctrl->link->link_params.rate) { 1146 case 810000: 1147 ctrl->link->link_params.rate = 540000; 1148 break; 1149 case 540000: 1150 ctrl->link->link_params.rate = 270000; 1151 break; 1152 case 270000: 1153 ctrl->link->link_params.rate = 162000; 1154 break; 1155 case 162000: 1156 default: 1157 ret = -EINVAL; 1158 break; 1159 } 1160 1161 if (!ret) 1162 DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate); 1163 1164 return ret; 1165 } 1166 1167 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) 1168 { 1169 1170 if (ctrl->link->link_params.num_lanes == 1) 1171 return -1; 1172 1173 ctrl->link->link_params.num_lanes /= 2; 1174 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; 1175 1176 ctrl->link->phy_params.p_level = 0; 1177 ctrl->link->phy_params.v_level = 0; 1178 1179 return 0; 1180 } 1181 1182 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) 1183 { 1184 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); 1185 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1186 } 1187 1188 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 1189 struct dp_cr_status *cr, int *training_step) 1190 { 1191 int tries = 0, ret = 0; 1192 char pattern; 1193 int const maximum_retries = 5; 1194 u8 link_status[DP_LINK_STATUS_SIZE]; 1195 1196 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1197 1198 *training_step = DP_TRAINING_2; 1199 1200 if (drm_dp_tps3_supported(ctrl->panel->dpcd)) 1201 pattern = DP_TRAINING_PATTERN_3; 1202 else 1203 pattern = DP_TRAINING_PATTERN_2; 1204 1205 ret = dp_ctrl_update_vx_px(ctrl); 1206 if (ret) 1207 return ret; 1208 1209 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); 1210 if (ret) 1211 return ret; 1212 1213 dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); 1214 1215 for (tries = 0; tries <= maximum_retries; tries++) { 1216 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1217 1218 ret = dp_ctrl_read_link_status(ctrl, link_status); 1219 if (ret) 1220 return ret; 1221 cr->lane_0_1 = link_status[0]; 1222 cr->lane_2_3 = link_status[1]; 1223 1224 if (drm_dp_channel_eq_ok(link_status, 1225 ctrl->link->link_params.num_lanes)) { 1226 return 0; 1227 } 1228 1229 dp_link_adjust_levels(ctrl->link, link_status); 1230 ret = dp_ctrl_update_vx_px(ctrl); 1231 if (ret) 1232 return ret; 1233 1234 } 1235 1236 return -ETIMEDOUT; 1237 } 1238 1239 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl); 1240 1241 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 1242 struct dp_cr_status *cr, int *training_step) 1243 { 1244 int ret = 0; 1245 u8 encoding = DP_SET_ANSI_8B10B; 1246 struct dp_link_info link_info = {0}; 1247 1248 dp_ctrl_config_ctrl(ctrl); 1249 1250 link_info.num_lanes = ctrl->link->link_params.num_lanes; 1251 link_info.rate = ctrl->link->link_params.rate; 1252 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; 1253 1254 dp_aux_link_configure(ctrl->aux, &link_info); 1255 drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, 1256 &encoding, 1); 1257 1258 ret = dp_ctrl_link_train_1(ctrl, cr, training_step); 1259 if (ret) { 1260 DRM_ERROR("link training #1 failed. ret=%d\n", ret); 1261 goto end; 1262 } 1263 1264 /* print success info as this is a result of user initiated action */ 1265 DRM_DEBUG_DP("link training #1 successful\n"); 1266 1267 ret = dp_ctrl_link_train_2(ctrl, cr, training_step); 1268 if (ret) { 1269 DRM_ERROR("link training #2 failed. ret=%d\n", ret); 1270 goto end; 1271 } 1272 1273 /* print success info as this is a result of user initiated action */ 1274 DRM_DEBUG_DP("link training #2 successful\n"); 1275 1276 end: 1277 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1278 1279 return ret; 1280 } 1281 1282 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, 1283 struct dp_cr_status *cr, int *training_step) 1284 { 1285 int ret = 0; 1286 1287 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 1288 1289 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1290 return ret; 1291 1292 /* 1293 * As part of previous calls, DP controller state might have 1294 * transitioned to PUSH_IDLE. In order to start transmitting 1295 * a link training pattern, we have to first do soft reset. 1296 */ 1297 1298 ret = dp_ctrl_link_train(ctrl, cr, training_step); 1299 1300 return ret; 1301 } 1302 1303 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, 1304 enum dp_pm_type module, char *name, unsigned long rate) 1305 { 1306 u32 num = ctrl->parser->mp[module].num_clk; 1307 struct dss_clk *cfg = ctrl->parser->mp[module].clk_config; 1308 1309 while (num && strcmp(cfg->clk_name, name)) { 1310 num--; 1311 cfg++; 1312 } 1313 1314 DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name); 1315 1316 if (num) 1317 cfg->rate = rate; 1318 else 1319 DRM_ERROR("%s clock doesn't exit to set rate %lu\n", 1320 name, rate); 1321 } 1322 1323 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) 1324 { 1325 int ret = 0; 1326 struct dp_io *dp_io = &ctrl->parser->io; 1327 struct phy *phy = dp_io->phy; 1328 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; 1329 1330 opts_dp->lanes = ctrl->link->link_params.num_lanes; 1331 opts_dp->link_rate = ctrl->link->link_params.rate / 100; 1332 dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", 1333 ctrl->link->link_params.rate * 1000); 1334 1335 phy_configure(phy, &dp_io->phy_opts); 1336 phy_power_on(phy); 1337 1338 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); 1339 if (ret) 1340 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); 1341 1342 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n", 1343 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); 1344 1345 return ret; 1346 } 1347 1348 static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl) 1349 { 1350 int ret = 0; 1351 1352 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", 1353 ctrl->dp_ctrl.pixel_rate * 1000); 1354 1355 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); 1356 if (ret) 1357 DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret); 1358 1359 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n", 1360 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate); 1361 1362 return ret; 1363 } 1364 1365 int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset) 1366 { 1367 struct dp_ctrl_private *ctrl; 1368 struct dp_io *dp_io; 1369 struct phy *phy; 1370 1371 if (!dp_ctrl) { 1372 DRM_ERROR("Invalid input data\n"); 1373 return -EINVAL; 1374 } 1375 1376 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1377 dp_io = &ctrl->parser->io; 1378 phy = dp_io->phy; 1379 1380 ctrl->dp_ctrl.orientation = flip; 1381 1382 if (reset) 1383 dp_catalog_ctrl_reset(ctrl->catalog); 1384 1385 dp_catalog_ctrl_phy_reset(ctrl->catalog); 1386 phy_init(phy); 1387 dp_catalog_ctrl_enable_irq(ctrl->catalog, true); 1388 1389 return 0; 1390 } 1391 1392 /** 1393 * dp_ctrl_host_deinit() - Uninitialize DP controller 1394 * @dp_ctrl: Display Port Driver data 1395 * 1396 * Perform required steps to uninitialize DP controller 1397 * and its resources. 1398 */ 1399 void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl) 1400 { 1401 struct dp_ctrl_private *ctrl; 1402 struct dp_io *dp_io; 1403 struct phy *phy; 1404 1405 if (!dp_ctrl) { 1406 DRM_ERROR("Invalid input data\n"); 1407 return; 1408 } 1409 1410 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1411 dp_io = &ctrl->parser->io; 1412 phy = dp_io->phy; 1413 1414 dp_catalog_ctrl_enable_irq(ctrl->catalog, false); 1415 phy_exit(phy); 1416 1417 DRM_DEBUG_DP("Host deinitialized successfully\n"); 1418 } 1419 1420 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) 1421 { 1422 u8 *dpcd = ctrl->panel->dpcd; 1423 1424 /* 1425 * For better interop experience, used a fixed NVID=0x8000 1426 * whenever connected to a VGA dongle downstream. 1427 */ 1428 if (drm_dp_is_branch(dpcd)) 1429 return (drm_dp_has_quirk(&ctrl->panel->desc, 1430 DP_DPCD_QUIRK_CONSTANT_N)); 1431 1432 return false; 1433 } 1434 1435 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) 1436 { 1437 int ret = 0; 1438 struct dp_io *dp_io = &ctrl->parser->io; 1439 struct phy *phy = dp_io->phy; 1440 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; 1441 1442 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1443 opts_dp->lanes = ctrl->link->link_params.num_lanes; 1444 phy_configure(phy, &dp_io->phy_opts); 1445 /* 1446 * Disable and re-enable the mainlink clock since the 1447 * link clock might have been adjusted as part of the 1448 * link maintenance. 1449 */ 1450 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1451 if (ret) { 1452 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); 1453 return ret; 1454 } 1455 phy_power_off(phy); 1456 /* hw recommended delay before re-enabling clocks */ 1457 msleep(20); 1458 1459 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1460 if (ret) { 1461 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); 1462 return ret; 1463 } 1464 1465 return ret; 1466 } 1467 1468 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) 1469 { 1470 struct dp_io *dp_io; 1471 struct phy *phy; 1472 int ret; 1473 1474 dp_io = &ctrl->parser->io; 1475 phy = dp_io->phy; 1476 1477 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1478 1479 dp_catalog_ctrl_reset(ctrl->catalog); 1480 1481 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1482 if (ret) { 1483 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1484 } 1485 1486 phy_power_off(phy); 1487 phy_exit(phy); 1488 1489 return 0; 1490 } 1491 1492 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) 1493 { 1494 int ret = 0; 1495 struct dp_cr_status cr; 1496 int training_step = DP_TRAINING_NONE; 1497 1498 dp_ctrl_push_idle(&ctrl->dp_ctrl); 1499 1500 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1501 1502 ret = dp_ctrl_setup_main_link(ctrl, &cr, &training_step); 1503 if (ret) 1504 goto end; 1505 1506 dp_ctrl_clear_training_pattern(ctrl); 1507 1508 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1509 1510 ret = dp_ctrl_wait4video_ready(ctrl); 1511 end: 1512 return ret; 1513 } 1514 1515 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) 1516 { 1517 int ret = 0; 1518 1519 if (!ctrl->link->phy_params.phy_test_pattern_sel) { 1520 DRM_DEBUG_DP("no test pattern selected by sink\n"); 1521 return ret; 1522 } 1523 1524 /* 1525 * The global reset will need DP link related clocks to be 1526 * running. Add the global reset just before disabling the 1527 * link clocks and core clocks. 1528 */ 1529 ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl); 1530 if (ret) { 1531 DRM_ERROR("failed to disable DP controller\n"); 1532 return ret; 1533 } 1534 1535 ret = dp_ctrl_on_link(&ctrl->dp_ctrl); 1536 if (!ret) 1537 ret = dp_ctrl_on_stream(&ctrl->dp_ctrl); 1538 else 1539 DRM_ERROR("failed to enable DP link controller\n"); 1540 1541 return ret; 1542 } 1543 1544 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) 1545 { 1546 bool success = false; 1547 u32 pattern_sent = 0x0; 1548 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; 1549 1550 DRM_DEBUG_DP("request: 0x%x\n", pattern_requested); 1551 1552 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog, 1553 ctrl->link->phy_params.v_level, 1554 ctrl->link->phy_params.p_level)) { 1555 DRM_ERROR("Failed to set v/p levels\n"); 1556 return false; 1557 } 1558 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); 1559 dp_ctrl_update_vx_px(ctrl); 1560 dp_link_send_test_response(ctrl->link); 1561 1562 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); 1563 1564 switch (pattern_sent) { 1565 case MR_LINK_TRAINING1: 1566 success = (pattern_requested == 1567 DP_PHY_TEST_PATTERN_D10_2); 1568 break; 1569 case MR_LINK_SYMBOL_ERM: 1570 success = ((pattern_requested == 1571 DP_PHY_TEST_PATTERN_ERROR_COUNT) || 1572 (pattern_requested == 1573 DP_PHY_TEST_PATTERN_CP2520)); 1574 break; 1575 case MR_LINK_PRBS7: 1576 success = (pattern_requested == 1577 DP_PHY_TEST_PATTERN_PRBS7); 1578 break; 1579 case MR_LINK_CUSTOM80: 1580 success = (pattern_requested == 1581 DP_PHY_TEST_PATTERN_80BIT_CUSTOM); 1582 break; 1583 case MR_LINK_TRAINING4: 1584 success = (pattern_requested == 1585 DP_PHY_TEST_PATTERN_SEL_MASK); 1586 break; 1587 default: 1588 success = false; 1589 } 1590 1591 DRM_DEBUG_DP("%s: test->0x%x\n", success ? "success" : "failed", 1592 pattern_requested); 1593 return success; 1594 } 1595 1596 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) 1597 { 1598 struct dp_ctrl_private *ctrl; 1599 u32 sink_request = 0x0; 1600 1601 if (!dp_ctrl) { 1602 DRM_ERROR("invalid input\n"); 1603 return; 1604 } 1605 1606 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1607 sink_request = ctrl->link->sink_request; 1608 1609 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1610 DRM_DEBUG_DP("PHY_TEST_PATTERN request\n"); 1611 if (dp_ctrl_process_phy_test_request(ctrl)) { 1612 DRM_ERROR("process phy_test_req failed\n"); 1613 return; 1614 } 1615 } 1616 1617 if (sink_request & DP_LINK_STATUS_UPDATED) { 1618 if (dp_ctrl_link_maintenance(ctrl)) { 1619 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1620 return; 1621 } 1622 } 1623 1624 if (sink_request & DP_TEST_LINK_TRAINING) { 1625 dp_link_send_test_response(ctrl->link); 1626 if (dp_ctrl_link_maintenance(ctrl)) { 1627 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1628 return; 1629 } 1630 } 1631 } 1632 1633 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 1634 { 1635 int rc = 0; 1636 struct dp_ctrl_private *ctrl; 1637 u32 rate = 0; 1638 int link_train_max_retries = 5; 1639 u32 const phy_cts_pixel_clk_khz = 148500; 1640 struct dp_cr_status cr; 1641 unsigned int training_step; 1642 1643 if (!dp_ctrl) 1644 return -EINVAL; 1645 1646 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1647 1648 rate = ctrl->panel->link_info.rate; 1649 1650 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); 1651 1652 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1653 DRM_DEBUG_DP("using phy test link parameters\n"); 1654 if (!ctrl->panel->dp_mode.drm_mode.clock) 1655 ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz; 1656 } else { 1657 ctrl->link->link_params.rate = rate; 1658 ctrl->link->link_params.num_lanes = 1659 ctrl->panel->link_info.num_lanes; 1660 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1661 } 1662 1663 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", 1664 ctrl->link->link_params.rate, 1665 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); 1666 1667 rc = dp_ctrl_enable_mainlink_clocks(ctrl); 1668 if (rc) 1669 return rc; 1670 1671 while (--link_train_max_retries) { 1672 rc = dp_ctrl_reinitialize_mainlink(ctrl); 1673 if (rc) { 1674 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", 1675 rc); 1676 break; 1677 } 1678 1679 training_step = DP_TRAINING_NONE; 1680 rc = dp_ctrl_setup_main_link(ctrl, &cr, &training_step); 1681 if (rc == 0) { 1682 /* training completed successfully */ 1683 break; 1684 } else if (training_step == DP_TRAINING_1) { 1685 /* link train_1 failed */ 1686 if (!dp_catalog_link_is_connected(ctrl->catalog)) { 1687 break; 1688 } 1689 1690 rc = dp_ctrl_link_rate_down_shift(ctrl); 1691 if (rc < 0) { /* already in RBR = 1.6G */ 1692 if (cr.lane_0_1 & DP_LANE0_1_CR_DONE) { 1693 /* 1694 * some lanes are ready, 1695 * reduce lane number 1696 */ 1697 rc = dp_ctrl_link_lane_down_shift(ctrl); 1698 if (rc < 0) { /* lane == 1 already */ 1699 /* end with failure */ 1700 break; 1701 } 1702 } else { 1703 /* end with failure */ 1704 break; /* lane == 1 already */ 1705 } 1706 } 1707 } else if (training_step == DP_TRAINING_2) { 1708 /* link train_2 failed, lower lane rate */ 1709 if (!dp_catalog_link_is_connected(ctrl->catalog)) { 1710 break; 1711 } 1712 1713 rc = dp_ctrl_link_lane_down_shift(ctrl); 1714 if (rc < 0) { 1715 /* end with failure */ 1716 break; /* lane == 1 already */ 1717 } 1718 } 1719 } 1720 1721 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1722 return rc; 1723 1724 /* stop txing train pattern */ 1725 dp_ctrl_clear_training_pattern(ctrl); 1726 1727 /* 1728 * keep transmitting idle pattern until video ready 1729 * to avoid main link from loss of sync 1730 */ 1731 if (rc == 0) /* link train successfully */ 1732 dp_ctrl_push_idle(dp_ctrl); 1733 else { 1734 /* link training failed */ 1735 dp_ctrl_deinitialize_mainlink(ctrl); 1736 rc = -ECONNRESET; 1737 } 1738 1739 return rc; 1740 } 1741 1742 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) 1743 { 1744 u32 rate = 0; 1745 int ret = 0; 1746 bool mainlink_ready = false; 1747 struct dp_ctrl_private *ctrl; 1748 1749 if (!dp_ctrl) 1750 return -EINVAL; 1751 1752 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1753 1754 rate = ctrl->panel->link_info.rate; 1755 1756 ctrl->link->link_params.rate = rate; 1757 ctrl->link->link_params.num_lanes = ctrl->panel->link_info.num_lanes; 1758 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1759 1760 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n", 1761 ctrl->link->link_params.rate, 1762 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate); 1763 1764 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */ 1765 ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1766 if (ret) { 1767 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); 1768 goto end; 1769 } 1770 } 1771 1772 ret = dp_ctrl_enable_stream_clocks(ctrl); 1773 if (ret) { 1774 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); 1775 goto end; 1776 } 1777 1778 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1779 dp_ctrl_send_phy_test_pattern(ctrl); 1780 return 0; 1781 } 1782 1783 /* 1784 * Set up transfer unit values and set controller state to send 1785 * video. 1786 */ 1787 reinit_completion(&ctrl->video_comp); 1788 1789 dp_ctrl_configure_source_params(ctrl); 1790 1791 dp_catalog_ctrl_config_msa(ctrl->catalog, 1792 ctrl->link->link_params.rate, 1793 ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl)); 1794 1795 dp_ctrl_setup_tr_unit(ctrl); 1796 1797 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1798 1799 ret = dp_ctrl_wait4video_ready(ctrl); 1800 if (ret) 1801 return ret; 1802 1803 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); 1804 DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); 1805 1806 end: 1807 return ret; 1808 } 1809 1810 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) 1811 { 1812 struct dp_ctrl_private *ctrl; 1813 struct dp_io *dp_io; 1814 struct phy *phy; 1815 int ret; 1816 1817 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1818 dp_io = &ctrl->parser->io; 1819 phy = dp_io->phy; 1820 1821 /* set dongle to D3 (power off) mode */ 1822 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); 1823 1824 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1825 1826 if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) { 1827 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); 1828 if (ret) { 1829 DRM_ERROR("Failed to disable pclk. ret=%d\n", ret); 1830 return ret; 1831 } 1832 } 1833 1834 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1835 if (ret) { 1836 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1837 return ret; 1838 } 1839 1840 phy_power_off(phy); 1841 1842 /* aux channel down, reinit phy */ 1843 phy_exit(phy); 1844 phy_init(phy); 1845 1846 DRM_DEBUG_DP("DP off link/stream done\n"); 1847 return ret; 1848 } 1849 1850 void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl) 1851 { 1852 struct dp_ctrl_private *ctrl; 1853 struct dp_io *dp_io; 1854 struct phy *phy; 1855 1856 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1857 dp_io = &ctrl->parser->io; 1858 phy = dp_io->phy; 1859 1860 dp_catalog_ctrl_reset(ctrl->catalog); 1861 1862 phy_exit(phy); 1863 1864 DRM_DEBUG_DP("DP off phy done\n"); 1865 } 1866 1867 int dp_ctrl_off(struct dp_ctrl *dp_ctrl) 1868 { 1869 struct dp_ctrl_private *ctrl; 1870 struct dp_io *dp_io; 1871 struct phy *phy; 1872 int ret = 0; 1873 1874 if (!dp_ctrl) 1875 return -EINVAL; 1876 1877 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1878 dp_io = &ctrl->parser->io; 1879 phy = dp_io->phy; 1880 1881 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1882 1883 dp_catalog_ctrl_reset(ctrl->catalog); 1884 1885 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); 1886 if (ret) 1887 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); 1888 1889 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); 1890 if (ret) { 1891 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); 1892 } 1893 1894 phy_power_off(phy); 1895 phy_exit(phy); 1896 1897 DRM_DEBUG_DP("DP off done\n"); 1898 return ret; 1899 } 1900 1901 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl) 1902 { 1903 struct dp_ctrl_private *ctrl; 1904 u32 isr; 1905 1906 if (!dp_ctrl) 1907 return; 1908 1909 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1910 1911 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog); 1912 1913 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { 1914 DRM_DEBUG_DP("dp_video_ready\n"); 1915 complete(&ctrl->video_comp); 1916 } 1917 1918 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { 1919 DRM_DEBUG_DP("idle_patterns_sent\n"); 1920 complete(&ctrl->idle_comp); 1921 } 1922 } 1923 1924 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, 1925 struct dp_panel *panel, struct drm_dp_aux *aux, 1926 struct dp_power *power, struct dp_catalog *catalog, 1927 struct dp_parser *parser) 1928 { 1929 struct dp_ctrl_private *ctrl; 1930 int ret; 1931 1932 if (!dev || !panel || !aux || 1933 !link || !catalog) { 1934 DRM_ERROR("invalid input\n"); 1935 return ERR_PTR(-EINVAL); 1936 } 1937 1938 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1939 if (!ctrl) { 1940 DRM_ERROR("Mem allocation failure\n"); 1941 return ERR_PTR(-ENOMEM); 1942 } 1943 1944 ret = devm_pm_opp_set_clkname(dev, "ctrl_link"); 1945 if (ret) { 1946 dev_err(dev, "invalid DP OPP table in device tree\n"); 1947 /* caller do PTR_ERR(opp_table) */ 1948 return (struct dp_ctrl *)ERR_PTR(ret); 1949 } 1950 1951 /* OPP table is optional */ 1952 ret = devm_pm_opp_of_add_table(dev); 1953 if (ret) 1954 dev_err(dev, "failed to add DP OPP table\n"); 1955 1956 init_completion(&ctrl->idle_comp); 1957 init_completion(&ctrl->video_comp); 1958 1959 /* in parameters */ 1960 ctrl->parser = parser; 1961 ctrl->panel = panel; 1962 ctrl->power = power; 1963 ctrl->aux = aux; 1964 ctrl->link = link; 1965 ctrl->catalog = catalog; 1966 ctrl->dev = dev; 1967 1968 return &ctrl->dp_ctrl; 1969 } 1970