xref: /openbmc/linux/drivers/gpu/drm/msm/dp/dp_aux.c (revision 2ae1beb3) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/delay.h>
7 #include <drm/drm_print.h>
8 
9 #include "dp_reg.h"
10 #include "dp_aux.h"
11 
12 enum msm_dp_aux_err {
13 	DP_AUX_ERR_NONE,
14 	DP_AUX_ERR_ADDR,
15 	DP_AUX_ERR_TOUT,
16 	DP_AUX_ERR_NACK,
17 	DP_AUX_ERR_DEFER,
18 	DP_AUX_ERR_NACK_DEFER,
19 	DP_AUX_ERR_PHY,
20 };
21 
22 struct dp_aux_private {
23 	struct device *dev;
24 	struct dp_catalog *catalog;
25 
26 	struct mutex mutex;
27 	struct completion comp;
28 
29 	enum msm_dp_aux_err aux_error_num;
30 	u32 retry_cnt;
31 	bool cmd_busy;
32 	bool native;
33 	bool read;
34 	bool no_send_addr;
35 	bool no_send_stop;
36 	bool initted;
37 	bool is_edp;
38 	bool enable_xfers;
39 	u32 offset;
40 	u32 segment;
41 
42 	struct drm_dp_aux dp_aux;
43 };
44 
45 #define MAX_AUX_RETRIES			5
46 
47 static ssize_t dp_aux_write(struct dp_aux_private *aux,
48 			struct drm_dp_aux_msg *msg)
49 {
50 	u8 data[4];
51 	u32 reg;
52 	ssize_t len;
53 	u8 *msgdata = msg->buffer;
54 	int const AUX_CMD_FIFO_LEN = 128;
55 	int i = 0;
56 
57 	if (aux->read)
58 		len = 0;
59 	else
60 		len = msg->size;
61 
62 	/*
63 	 * cmd fifo only has depth of 144 bytes
64 	 * limit buf length to 128 bytes here
65 	 */
66 	if (len > AUX_CMD_FIFO_LEN - 4) {
67 		DRM_ERROR("buf size greater than allowed size of 128 bytes\n");
68 		return -EINVAL;
69 	}
70 
71 	/* Pack cmd and write to HW */
72 	data[0] = (msg->address >> 16) & 0xf;	/* addr[19:16] */
73 	if (aux->read)
74 		data[0] |=  BIT(4);		/* R/W */
75 
76 	data[1] = msg->address >> 8;		/* addr[15:8] */
77 	data[2] = msg->address;			/* addr[7:0] */
78 	data[3] = msg->size - 1;		/* len[7:0] */
79 
80 	for (i = 0; i < len + 4; i++) {
81 		reg = (i < 4) ? data[i] : msgdata[i - 4];
82 		reg <<= DP_AUX_DATA_OFFSET;
83 		reg &= DP_AUX_DATA_MASK;
84 		reg |= DP_AUX_DATA_WRITE;
85 		/* index = 0, write */
86 		if (i == 0)
87 			reg |= DP_AUX_DATA_INDEX_WRITE;
88 		aux->catalog->aux_data = reg;
89 		dp_catalog_aux_write_data(aux->catalog);
90 	}
91 
92 	dp_catalog_aux_clear_trans(aux->catalog, false);
93 	dp_catalog_aux_clear_hw_interrupts(aux->catalog);
94 
95 	reg = 0; /* Transaction number == 1 */
96 	if (!aux->native) { /* i2c */
97 		reg |= DP_AUX_TRANS_CTRL_I2C;
98 
99 		if (aux->no_send_addr)
100 			reg |= DP_AUX_TRANS_CTRL_NO_SEND_ADDR;
101 
102 		if (aux->no_send_stop)
103 			reg |= DP_AUX_TRANS_CTRL_NO_SEND_STOP;
104 	}
105 
106 	reg |= DP_AUX_TRANS_CTRL_GO;
107 	aux->catalog->aux_data = reg;
108 	dp_catalog_aux_write_trans(aux->catalog);
109 
110 	return len;
111 }
112 
113 static ssize_t dp_aux_cmd_fifo_tx(struct dp_aux_private *aux,
114 			      struct drm_dp_aux_msg *msg)
115 {
116 	ssize_t ret;
117 	unsigned long time_left;
118 
119 	reinit_completion(&aux->comp);
120 
121 	ret = dp_aux_write(aux, msg);
122 	if (ret < 0)
123 		return ret;
124 
125 	time_left = wait_for_completion_timeout(&aux->comp,
126 						msecs_to_jiffies(250));
127 	if (!time_left)
128 		return -ETIMEDOUT;
129 
130 	return ret;
131 }
132 
133 static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
134 		struct drm_dp_aux_msg *msg)
135 {
136 	u32 data;
137 	u8 *dp;
138 	u32 i, actual_i;
139 	u32 len = msg->size;
140 
141 	dp_catalog_aux_clear_trans(aux->catalog, true);
142 
143 	data = DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */
144 	data |= DP_AUX_DATA_READ;  /* read */
145 
146 	aux->catalog->aux_data = data;
147 	dp_catalog_aux_write_data(aux->catalog);
148 
149 	dp = msg->buffer;
150 
151 	/* discard first byte */
152 	data = dp_catalog_aux_read_data(aux->catalog);
153 
154 	for (i = 0; i < len; i++) {
155 		data = dp_catalog_aux_read_data(aux->catalog);
156 		*dp++ = (u8)((data >> DP_AUX_DATA_OFFSET) & 0xff);
157 
158 		actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF;
159 		if (i != actual_i)
160 			break;
161 	}
162 
163 	return i;
164 }
165 
166 static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux,
167 					     struct drm_dp_aux_msg *input_msg)
168 {
169 	u32 edid_address = 0x50;
170 	u32 segment_address = 0x30;
171 	bool i2c_read = input_msg->request &
172 		(DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
173 	u8 *data;
174 
175 	if (aux->native || i2c_read || ((input_msg->address != edid_address) &&
176 		(input_msg->address != segment_address)))
177 		return;
178 
179 
180 	data = input_msg->buffer;
181 	if (input_msg->address == segment_address)
182 		aux->segment = *data;
183 	else
184 		aux->offset = *data;
185 }
186 
187 /**
188  * dp_aux_transfer_helper() - helper function for EDID read transactions
189  *
190  * @aux: DP AUX private structure
191  * @input_msg: input message from DRM upstream APIs
192  * @send_seg: send the segment to sink
193  *
194  * return: void
195  *
196  * This helper function is used to fix EDID reads for non-compliant
197  * sinks that do not handle the i2c middle-of-transaction flag correctly.
198  */
199 static void dp_aux_transfer_helper(struct dp_aux_private *aux,
200 				   struct drm_dp_aux_msg *input_msg,
201 				   bool send_seg)
202 {
203 	struct drm_dp_aux_msg helper_msg;
204 	u32 message_size = 0x10;
205 	u32 segment_address = 0x30;
206 	u32 const edid_block_length = 0x80;
207 	bool i2c_mot = input_msg->request & DP_AUX_I2C_MOT;
208 	bool i2c_read = input_msg->request &
209 		(DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
210 
211 	if (!i2c_mot || !i2c_read || (input_msg->size == 0))
212 		return;
213 
214 	/*
215 	 * Sending the segment value and EDID offset will be performed
216 	 * from the DRM upstream EDID driver for each block. Avoid
217 	 * duplicate AUX transactions related to this while reading the
218 	 * first 16 bytes of each block.
219 	 */
220 	if (!(aux->offset % edid_block_length) || !send_seg)
221 		goto end;
222 
223 	aux->read = false;
224 	aux->cmd_busy = true;
225 	aux->no_send_addr = true;
226 	aux->no_send_stop = true;
227 
228 	/*
229 	 * Send the segment address for every i2c read in which the
230 	 * middle-of-tranaction flag is set. This is required to support EDID
231 	 * reads of more than 2 blocks as the segment address is reset to 0
232 	 * since we are overriding the middle-of-transaction flag for read
233 	 * transactions.
234 	 */
235 
236 	if (aux->segment) {
237 		memset(&helper_msg, 0, sizeof(helper_msg));
238 		helper_msg.address = segment_address;
239 		helper_msg.buffer = &aux->segment;
240 		helper_msg.size = 1;
241 		dp_aux_cmd_fifo_tx(aux, &helper_msg);
242 	}
243 
244 	/*
245 	 * Send the offset address for every i2c read in which the
246 	 * middle-of-transaction flag is set. This will ensure that the sink
247 	 * will update its read pointer and return the correct portion of the
248 	 * EDID buffer in the subsequent i2c read trasntion triggered in the
249 	 * native AUX transfer function.
250 	 */
251 	memset(&helper_msg, 0, sizeof(helper_msg));
252 	helper_msg.address = input_msg->address;
253 	helper_msg.buffer = &aux->offset;
254 	helper_msg.size = 1;
255 	dp_aux_cmd_fifo_tx(aux, &helper_msg);
256 
257 end:
258 	aux->offset += message_size;
259 	if (aux->offset == 0x80 || aux->offset == 0x100)
260 		aux->segment = 0x0; /* reset segment at end of block */
261 }
262 
263 /*
264  * This function does the real job to process an AUX transaction.
265  * It will call aux_reset() function to reset the AUX channel,
266  * if the waiting is timeout.
267  */
268 static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux,
269 			       struct drm_dp_aux_msg *msg)
270 {
271 	ssize_t ret;
272 	int const aux_cmd_native_max = 16;
273 	int const aux_cmd_i2c_max = 128;
274 	struct dp_aux_private *aux;
275 
276 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
277 
278 	aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ);
279 
280 	/* Ignore address only message */
281 	if (msg->size == 0 || !msg->buffer) {
282 		msg->reply = aux->native ?
283 			DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
284 		return msg->size;
285 	}
286 
287 	/* msg sanity check */
288 	if ((aux->native && msg->size > aux_cmd_native_max) ||
289 	    msg->size > aux_cmd_i2c_max) {
290 		DRM_ERROR("%s: invalid msg: size(%zu), request(%x)\n",
291 			__func__, msg->size, msg->request);
292 		return -EINVAL;
293 	}
294 
295 	mutex_lock(&aux->mutex);
296 	if (!aux->initted) {
297 		ret = -EIO;
298 		goto exit;
299 	}
300 
301 	/*
302 	 * If we're using DP and an external display isn't connected then the
303 	 * transfer won't succeed. Return right away. If we don't do this we
304 	 * can end up with long timeouts if someone tries to access the DP AUX
305 	 * character device when no DP device is connected.
306 	 */
307 	if (!aux->is_edp && !aux->enable_xfers) {
308 		ret = -ENXIO;
309 		goto exit;
310 	}
311 
312 	/*
313 	 * For eDP it's important to give a reasonably long wait here for HPD
314 	 * to be asserted. This is because the panel driver may have _just_
315 	 * turned on the panel and then tried to do an AUX transfer. The panel
316 	 * driver has no way of knowing when the panel is ready, so it's up
317 	 * to us to wait. For DP we never get into this situation so let's
318 	 * avoid ever doing the extra long wait for DP.
319 	 */
320 	if (aux->is_edp) {
321 		ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog);
322 		if (ret) {
323 			DRM_DEBUG_DP("Panel not ready for aux transactions\n");
324 			goto exit;
325 		}
326 	}
327 
328 	dp_aux_update_offset_and_segment(aux, msg);
329 	dp_aux_transfer_helper(aux, msg, true);
330 
331 	aux->read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ);
332 	aux->cmd_busy = true;
333 
334 	if (aux->read) {
335 		aux->no_send_addr = true;
336 		aux->no_send_stop = false;
337 	} else {
338 		aux->no_send_addr = true;
339 		aux->no_send_stop = true;
340 	}
341 
342 	ret = dp_aux_cmd_fifo_tx(aux, msg);
343 	if (ret < 0) {
344 		if (aux->native) {
345 			aux->retry_cnt++;
346 			if (!(aux->retry_cnt % MAX_AUX_RETRIES))
347 				dp_catalog_aux_update_cfg(aux->catalog);
348 		}
349 		/* reset aux if link is in connected state */
350 		if (dp_catalog_link_is_connected(aux->catalog))
351 			dp_catalog_aux_reset(aux->catalog);
352 	} else {
353 		aux->retry_cnt = 0;
354 		switch (aux->aux_error_num) {
355 		case DP_AUX_ERR_NONE:
356 			if (aux->read)
357 				ret = dp_aux_cmd_fifo_rx(aux, msg);
358 			msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
359 			break;
360 		case DP_AUX_ERR_DEFER:
361 			msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER;
362 			break;
363 		case DP_AUX_ERR_PHY:
364 		case DP_AUX_ERR_ADDR:
365 		case DP_AUX_ERR_NACK:
366 		case DP_AUX_ERR_NACK_DEFER:
367 			msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_NACK : DP_AUX_I2C_REPLY_NACK;
368 			break;
369 		case DP_AUX_ERR_TOUT:
370 			ret = -ETIMEDOUT;
371 			break;
372 		}
373 	}
374 
375 	aux->cmd_busy = false;
376 
377 exit:
378 	mutex_unlock(&aux->mutex);
379 
380 	return ret;
381 }
382 
383 irqreturn_t dp_aux_isr(struct drm_dp_aux *dp_aux)
384 {
385 	u32 isr;
386 	struct dp_aux_private *aux;
387 
388 	if (!dp_aux) {
389 		DRM_ERROR("invalid input\n");
390 		return IRQ_NONE;
391 	}
392 
393 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
394 
395 	isr = dp_catalog_aux_get_irq(aux->catalog);
396 
397 	/* no interrupts pending, return immediately */
398 	if (!isr)
399 		return IRQ_NONE;
400 
401 	if (!aux->cmd_busy) {
402 		DRM_ERROR("Unexpected DP AUX IRQ %#010x when not busy\n", isr);
403 		return IRQ_NONE;
404 	}
405 
406 	/*
407 	 * The logic below assumes only one error bit is set (other than "done"
408 	 * which can apparently be set at the same time as some of the other
409 	 * bits). Warn if more than one get set so we know we need to improve
410 	 * the logic.
411 	 */
412 	if (hweight32(isr & ~DP_INTR_AUX_XFER_DONE) > 1)
413 		DRM_WARN("Some DP AUX interrupts unhandled: %#010x\n", isr);
414 
415 	if (isr & DP_INTR_AUX_ERROR) {
416 		aux->aux_error_num = DP_AUX_ERR_PHY;
417 		dp_catalog_aux_clear_hw_interrupts(aux->catalog);
418 	} else if (isr & DP_INTR_NACK_DEFER) {
419 		aux->aux_error_num = DP_AUX_ERR_NACK_DEFER;
420 	} else if (isr & DP_INTR_WRONG_ADDR) {
421 		aux->aux_error_num = DP_AUX_ERR_ADDR;
422 	} else if (isr & DP_INTR_TIMEOUT) {
423 		aux->aux_error_num = DP_AUX_ERR_TOUT;
424 	} else if (!aux->native && (isr & DP_INTR_I2C_NACK)) {
425 		aux->aux_error_num = DP_AUX_ERR_NACK;
426 	} else if (!aux->native && (isr & DP_INTR_I2C_DEFER)) {
427 		if (isr & DP_INTR_AUX_XFER_DONE)
428 			aux->aux_error_num = DP_AUX_ERR_NACK;
429 		else
430 			aux->aux_error_num = DP_AUX_ERR_DEFER;
431 	} else if (isr & DP_INTR_AUX_XFER_DONE) {
432 		aux->aux_error_num = DP_AUX_ERR_NONE;
433 	} else {
434 		DRM_WARN("Unexpected interrupt: %#010x\n", isr);
435 		return IRQ_NONE;
436 	}
437 
438 	complete(&aux->comp);
439 
440 	return IRQ_HANDLED;
441 }
442 
443 void dp_aux_enable_xfers(struct drm_dp_aux *dp_aux, bool enabled)
444 {
445 	struct dp_aux_private *aux;
446 
447 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
448 	aux->enable_xfers = enabled;
449 }
450 
451 void dp_aux_reconfig(struct drm_dp_aux *dp_aux)
452 {
453 	struct dp_aux_private *aux;
454 
455 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
456 
457 	dp_catalog_aux_update_cfg(aux->catalog);
458 	dp_catalog_aux_reset(aux->catalog);
459 }
460 
461 void dp_aux_init(struct drm_dp_aux *dp_aux)
462 {
463 	struct dp_aux_private *aux;
464 
465 	if (!dp_aux) {
466 		DRM_ERROR("invalid input\n");
467 		return;
468 	}
469 
470 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
471 
472 	mutex_lock(&aux->mutex);
473 
474 	dp_catalog_aux_enable(aux->catalog, true);
475 	aux->retry_cnt = 0;
476 	aux->initted = true;
477 
478 	mutex_unlock(&aux->mutex);
479 }
480 
481 void dp_aux_deinit(struct drm_dp_aux *dp_aux)
482 {
483 	struct dp_aux_private *aux;
484 
485 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
486 
487 	mutex_lock(&aux->mutex);
488 
489 	aux->initted = false;
490 	dp_catalog_aux_enable(aux->catalog, false);
491 
492 	mutex_unlock(&aux->mutex);
493 }
494 
495 int dp_aux_register(struct drm_dp_aux *dp_aux)
496 {
497 	struct dp_aux_private *aux;
498 	int ret;
499 
500 	if (!dp_aux) {
501 		DRM_ERROR("invalid input\n");
502 		return -EINVAL;
503 	}
504 
505 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
506 
507 	aux->dp_aux.name = "dpu_dp_aux";
508 	aux->dp_aux.dev = aux->dev;
509 	aux->dp_aux.transfer = dp_aux_transfer;
510 	ret = drm_dp_aux_register(&aux->dp_aux);
511 	if (ret) {
512 		DRM_ERROR("%s: failed to register drm aux: %d\n", __func__,
513 				ret);
514 		return ret;
515 	}
516 
517 	return 0;
518 }
519 
520 void dp_aux_unregister(struct drm_dp_aux *dp_aux)
521 {
522 	drm_dp_aux_unregister(dp_aux);
523 }
524 
525 struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog,
526 			      bool is_edp)
527 {
528 	struct dp_aux_private *aux;
529 
530 	if (!catalog) {
531 		DRM_ERROR("invalid input\n");
532 		return ERR_PTR(-ENODEV);
533 	}
534 
535 	aux = devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL);
536 	if (!aux)
537 		return ERR_PTR(-ENOMEM);
538 
539 	init_completion(&aux->comp);
540 	aux->cmd_busy = false;
541 	aux->is_edp = is_edp;
542 	mutex_init(&aux->mutex);
543 
544 	aux->dev = dev;
545 	aux->catalog = catalog;
546 	aux->retry_cnt = 0;
547 
548 	return &aux->dp_aux;
549 }
550 
551 void dp_aux_put(struct drm_dp_aux *dp_aux)
552 {
553 	struct dp_aux_private *aux;
554 
555 	if (!dp_aux)
556 		return;
557 
558 	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
559 
560 	mutex_destroy(&aux->mutex);
561 
562 	devm_kfree(aux->dev, aux);
563 }
564