1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/delay.h> 7 #include <drm/drm_print.h> 8 9 #include "dp_reg.h" 10 #include "dp_aux.h" 11 12 #define DP_AUX_ENUM_STR(x) #x 13 14 struct dp_aux_private { 15 struct device *dev; 16 struct dp_catalog *catalog; 17 18 struct mutex mutex; 19 struct completion comp; 20 21 u32 aux_error_num; 22 u32 retry_cnt; 23 bool cmd_busy; 24 bool native; 25 bool read; 26 bool no_send_addr; 27 bool no_send_stop; 28 u32 offset; 29 u32 segment; 30 u32 isr; 31 32 struct drm_dp_aux dp_aux; 33 }; 34 35 #define MAX_AUX_RETRIES 5 36 37 static const char *dp_aux_get_error(u32 aux_error) 38 { 39 switch (aux_error) { 40 case DP_AUX_ERR_NONE: 41 return DP_AUX_ENUM_STR(DP_AUX_ERR_NONE); 42 case DP_AUX_ERR_ADDR: 43 return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR); 44 case DP_AUX_ERR_TOUT: 45 return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT); 46 case DP_AUX_ERR_NACK: 47 return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK); 48 case DP_AUX_ERR_DEFER: 49 return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER); 50 case DP_AUX_ERR_NACK_DEFER: 51 return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER); 52 default: 53 return "unknown"; 54 } 55 } 56 57 static u32 dp_aux_write(struct dp_aux_private *aux, 58 struct drm_dp_aux_msg *msg) 59 { 60 u32 data[4], reg, len; 61 u8 *msgdata = msg->buffer; 62 int const AUX_CMD_FIFO_LEN = 128; 63 int i = 0; 64 65 if (aux->read) 66 len = 4; 67 else 68 len = msg->size + 4; 69 70 /* 71 * cmd fifo only has depth of 144 bytes 72 * limit buf length to 128 bytes here 73 */ 74 if (len > AUX_CMD_FIFO_LEN) { 75 DRM_ERROR("buf size greater than allowed size of 128 bytes\n"); 76 return 0; 77 } 78 79 /* Pack cmd and write to HW */ 80 data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */ 81 if (aux->read) 82 data[0] |= BIT(4); /* R/W */ 83 84 data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */ 85 data[2] = msg->address & 0xff; /* addr[7:0] */ 86 data[3] = (msg->size - 1) & 0xff; /* len[7:0] */ 87 88 for (i = 0; i < len; i++) { 89 reg = (i < 4) ? data[i] : msgdata[i - 4]; 90 /* index = 0, write */ 91 reg = (((reg) << DP_AUX_DATA_OFFSET) 92 & DP_AUX_DATA_MASK) | DP_AUX_DATA_WRITE; 93 if (i == 0) 94 reg |= DP_AUX_DATA_INDEX_WRITE; 95 aux->catalog->aux_data = reg; 96 dp_catalog_aux_write_data(aux->catalog); 97 } 98 99 dp_catalog_aux_clear_trans(aux->catalog, false); 100 dp_catalog_aux_clear_hw_interrupts(aux->catalog); 101 102 reg = 0; /* Transaction number == 1 */ 103 if (!aux->native) { /* i2c */ 104 reg |= DP_AUX_TRANS_CTRL_I2C; 105 106 if (aux->no_send_addr) 107 reg |= DP_AUX_TRANS_CTRL_NO_SEND_ADDR; 108 109 if (aux->no_send_stop) 110 reg |= DP_AUX_TRANS_CTRL_NO_SEND_STOP; 111 } 112 113 reg |= DP_AUX_TRANS_CTRL_GO; 114 aux->catalog->aux_data = reg; 115 dp_catalog_aux_write_trans(aux->catalog); 116 117 return len; 118 } 119 120 static int dp_aux_cmd_fifo_tx(struct dp_aux_private *aux, 121 struct drm_dp_aux_msg *msg) 122 { 123 u32 ret, len, timeout; 124 int aux_timeout_ms = HZ/4; 125 126 reinit_completion(&aux->comp); 127 128 len = dp_aux_write(aux, msg); 129 if (len == 0) { 130 DRM_ERROR("DP AUX write failed\n"); 131 return -EINVAL; 132 } 133 134 timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms); 135 if (!timeout) { 136 DRM_ERROR("aux %s timeout\n", (aux->read ? "read" : "write")); 137 return -ETIMEDOUT; 138 } 139 140 if (aux->aux_error_num == DP_AUX_ERR_NONE) { 141 ret = len; 142 } else { 143 DRM_ERROR_RATELIMITED("aux err: %s\n", 144 dp_aux_get_error(aux->aux_error_num)); 145 146 ret = -EINVAL; 147 } 148 149 return ret; 150 } 151 152 static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux, 153 struct drm_dp_aux_msg *msg) 154 { 155 u32 data; 156 u8 *dp; 157 u32 i, actual_i; 158 u32 len = msg->size; 159 160 dp_catalog_aux_clear_trans(aux->catalog, true); 161 162 data = DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */ 163 data |= DP_AUX_DATA_READ; /* read */ 164 165 aux->catalog->aux_data = data; 166 dp_catalog_aux_write_data(aux->catalog); 167 168 dp = msg->buffer; 169 170 /* discard first byte */ 171 data = dp_catalog_aux_read_data(aux->catalog); 172 173 for (i = 0; i < len; i++) { 174 data = dp_catalog_aux_read_data(aux->catalog); 175 *dp++ = (u8)((data >> DP_AUX_DATA_OFFSET) & 0xff); 176 177 actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF; 178 if (i != actual_i) 179 DRM_ERROR("Index mismatch: expected %d, found %d\n", 180 i, actual_i); 181 } 182 } 183 184 static void dp_aux_native_handler(struct dp_aux_private *aux) 185 { 186 u32 isr = aux->isr; 187 188 if (isr & DP_INTR_AUX_I2C_DONE) 189 aux->aux_error_num = DP_AUX_ERR_NONE; 190 else if (isr & DP_INTR_WRONG_ADDR) 191 aux->aux_error_num = DP_AUX_ERR_ADDR; 192 else if (isr & DP_INTR_TIMEOUT) 193 aux->aux_error_num = DP_AUX_ERR_TOUT; 194 if (isr & DP_INTR_NACK_DEFER) 195 aux->aux_error_num = DP_AUX_ERR_NACK; 196 if (isr & DP_INTR_AUX_ERROR) { 197 aux->aux_error_num = DP_AUX_ERR_PHY; 198 dp_catalog_aux_clear_hw_interrupts(aux->catalog); 199 } 200 201 complete(&aux->comp); 202 } 203 204 static void dp_aux_i2c_handler(struct dp_aux_private *aux) 205 { 206 u32 isr = aux->isr; 207 208 if (isr & DP_INTR_AUX_I2C_DONE) { 209 if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER)) 210 aux->aux_error_num = DP_AUX_ERR_NACK; 211 else 212 aux->aux_error_num = DP_AUX_ERR_NONE; 213 } else { 214 if (isr & DP_INTR_WRONG_ADDR) 215 aux->aux_error_num = DP_AUX_ERR_ADDR; 216 else if (isr & DP_INTR_TIMEOUT) 217 aux->aux_error_num = DP_AUX_ERR_TOUT; 218 if (isr & DP_INTR_NACK_DEFER) 219 aux->aux_error_num = DP_AUX_ERR_NACK_DEFER; 220 if (isr & DP_INTR_I2C_NACK) 221 aux->aux_error_num = DP_AUX_ERR_NACK; 222 if (isr & DP_INTR_I2C_DEFER) 223 aux->aux_error_num = DP_AUX_ERR_DEFER; 224 if (isr & DP_INTR_AUX_ERROR) { 225 aux->aux_error_num = DP_AUX_ERR_PHY; 226 dp_catalog_aux_clear_hw_interrupts(aux->catalog); 227 } 228 } 229 230 complete(&aux->comp); 231 } 232 233 static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux, 234 struct drm_dp_aux_msg *input_msg) 235 { 236 u32 edid_address = 0x50; 237 u32 segment_address = 0x30; 238 bool i2c_read = input_msg->request & 239 (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); 240 u8 *data; 241 242 if (aux->native || i2c_read || ((input_msg->address != edid_address) && 243 (input_msg->address != segment_address))) 244 return; 245 246 247 data = input_msg->buffer; 248 if (input_msg->address == segment_address) 249 aux->segment = *data; 250 else 251 aux->offset = *data; 252 } 253 254 /** 255 * dp_aux_transfer_helper() - helper function for EDID read transactions 256 * 257 * @aux: DP AUX private structure 258 * @input_msg: input message from DRM upstream APIs 259 * @send_seg: send the segment to sink 260 * 261 * return: void 262 * 263 * This helper function is used to fix EDID reads for non-compliant 264 * sinks that do not handle the i2c middle-of-transaction flag correctly. 265 */ 266 static void dp_aux_transfer_helper(struct dp_aux_private *aux, 267 struct drm_dp_aux_msg *input_msg, 268 bool send_seg) 269 { 270 struct drm_dp_aux_msg helper_msg; 271 u32 message_size = 0x10; 272 u32 segment_address = 0x30; 273 u32 const edid_block_length = 0x80; 274 bool i2c_mot = input_msg->request & DP_AUX_I2C_MOT; 275 bool i2c_read = input_msg->request & 276 (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); 277 278 if (!i2c_mot || !i2c_read || (input_msg->size == 0)) 279 return; 280 281 /* 282 * Sending the segment value and EDID offset will be performed 283 * from the DRM upstream EDID driver for each block. Avoid 284 * duplicate AUX transactions related to this while reading the 285 * first 16 bytes of each block. 286 */ 287 if (!(aux->offset % edid_block_length) || !send_seg) 288 goto end; 289 290 aux->read = false; 291 aux->cmd_busy = true; 292 aux->no_send_addr = true; 293 aux->no_send_stop = true; 294 295 /* 296 * Send the segment address for every i2c read in which the 297 * middle-of-tranaction flag is set. This is required to support EDID 298 * reads of more than 2 blocks as the segment address is reset to 0 299 * since we are overriding the middle-of-transaction flag for read 300 * transactions. 301 */ 302 303 if (aux->segment) { 304 memset(&helper_msg, 0, sizeof(helper_msg)); 305 helper_msg.address = segment_address; 306 helper_msg.buffer = &aux->segment; 307 helper_msg.size = 1; 308 dp_aux_cmd_fifo_tx(aux, &helper_msg); 309 } 310 311 /* 312 * Send the offset address for every i2c read in which the 313 * middle-of-transaction flag is set. This will ensure that the sink 314 * will update its read pointer and return the correct portion of the 315 * EDID buffer in the subsequent i2c read trasntion triggered in the 316 * native AUX transfer function. 317 */ 318 memset(&helper_msg, 0, sizeof(helper_msg)); 319 helper_msg.address = input_msg->address; 320 helper_msg.buffer = &aux->offset; 321 helper_msg.size = 1; 322 dp_aux_cmd_fifo_tx(aux, &helper_msg); 323 324 end: 325 aux->offset += message_size; 326 if (aux->offset == 0x80 || aux->offset == 0x100) 327 aux->segment = 0x0; /* reset segment at end of block */ 328 } 329 330 /* 331 * This function does the real job to process an AUX transaction. 332 * It will call aux_reset() function to reset the AUX channel, 333 * if the waiting is timeout. 334 */ 335 static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, 336 struct drm_dp_aux_msg *msg) 337 { 338 ssize_t ret; 339 int const aux_cmd_native_max = 16; 340 int const aux_cmd_i2c_max = 128; 341 struct dp_aux_private *aux = container_of(dp_aux, 342 struct dp_aux_private, dp_aux); 343 344 mutex_lock(&aux->mutex); 345 346 aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); 347 348 /* Ignore address only message */ 349 if ((msg->size == 0) || (msg->buffer == NULL)) { 350 msg->reply = aux->native ? 351 DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; 352 ret = msg->size; 353 goto unlock_exit; 354 } 355 356 /* msg sanity check */ 357 if ((aux->native && (msg->size > aux_cmd_native_max)) || 358 (msg->size > aux_cmd_i2c_max)) { 359 DRM_ERROR("%s: invalid msg: size(%zu), request(%x)\n", 360 __func__, msg->size, msg->request); 361 ret = -EINVAL; 362 goto unlock_exit; 363 } 364 365 dp_aux_update_offset_and_segment(aux, msg); 366 dp_aux_transfer_helper(aux, msg, true); 367 368 aux->read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); 369 aux->cmd_busy = true; 370 371 if (aux->read) { 372 aux->no_send_addr = true; 373 aux->no_send_stop = false; 374 } else { 375 aux->no_send_addr = true; 376 aux->no_send_stop = true; 377 } 378 379 ret = dp_aux_cmd_fifo_tx(aux, msg); 380 381 if (ret < 0) { 382 if (aux->native) { 383 aux->retry_cnt++; 384 if (!(aux->retry_cnt % MAX_AUX_RETRIES)) 385 dp_catalog_aux_update_cfg(aux->catalog); 386 } 387 usleep_range(400, 500); /* at least 400us to next try */ 388 goto unlock_exit; 389 } 390 391 if (aux->aux_error_num == DP_AUX_ERR_NONE) { 392 if (aux->read) 393 dp_aux_cmd_fifo_rx(aux, msg); 394 395 msg->reply = aux->native ? 396 DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; 397 } else { 398 /* Reply defer to retry */ 399 msg->reply = aux->native ? 400 DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER; 401 } 402 403 /* Return requested size for success or retry */ 404 ret = msg->size; 405 aux->retry_cnt = 0; 406 407 unlock_exit: 408 aux->cmd_busy = false; 409 mutex_unlock(&aux->mutex); 410 return ret; 411 } 412 413 void dp_aux_isr(struct drm_dp_aux *dp_aux) 414 { 415 struct dp_aux_private *aux; 416 417 if (!dp_aux) { 418 DRM_ERROR("invalid input\n"); 419 return; 420 } 421 422 aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 423 424 aux->isr = dp_catalog_aux_get_irq(aux->catalog); 425 426 if (!aux->cmd_busy) 427 return; 428 429 if (aux->native) 430 dp_aux_native_handler(aux); 431 else 432 dp_aux_i2c_handler(aux); 433 } 434 435 void dp_aux_reconfig(struct drm_dp_aux *dp_aux) 436 { 437 struct dp_aux_private *aux; 438 439 aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 440 441 dp_catalog_aux_update_cfg(aux->catalog); 442 dp_catalog_aux_reset(aux->catalog); 443 } 444 445 void dp_aux_init(struct drm_dp_aux *dp_aux) 446 { 447 struct dp_aux_private *aux; 448 449 if (!dp_aux) { 450 DRM_ERROR("invalid input\n"); 451 return; 452 } 453 454 aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 455 456 dp_catalog_aux_enable(aux->catalog, true); 457 aux->retry_cnt = 0; 458 } 459 460 void dp_aux_deinit(struct drm_dp_aux *dp_aux) 461 { 462 struct dp_aux_private *aux; 463 464 aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 465 466 dp_catalog_aux_enable(aux->catalog, false); 467 } 468 469 int dp_aux_register(struct drm_dp_aux *dp_aux) 470 { 471 struct dp_aux_private *aux; 472 int ret; 473 474 if (!dp_aux) { 475 DRM_ERROR("invalid input\n"); 476 return -EINVAL; 477 } 478 479 aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 480 481 aux->dp_aux.name = "dpu_dp_aux"; 482 aux->dp_aux.dev = aux->dev; 483 aux->dp_aux.transfer = dp_aux_transfer; 484 ret = drm_dp_aux_register(&aux->dp_aux); 485 if (ret) { 486 DRM_ERROR("%s: failed to register drm aux: %d\n", __func__, 487 ret); 488 return ret; 489 } 490 491 return 0; 492 } 493 494 void dp_aux_unregister(struct drm_dp_aux *dp_aux) 495 { 496 drm_dp_aux_unregister(dp_aux); 497 } 498 499 struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog) 500 { 501 struct dp_aux_private *aux; 502 503 if (!catalog) { 504 DRM_ERROR("invalid input\n"); 505 return ERR_PTR(-ENODEV); 506 } 507 508 aux = devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL); 509 if (!aux) 510 return ERR_PTR(-ENOMEM); 511 512 init_completion(&aux->comp); 513 aux->cmd_busy = false; 514 mutex_init(&aux->mutex); 515 516 aux->dev = dev; 517 aux->catalog = catalog; 518 aux->retry_cnt = 0; 519 520 return &aux->dp_aux; 521 } 522 523 void dp_aux_put(struct drm_dp_aux *dp_aux) 524 { 525 struct dp_aux_private *aux; 526 527 if (!dp_aux) 528 return; 529 530 aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 531 532 mutex_destroy(&aux->mutex); 533 534 devm_kfree(aux->dev, aux); 535 } 536