1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <drm/drm_atomic.h> 9 #include <drm/drm_damage_helper.h> 10 #include <drm/drm_fourcc.h> 11 #include <drm/drm_gem_atomic_helper.h> 12 #include <drm/drm_print.h> 13 14 #include "mdp5_kms.h" 15 16 struct mdp5_plane { 17 struct drm_plane base; 18 19 uint32_t nformats; 20 uint32_t formats[32]; 21 }; 22 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) 23 24 static int mdp5_plane_mode_set(struct drm_plane *plane, 25 struct drm_crtc *crtc, struct drm_framebuffer *fb, 26 struct drm_rect *src, struct drm_rect *dest); 27 28 static struct mdp5_kms *get_kms(struct drm_plane *plane) 29 { 30 struct msm_drm_private *priv = plane->dev->dev_private; 31 return to_mdp5_kms(to_mdp_kms(priv->kms)); 32 } 33 34 static bool plane_enabled(struct drm_plane_state *state) 35 { 36 return state->visible; 37 } 38 39 static void mdp5_plane_destroy(struct drm_plane *plane) 40 { 41 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); 42 43 drm_plane_cleanup(plane); 44 45 kfree(mdp5_plane); 46 } 47 48 /* helper to install properties which are common to planes and crtcs */ 49 static void mdp5_plane_install_properties(struct drm_plane *plane, 50 struct drm_mode_object *obj) 51 { 52 unsigned int zpos; 53 54 drm_plane_create_rotation_property(plane, 55 DRM_MODE_ROTATE_0, 56 DRM_MODE_ROTATE_0 | 57 DRM_MODE_ROTATE_180 | 58 DRM_MODE_REFLECT_X | 59 DRM_MODE_REFLECT_Y); 60 drm_plane_create_alpha_property(plane); 61 drm_plane_create_blend_mode_property(plane, 62 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 63 BIT(DRM_MODE_BLEND_PREMULTI) | 64 BIT(DRM_MODE_BLEND_COVERAGE)); 65 66 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 67 zpos = STAGE_BASE; 68 else 69 zpos = STAGE0 + drm_plane_index(plane); 70 drm_plane_create_zpos_property(plane, zpos, 1, 255); 71 } 72 73 static void 74 mdp5_plane_atomic_print_state(struct drm_printer *p, 75 const struct drm_plane_state *state) 76 { 77 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 78 struct mdp5_kms *mdp5_kms = get_kms(state->plane); 79 80 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? 81 pstate->hwpipe->name : "(null)"); 82 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) 83 drm_printf(p, "\tright-hwpipe=%s\n", 84 pstate->r_hwpipe ? pstate->r_hwpipe->name : 85 "(null)"); 86 drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode); 87 drm_printf(p, "\tzpos=%u\n", pstate->base.zpos); 88 drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos); 89 drm_printf(p, "\talpha=%u\n", pstate->base.alpha); 90 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); 91 } 92 93 static void mdp5_plane_reset(struct drm_plane *plane) 94 { 95 struct mdp5_plane_state *mdp5_state; 96 97 if (plane->state) 98 __drm_atomic_helper_plane_destroy_state(plane->state); 99 100 kfree(to_mdp5_plane_state(plane->state)); 101 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); 102 __drm_atomic_helper_plane_reset(plane, &mdp5_state->base); 103 } 104 105 static struct drm_plane_state * 106 mdp5_plane_duplicate_state(struct drm_plane *plane) 107 { 108 struct mdp5_plane_state *mdp5_state; 109 110 if (WARN_ON(!plane->state)) 111 return NULL; 112 113 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state), 114 sizeof(*mdp5_state), GFP_KERNEL); 115 if (!mdp5_state) 116 return NULL; 117 118 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); 119 120 return &mdp5_state->base; 121 } 122 123 static void mdp5_plane_destroy_state(struct drm_plane *plane, 124 struct drm_plane_state *state) 125 { 126 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 127 128 if (state->fb) 129 drm_framebuffer_put(state->fb); 130 131 kfree(pstate); 132 } 133 134 static const struct drm_plane_funcs mdp5_plane_funcs = { 135 .update_plane = drm_atomic_helper_update_plane, 136 .disable_plane = drm_atomic_helper_disable_plane, 137 .destroy = mdp5_plane_destroy, 138 .reset = mdp5_plane_reset, 139 .atomic_duplicate_state = mdp5_plane_duplicate_state, 140 .atomic_destroy_state = mdp5_plane_destroy_state, 141 .atomic_print_state = mdp5_plane_atomic_print_state, 142 }; 143 144 static int mdp5_plane_prepare_fb(struct drm_plane *plane, 145 struct drm_plane_state *new_state) 146 { 147 struct msm_drm_private *priv = plane->dev->dev_private; 148 struct msm_kms *kms = priv->kms; 149 bool needs_dirtyfb = to_mdp5_plane_state(new_state)->needs_dirtyfb; 150 151 if (!new_state->fb) 152 return 0; 153 154 drm_gem_plane_helper_prepare_fb(plane, new_state); 155 156 return msm_framebuffer_prepare(new_state->fb, kms->aspace, needs_dirtyfb); 157 } 158 159 static void mdp5_plane_cleanup_fb(struct drm_plane *plane, 160 struct drm_plane_state *old_state) 161 { 162 struct mdp5_kms *mdp5_kms = get_kms(plane); 163 struct msm_kms *kms = &mdp5_kms->base.base; 164 struct drm_framebuffer *fb = old_state->fb; 165 bool needed_dirtyfb = to_mdp5_plane_state(old_state)->needs_dirtyfb; 166 167 if (!fb) 168 return; 169 170 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); 171 msm_framebuffer_cleanup(fb, kms->aspace, needed_dirtyfb); 172 } 173 174 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, 175 struct drm_plane_state *state) 176 { 177 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 178 struct drm_plane *plane = state->plane; 179 struct drm_plane_state *old_state = plane->state; 180 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg); 181 bool new_hwpipe = false; 182 bool need_right_hwpipe = false; 183 uint32_t max_width, max_height; 184 bool out_of_bounds = false; 185 uint32_t caps = 0; 186 int min_scale, max_scale; 187 int ret; 188 189 DBG("%s: check (%d -> %d)", plane->name, 190 plane_enabled(old_state), plane_enabled(state)); 191 192 max_width = config->hw->lm.max_width << 16; 193 max_height = config->hw->lm.max_height << 16; 194 195 /* Make sure source dimensions are within bounds. */ 196 if (state->src_h > max_height) 197 out_of_bounds = true; 198 199 if (state->src_w > max_width) { 200 /* If source split is supported, we can go up to 2x 201 * the max LM width, but we'd need to stage another 202 * hwpipe to the right LM. So, the drm_plane would 203 * consist of 2 hwpipes. 204 */ 205 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT && 206 (state->src_w <= 2 * max_width)) 207 need_right_hwpipe = true; 208 else 209 out_of_bounds = true; 210 } 211 212 if (out_of_bounds) { 213 struct drm_rect src = drm_plane_state_src(state); 214 DBG("Invalid source size "DRM_RECT_FP_FMT, 215 DRM_RECT_FP_ARG(&src)); 216 return -ERANGE; 217 } 218 219 min_scale = FRAC_16_16(1, 8); 220 max_scale = FRAC_16_16(8, 1); 221 222 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 223 min_scale, max_scale, 224 true, true); 225 if (ret) 226 return ret; 227 228 if (plane_enabled(state)) { 229 unsigned int rotation; 230 const struct mdp_format *format; 231 struct mdp5_kms *mdp5_kms = get_kms(plane); 232 uint32_t blkcfg = 0; 233 234 format = to_mdp_format(msm_framebuffer_format(state->fb)); 235 if (MDP_FORMAT_IS_YUV(format)) 236 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC; 237 238 if (((state->src_w >> 16) != state->crtc_w) || 239 ((state->src_h >> 16) != state->crtc_h)) 240 caps |= MDP_PIPE_CAP_SCALE; 241 242 rotation = drm_rotation_simplify(state->rotation, 243 DRM_MODE_ROTATE_0 | 244 DRM_MODE_REFLECT_X | 245 DRM_MODE_REFLECT_Y); 246 247 if (rotation & DRM_MODE_REFLECT_X) 248 caps |= MDP_PIPE_CAP_HFLIP; 249 250 if (rotation & DRM_MODE_REFLECT_Y) 251 caps |= MDP_PIPE_CAP_VFLIP; 252 253 if (plane->type == DRM_PLANE_TYPE_CURSOR) 254 caps |= MDP_PIPE_CAP_CURSOR; 255 256 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */ 257 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps)) 258 new_hwpipe = true; 259 260 /* 261 * (re)allocte hw pipe if we're either requesting for 2 hw pipes 262 * or we're switching from 2 hw pipes to 1 hw pipe because the 263 * new src_w can be supported by 1 hw pipe itself. 264 */ 265 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) || 266 (!need_right_hwpipe && mdp5_state->r_hwpipe)) 267 new_hwpipe = true; 268 269 if (mdp5_kms->smp) { 270 const struct mdp_format *format = 271 to_mdp_format(msm_framebuffer_format(state->fb)); 272 273 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, 274 state->src_w >> 16, false); 275 276 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg)) 277 new_hwpipe = true; 278 } 279 280 /* (re)assign hwpipe if needed, otherwise keep old one: */ 281 if (new_hwpipe) { 282 /* TODO maybe we want to re-assign hwpipe sometimes 283 * in cases when we no-longer need some caps to make 284 * it available for other planes? 285 */ 286 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe; 287 struct mdp5_hw_pipe *old_right_hwpipe = 288 mdp5_state->r_hwpipe; 289 struct mdp5_hw_pipe *new_hwpipe = NULL; 290 struct mdp5_hw_pipe *new_right_hwpipe = NULL; 291 292 ret = mdp5_pipe_assign(state->state, plane, caps, 293 blkcfg, &new_hwpipe, 294 need_right_hwpipe ? 295 &new_right_hwpipe : NULL); 296 if (ret) { 297 DBG("%s: failed to assign hwpipe(s)!", 298 plane->name); 299 return ret; 300 } 301 302 mdp5_state->hwpipe = new_hwpipe; 303 if (need_right_hwpipe) 304 mdp5_state->r_hwpipe = new_right_hwpipe; 305 else 306 /* 307 * set it to NULL so that the driver knows we 308 * don't have a right hwpipe when committing a 309 * new state 310 */ 311 mdp5_state->r_hwpipe = NULL; 312 313 314 mdp5_pipe_release(state->state, old_hwpipe); 315 mdp5_pipe_release(state->state, old_right_hwpipe); 316 } 317 } else { 318 mdp5_pipe_release(state->state, mdp5_state->hwpipe); 319 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe); 320 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL; 321 } 322 323 return 0; 324 } 325 326 static int mdp5_plane_atomic_check(struct drm_plane *plane, 327 struct drm_atomic_state *state) 328 { 329 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 330 plane); 331 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 332 plane); 333 struct drm_crtc *crtc; 334 struct drm_crtc_state *crtc_state; 335 336 crtc = new_plane_state->crtc ? new_plane_state->crtc : old_plane_state->crtc; 337 if (!crtc) 338 return 0; 339 340 crtc_state = drm_atomic_get_existing_crtc_state(state, 341 crtc); 342 if (WARN_ON(!crtc_state)) 343 return -EINVAL; 344 345 return mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state); 346 } 347 348 static void mdp5_plane_atomic_update(struct drm_plane *plane, 349 struct drm_atomic_state *state) 350 { 351 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 352 plane); 353 354 DBG("%s: update", plane->name); 355 356 if (plane_enabled(new_state)) { 357 int ret; 358 359 ret = mdp5_plane_mode_set(plane, 360 new_state->crtc, new_state->fb, 361 &new_state->src, &new_state->dst); 362 /* atomic_check should have ensured that this doesn't fail */ 363 WARN_ON(ret < 0); 364 } 365 } 366 367 static int mdp5_plane_atomic_async_check(struct drm_plane *plane, 368 struct drm_atomic_state *state) 369 { 370 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 371 plane); 372 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(new_plane_state); 373 struct drm_crtc_state *crtc_state; 374 int min_scale, max_scale; 375 int ret; 376 377 crtc_state = drm_atomic_get_existing_crtc_state(state, 378 new_plane_state->crtc); 379 if (WARN_ON(!crtc_state)) 380 return -EINVAL; 381 382 if (!crtc_state->active) 383 return -EINVAL; 384 385 mdp5_state = to_mdp5_plane_state(new_plane_state); 386 387 /* don't use fast path if we don't have a hwpipe allocated yet */ 388 if (!mdp5_state->hwpipe) 389 return -EINVAL; 390 391 /* only allow changing of position(crtc x/y or src x/y) in fast path */ 392 if (plane->state->crtc != new_plane_state->crtc || 393 plane->state->src_w != new_plane_state->src_w || 394 plane->state->src_h != new_plane_state->src_h || 395 plane->state->crtc_w != new_plane_state->crtc_w || 396 plane->state->crtc_h != new_plane_state->crtc_h || 397 !plane->state->fb || 398 plane->state->fb != new_plane_state->fb) 399 return -EINVAL; 400 401 min_scale = FRAC_16_16(1, 8); 402 max_scale = FRAC_16_16(8, 1); 403 404 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 405 min_scale, max_scale, 406 true, true); 407 if (ret) 408 return ret; 409 410 /* 411 * if the visibility of the plane changes (i.e, if the cursor is 412 * clipped out completely, we can't take the async path because 413 * we need to stage/unstage the plane from the Layer Mixer(s). We 414 * also assign/unassign the hwpipe(s) tied to the plane. We avoid 415 * taking the fast path for both these reasons. 416 */ 417 if (new_plane_state->visible != plane->state->visible) 418 return -EINVAL; 419 420 return 0; 421 } 422 423 static void mdp5_plane_atomic_async_update(struct drm_plane *plane, 424 struct drm_atomic_state *state) 425 { 426 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 427 plane); 428 struct drm_framebuffer *old_fb = plane->state->fb; 429 430 plane->state->src_x = new_state->src_x; 431 plane->state->src_y = new_state->src_y; 432 plane->state->crtc_x = new_state->crtc_x; 433 plane->state->crtc_y = new_state->crtc_y; 434 435 if (plane_enabled(new_state)) { 436 struct mdp5_ctl *ctl; 437 struct mdp5_pipeline *pipeline = 438 mdp5_crtc_get_pipeline(new_state->crtc); 439 int ret; 440 441 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb, 442 &new_state->src, &new_state->dst); 443 WARN_ON(ret < 0); 444 445 ctl = mdp5_crtc_get_ctl(new_state->crtc); 446 447 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true); 448 } 449 450 *to_mdp5_plane_state(plane->state) = 451 *to_mdp5_plane_state(new_state); 452 453 new_state->fb = old_fb; 454 } 455 456 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { 457 .prepare_fb = mdp5_plane_prepare_fb, 458 .cleanup_fb = mdp5_plane_cleanup_fb, 459 .atomic_check = mdp5_plane_atomic_check, 460 .atomic_update = mdp5_plane_atomic_update, 461 .atomic_async_check = mdp5_plane_atomic_async_check, 462 .atomic_async_update = mdp5_plane_atomic_async_update, 463 }; 464 465 static void set_scanout_locked(struct mdp5_kms *mdp5_kms, 466 enum mdp5_pipe pipe, 467 struct drm_framebuffer *fb) 468 { 469 struct msm_kms *kms = &mdp5_kms->base.base; 470 471 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), 472 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | 473 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1])); 474 475 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), 476 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) | 477 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); 478 479 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), 480 msm_framebuffer_iova(fb, kms->aspace, 0)); 481 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), 482 msm_framebuffer_iova(fb, kms->aspace, 1)); 483 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), 484 msm_framebuffer_iova(fb, kms->aspace, 2)); 485 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), 486 msm_framebuffer_iova(fb, kms->aspace, 3)); 487 } 488 489 /* Note: mdp5_plane->pipe_lock must be locked */ 490 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) 491 { 492 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & 493 ~MDP5_PIPE_OP_MODE_CSC_1_EN; 494 495 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); 496 } 497 498 /* Note: mdp5_plane->pipe_lock must be locked */ 499 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 500 struct csc_cfg *csc) 501 { 502 uint32_t i, mode = 0; /* RGB, no CSC */ 503 uint32_t *matrix; 504 505 if (unlikely(!csc)) 506 return; 507 508 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) 509 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV); 510 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) 511 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); 512 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN; 513 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); 514 515 matrix = csc->matrix; 516 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), 517 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) | 518 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1])); 519 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), 520 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) | 521 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3])); 522 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), 523 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) | 524 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5])); 525 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), 526 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) | 527 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7])); 528 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), 529 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8])); 530 531 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { 532 uint32_t *pre_clamp = csc->pre_clamp; 533 uint32_t *post_clamp = csc->post_clamp; 534 535 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), 536 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) | 537 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i])); 538 539 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), 540 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) | 541 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i])); 542 543 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), 544 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); 545 546 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), 547 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); 548 } 549 } 550 551 #define PHASE_STEP_SHIFT 21 552 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */ 553 554 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) 555 { 556 uint32_t unit; 557 558 if (src == 0 || dst == 0) 559 return -EINVAL; 560 561 /* 562 * PHASE_STEP_X/Y is coded on 26 bits (25:0), 563 * where 2^21 represents the unity "1" in fixed-point hardware design. 564 * This leaves 5 bits for the integer part (downscale case): 565 * -> maximum downscale ratio = 0b1_1111 = 31 566 */ 567 if (src > (dst * DOWN_SCALE_RATIO_MAX)) 568 return -EOVERFLOW; 569 570 unit = 1 << PHASE_STEP_SHIFT; 571 *out_phase = mult_frac(unit, src, dst); 572 573 return 0; 574 } 575 576 static int calc_scalex_steps(struct drm_plane *plane, 577 uint32_t pixel_format, uint32_t src, uint32_t dest, 578 uint32_t phasex_steps[COMP_MAX]) 579 { 580 const struct drm_format_info *info = drm_format_info(pixel_format); 581 struct mdp5_kms *mdp5_kms = get_kms(plane); 582 struct device *dev = mdp5_kms->dev->dev; 583 uint32_t phasex_step; 584 int ret; 585 586 ret = calc_phase_step(src, dest, &phasex_step); 587 if (ret) { 588 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); 589 return ret; 590 } 591 592 phasex_steps[COMP_0] = phasex_step; 593 phasex_steps[COMP_3] = phasex_step; 594 phasex_steps[COMP_1_2] = phasex_step / info->hsub; 595 596 return 0; 597 } 598 599 static int calc_scaley_steps(struct drm_plane *plane, 600 uint32_t pixel_format, uint32_t src, uint32_t dest, 601 uint32_t phasey_steps[COMP_MAX]) 602 { 603 const struct drm_format_info *info = drm_format_info(pixel_format); 604 struct mdp5_kms *mdp5_kms = get_kms(plane); 605 struct device *dev = mdp5_kms->dev->dev; 606 uint32_t phasey_step; 607 int ret; 608 609 ret = calc_phase_step(src, dest, &phasey_step); 610 if (ret) { 611 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); 612 return ret; 613 } 614 615 phasey_steps[COMP_0] = phasey_step; 616 phasey_steps[COMP_3] = phasey_step; 617 phasey_steps[COMP_1_2] = phasey_step / info->vsub; 618 619 return 0; 620 } 621 622 static uint32_t get_scale_config(const struct mdp_format *format, 623 uint32_t src, uint32_t dst, bool horz) 624 { 625 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 626 bool scaling = format->is_yuv ? true : (src != dst); 627 uint32_t sub; 628 uint32_t ya_filter, uv_filter; 629 bool yuv = format->is_yuv; 630 631 if (!scaling) 632 return 0; 633 634 if (yuv) { 635 sub = horz ? info->hsub : info->vsub; 636 uv_filter = ((src / sub) <= dst) ? 637 SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 638 } 639 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 640 641 if (horz) 642 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | 643 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | 644 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | 645 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); 646 else 647 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | 648 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | 649 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | 650 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); 651 } 652 653 static void calc_pixel_ext(const struct mdp_format *format, 654 uint32_t src, uint32_t dst, uint32_t phase_step[2], 655 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], 656 bool horz) 657 { 658 bool scaling = format->is_yuv ? true : (src != dst); 659 int i; 660 661 /* 662 * Note: 663 * We assume here that: 664 * 1. PCMN filter is used for downscale 665 * 2. bilinear filter is used for upscale 666 * 3. we are in a single pipe configuration 667 */ 668 669 for (i = 0; i < COMP_MAX; i++) { 670 pix_ext_edge1[i] = 0; 671 pix_ext_edge2[i] = scaling ? 1 : 0; 672 } 673 } 674 675 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 676 const struct mdp_format *format, 677 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], 678 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) 679 { 680 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 681 uint32_t lr, tb, req; 682 int i; 683 684 for (i = 0; i < COMP_MAX; i++) { 685 uint32_t roi_w = src_w; 686 uint32_t roi_h = src_h; 687 688 if (format->is_yuv && i == COMP_1_2) { 689 roi_w /= info->hsub; 690 roi_h /= info->vsub; 691 } 692 693 lr = (pe_left[i] >= 0) ? 694 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : 695 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); 696 697 lr |= (pe_right[i] >= 0) ? 698 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : 699 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); 700 701 tb = (pe_top[i] >= 0) ? 702 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : 703 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); 704 705 tb |= (pe_bottom[i] >= 0) ? 706 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : 707 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); 708 709 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + 710 pe_left[i] + pe_right[i]); 711 712 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + 713 pe_top[i] + pe_bottom[i]); 714 715 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); 716 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); 717 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); 718 719 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, 720 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), 721 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), 722 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), 723 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), 724 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); 725 726 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, 727 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), 728 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), 729 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), 730 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), 731 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); 732 } 733 } 734 735 struct pixel_ext { 736 int left[COMP_MAX]; 737 int right[COMP_MAX]; 738 int top[COMP_MAX]; 739 int bottom[COMP_MAX]; 740 }; 741 742 struct phase_step { 743 u32 x[COMP_MAX]; 744 u32 y[COMP_MAX]; 745 }; 746 747 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms, 748 struct mdp5_hw_pipe *hwpipe, 749 struct drm_framebuffer *fb, 750 struct phase_step *step, 751 struct pixel_ext *pe, 752 u32 scale_config, u32 hdecm, u32 vdecm, 753 bool hflip, bool vflip, 754 int crtc_x, int crtc_y, 755 unsigned int crtc_w, unsigned int crtc_h, 756 u32 src_img_w, u32 src_img_h, 757 u32 src_x, u32 src_y, 758 u32 src_w, u32 src_h) 759 { 760 enum mdp5_pipe pipe = hwpipe->pipe; 761 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT; 762 const struct mdp_format *format = 763 to_mdp_format(msm_framebuffer_format(fb)); 764 765 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), 766 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) | 767 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h)); 768 769 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), 770 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | 771 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); 772 773 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), 774 MDP5_PIPE_SRC_XY_X(src_x) | 775 MDP5_PIPE_SRC_XY_Y(src_y)); 776 777 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), 778 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | 779 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); 780 781 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), 782 MDP5_PIPE_OUT_XY_X(crtc_x) | 783 MDP5_PIPE_OUT_XY_Y(crtc_y)); 784 785 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), 786 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) | 787 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) | 788 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) | 789 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) | 790 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) | 791 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) | 792 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | 793 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) | 794 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) | 795 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample)); 796 797 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), 798 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) | 799 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) | 800 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) | 801 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3])); 802 803 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), 804 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | 805 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | 806 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | 807 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); 808 809 /* not using secure mode: */ 810 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); 811 812 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) 813 mdp5_write_pixel_ext(mdp5_kms, pipe, format, 814 src_w, pe->left, pe->right, 815 src_h, pe->top, pe->bottom); 816 817 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) { 818 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), 819 step->x[COMP_0]); 820 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), 821 step->y[COMP_0]); 822 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), 823 step->x[COMP_1_2]); 824 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), 825 step->y[COMP_1_2]); 826 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), 827 MDP5_PIPE_DECIMATION_VERT(vdecm) | 828 MDP5_PIPE_DECIMATION_HORZ(hdecm)); 829 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), 830 scale_config); 831 } 832 833 if (hwpipe->caps & MDP_PIPE_CAP_CSC) { 834 if (MDP_FORMAT_IS_YUV(format)) 835 csc_enable(mdp5_kms, pipe, 836 mdp_get_default_csc_cfg(CSC_YUV2RGB)); 837 else 838 csc_disable(mdp5_kms, pipe); 839 } 840 841 set_scanout_locked(mdp5_kms, pipe, fb); 842 } 843 844 static int mdp5_plane_mode_set(struct drm_plane *plane, 845 struct drm_crtc *crtc, struct drm_framebuffer *fb, 846 struct drm_rect *src, struct drm_rect *dest) 847 { 848 struct drm_plane_state *pstate = plane->state; 849 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; 850 struct mdp5_kms *mdp5_kms = get_kms(plane); 851 enum mdp5_pipe pipe = hwpipe->pipe; 852 struct mdp5_hw_pipe *right_hwpipe; 853 const struct mdp_format *format; 854 uint32_t nplanes, config = 0; 855 struct phase_step step = { { 0 } }; 856 struct pixel_ext pe = { { 0 } }; 857 uint32_t hdecm = 0, vdecm = 0; 858 uint32_t pix_format; 859 unsigned int rotation; 860 bool vflip, hflip; 861 int crtc_x, crtc_y; 862 unsigned int crtc_w, crtc_h; 863 uint32_t src_x, src_y; 864 uint32_t src_w, src_h; 865 uint32_t src_img_w, src_img_h; 866 int ret; 867 868 nplanes = fb->format->num_planes; 869 870 /* bad formats should already be rejected: */ 871 if (WARN_ON(nplanes > pipe2nclients(pipe))) 872 return -EINVAL; 873 874 format = to_mdp_format(msm_framebuffer_format(fb)); 875 pix_format = format->base.pixel_format; 876 877 src_x = src->x1; 878 src_y = src->y1; 879 src_w = drm_rect_width(src); 880 src_h = drm_rect_height(src); 881 882 crtc_x = dest->x1; 883 crtc_y = dest->y1; 884 crtc_w = drm_rect_width(dest); 885 crtc_h = drm_rect_height(dest); 886 887 /* src values are in Q16 fixed point, convert to integer: */ 888 src_x = src_x >> 16; 889 src_y = src_y >> 16; 890 src_w = src_w >> 16; 891 src_h = src_h >> 16; 892 893 src_img_w = min(fb->width, src_w); 894 src_img_h = min(fb->height, src_h); 895 896 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name, 897 fb->base.id, src_x, src_y, src_w, src_h, 898 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); 899 900 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe; 901 if (right_hwpipe) { 902 /* 903 * if the plane comprises of 2 hw pipes, assume that the width 904 * is split equally across them. The only parameters that varies 905 * between the 2 pipes are src_x and crtc_x 906 */ 907 crtc_w /= 2; 908 src_w /= 2; 909 src_img_w /= 2; 910 } 911 912 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); 913 if (ret) 914 return ret; 915 916 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y); 917 if (ret) 918 return ret; 919 920 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) { 921 calc_pixel_ext(format, src_w, crtc_w, step.x, 922 pe.left, pe.right, true); 923 calc_pixel_ext(format, src_h, crtc_h, step.y, 924 pe.top, pe.bottom, false); 925 } 926 927 /* TODO calc hdecm, vdecm */ 928 929 /* SCALE is used to both scale and up-sample chroma components */ 930 config |= get_scale_config(format, src_w, crtc_w, true); 931 config |= get_scale_config(format, src_h, crtc_h, false); 932 DBG("scale config = %x", config); 933 934 rotation = drm_rotation_simplify(pstate->rotation, 935 DRM_MODE_ROTATE_0 | 936 DRM_MODE_REFLECT_X | 937 DRM_MODE_REFLECT_Y); 938 hflip = !!(rotation & DRM_MODE_REFLECT_X); 939 vflip = !!(rotation & DRM_MODE_REFLECT_Y); 940 941 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe, 942 config, hdecm, vdecm, hflip, vflip, 943 crtc_x, crtc_y, crtc_w, crtc_h, 944 src_img_w, src_img_h, 945 src_x, src_y, src_w, src_h); 946 if (right_hwpipe) 947 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, 948 config, hdecm, vdecm, hflip, vflip, 949 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h, 950 src_img_w, src_img_h, 951 src_x + src_w, src_y, src_w, src_h); 952 953 return ret; 954 } 955 956 /* 957 * Use this func and the one below only after the atomic state has been 958 * successfully swapped 959 */ 960 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) 961 { 962 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 963 964 if (WARN_ON(!pstate->hwpipe)) 965 return SSPP_NONE; 966 967 return pstate->hwpipe->pipe; 968 } 969 970 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane) 971 { 972 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 973 974 if (!pstate->r_hwpipe) 975 return SSPP_NONE; 976 977 return pstate->r_hwpipe->pipe; 978 } 979 980 uint32_t mdp5_plane_get_flush(struct drm_plane *plane) 981 { 982 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 983 u32 mask; 984 985 if (WARN_ON(!pstate->hwpipe)) 986 return 0; 987 988 mask = pstate->hwpipe->flush_mask; 989 990 if (pstate->r_hwpipe) 991 mask |= pstate->r_hwpipe->flush_mask; 992 993 return mask; 994 } 995 996 /* initialize plane */ 997 struct drm_plane *mdp5_plane_init(struct drm_device *dev, 998 enum drm_plane_type type) 999 { 1000 struct drm_plane *plane = NULL; 1001 struct mdp5_plane *mdp5_plane; 1002 int ret; 1003 1004 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL); 1005 if (!mdp5_plane) { 1006 ret = -ENOMEM; 1007 goto fail; 1008 } 1009 1010 plane = &mdp5_plane->base; 1011 1012 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats, 1013 ARRAY_SIZE(mdp5_plane->formats), false); 1014 1015 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs, 1016 mdp5_plane->formats, mdp5_plane->nformats, 1017 NULL, type, NULL); 1018 if (ret) 1019 goto fail; 1020 1021 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs); 1022 1023 mdp5_plane_install_properties(plane, &plane->base); 1024 1025 drm_plane_enable_fb_damage_clips(plane); 1026 1027 return plane; 1028 1029 fail: 1030 if (plane) 1031 mdp5_plane_destroy(plane); 1032 1033 return ERR_PTR(ret); 1034 } 1035