1 /* 2 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <drm/drm_print.h> 20 #include "mdp5_kms.h" 21 22 struct mdp5_plane { 23 struct drm_plane base; 24 25 uint32_t nformats; 26 uint32_t formats[32]; 27 }; 28 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) 29 30 static int mdp5_plane_mode_set(struct drm_plane *plane, 31 struct drm_crtc *crtc, struct drm_framebuffer *fb, 32 struct drm_rect *src, struct drm_rect *dest); 33 34 static struct mdp5_kms *get_kms(struct drm_plane *plane) 35 { 36 struct msm_drm_private *priv = plane->dev->dev_private; 37 return to_mdp5_kms(to_mdp_kms(priv->kms)); 38 } 39 40 static bool plane_enabled(struct drm_plane_state *state) 41 { 42 return state->visible; 43 } 44 45 static void mdp5_plane_destroy(struct drm_plane *plane) 46 { 47 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); 48 49 drm_plane_helper_disable(plane, NULL); 50 drm_plane_cleanup(plane); 51 52 kfree(mdp5_plane); 53 } 54 55 static void mdp5_plane_install_rotation_property(struct drm_device *dev, 56 struct drm_plane *plane) 57 { 58 drm_plane_create_rotation_property(plane, 59 DRM_MODE_ROTATE_0, 60 DRM_MODE_ROTATE_0 | 61 DRM_MODE_ROTATE_180 | 62 DRM_MODE_REFLECT_X | 63 DRM_MODE_REFLECT_Y); 64 } 65 66 /* helper to install properties which are common to planes and crtcs */ 67 static void mdp5_plane_install_properties(struct drm_plane *plane, 68 struct drm_mode_object *obj) 69 { 70 struct drm_device *dev = plane->dev; 71 struct msm_drm_private *dev_priv = dev->dev_private; 72 struct drm_property *prop; 73 74 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \ 75 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \ 76 if (!prop) { \ 77 prop = drm_property_##fnc(dev, 0, #name, \ 78 ##__VA_ARGS__); \ 79 if (!prop) { \ 80 dev_warn(dev->dev, \ 81 "Create property %s failed\n", \ 82 #name); \ 83 return; \ 84 } \ 85 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \ 86 } \ 87 drm_object_attach_property(&plane->base, prop, init_val); \ 88 } while (0) 89 90 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \ 91 INSTALL_PROPERTY(name, NAME, init_val, \ 92 create_range, min, max) 93 94 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \ 95 INSTALL_PROPERTY(name, NAME, init_val, \ 96 create_enum, name##_prop_enum_list, \ 97 ARRAY_SIZE(name##_prop_enum_list)) 98 99 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1); 100 101 mdp5_plane_install_rotation_property(dev, plane); 102 103 #undef INSTALL_RANGE_PROPERTY 104 #undef INSTALL_ENUM_PROPERTY 105 #undef INSTALL_PROPERTY 106 } 107 108 static int mdp5_plane_atomic_set_property(struct drm_plane *plane, 109 struct drm_plane_state *state, struct drm_property *property, 110 uint64_t val) 111 { 112 struct drm_device *dev = plane->dev; 113 struct mdp5_plane_state *pstate; 114 struct msm_drm_private *dev_priv = dev->dev_private; 115 int ret = 0; 116 117 pstate = to_mdp5_plane_state(state); 118 119 #define SET_PROPERTY(name, NAME, type) do { \ 120 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ 121 pstate->name = (type)val; \ 122 DBG("Set property %s %d", #name, (type)val); \ 123 goto done; \ 124 } \ 125 } while (0) 126 127 SET_PROPERTY(zpos, ZPOS, uint8_t); 128 129 dev_err(dev->dev, "Invalid property\n"); 130 ret = -EINVAL; 131 done: 132 return ret; 133 #undef SET_PROPERTY 134 } 135 136 static int mdp5_plane_atomic_get_property(struct drm_plane *plane, 137 const struct drm_plane_state *state, 138 struct drm_property *property, uint64_t *val) 139 { 140 struct drm_device *dev = plane->dev; 141 struct mdp5_plane_state *pstate; 142 struct msm_drm_private *dev_priv = dev->dev_private; 143 int ret = 0; 144 145 pstate = to_mdp5_plane_state(state); 146 147 #define GET_PROPERTY(name, NAME, type) do { \ 148 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ 149 *val = pstate->name; \ 150 DBG("Get property %s %lld", #name, *val); \ 151 goto done; \ 152 } \ 153 } while (0) 154 155 GET_PROPERTY(zpos, ZPOS, uint8_t); 156 157 dev_err(dev->dev, "Invalid property\n"); 158 ret = -EINVAL; 159 done: 160 return ret; 161 #undef SET_PROPERTY 162 } 163 164 static void 165 mdp5_plane_atomic_print_state(struct drm_printer *p, 166 const struct drm_plane_state *state) 167 { 168 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 169 struct mdp5_kms *mdp5_kms = get_kms(state->plane); 170 171 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? 172 pstate->hwpipe->name : "(null)"); 173 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) 174 drm_printf(p, "\tright-hwpipe=%s\n", 175 pstate->r_hwpipe ? pstate->r_hwpipe->name : 176 "(null)"); 177 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied); 178 drm_printf(p, "\tzpos=%u\n", pstate->zpos); 179 drm_printf(p, "\talpha=%u\n", pstate->alpha); 180 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); 181 } 182 183 static void mdp5_plane_reset(struct drm_plane *plane) 184 { 185 struct mdp5_plane_state *mdp5_state; 186 187 if (plane->state && plane->state->fb) 188 drm_framebuffer_unreference(plane->state->fb); 189 190 kfree(to_mdp5_plane_state(plane->state)); 191 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); 192 193 /* assign default blend parameters */ 194 mdp5_state->alpha = 255; 195 mdp5_state->premultiplied = 0; 196 197 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 198 mdp5_state->zpos = STAGE_BASE; 199 else 200 mdp5_state->zpos = STAGE0 + drm_plane_index(plane); 201 202 mdp5_state->base.plane = plane; 203 204 plane->state = &mdp5_state->base; 205 } 206 207 static struct drm_plane_state * 208 mdp5_plane_duplicate_state(struct drm_plane *plane) 209 { 210 struct mdp5_plane_state *mdp5_state; 211 212 if (WARN_ON(!plane->state)) 213 return NULL; 214 215 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state), 216 sizeof(*mdp5_state), GFP_KERNEL); 217 if (!mdp5_state) 218 return NULL; 219 220 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); 221 222 return &mdp5_state->base; 223 } 224 225 static void mdp5_plane_destroy_state(struct drm_plane *plane, 226 struct drm_plane_state *state) 227 { 228 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 229 230 if (state->fb) 231 drm_framebuffer_unreference(state->fb); 232 233 kfree(pstate); 234 } 235 236 static const struct drm_plane_funcs mdp5_plane_funcs = { 237 .update_plane = drm_atomic_helper_update_plane, 238 .disable_plane = drm_atomic_helper_disable_plane, 239 .destroy = mdp5_plane_destroy, 240 .atomic_set_property = mdp5_plane_atomic_set_property, 241 .atomic_get_property = mdp5_plane_atomic_get_property, 242 .reset = mdp5_plane_reset, 243 .atomic_duplicate_state = mdp5_plane_duplicate_state, 244 .atomic_destroy_state = mdp5_plane_destroy_state, 245 .atomic_print_state = mdp5_plane_atomic_print_state, 246 }; 247 248 static void mdp5_plane_cleanup_fb(struct drm_plane *plane, 249 struct drm_plane_state *old_state) 250 { 251 struct mdp5_kms *mdp5_kms = get_kms(plane); 252 struct msm_kms *kms = &mdp5_kms->base.base; 253 struct drm_framebuffer *fb = old_state->fb; 254 255 if (!fb) 256 return; 257 258 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); 259 msm_framebuffer_cleanup(fb, kms->aspace); 260 } 261 262 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 263 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, 264 struct drm_plane_state *state) 265 { 266 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 267 struct drm_plane *plane = state->plane; 268 struct drm_plane_state *old_state = plane->state; 269 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg); 270 bool new_hwpipe = false; 271 bool need_right_hwpipe = false; 272 uint32_t max_width, max_height; 273 bool out_of_bounds = false; 274 uint32_t caps = 0; 275 int min_scale, max_scale; 276 int ret; 277 278 DBG("%s: check (%d -> %d)", plane->name, 279 plane_enabled(old_state), plane_enabled(state)); 280 281 max_width = config->hw->lm.max_width << 16; 282 max_height = config->hw->lm.max_height << 16; 283 284 /* Make sure source dimensions are within bounds. */ 285 if (state->src_h > max_height) 286 out_of_bounds = true; 287 288 if (state->src_w > max_width) { 289 /* If source split is supported, we can go up to 2x 290 * the max LM width, but we'd need to stage another 291 * hwpipe to the right LM. So, the drm_plane would 292 * consist of 2 hwpipes. 293 */ 294 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT && 295 (state->src_w <= 2 * max_width)) 296 need_right_hwpipe = true; 297 else 298 out_of_bounds = true; 299 } 300 301 if (out_of_bounds) { 302 struct drm_rect src = drm_plane_state_src(state); 303 DBG("Invalid source size "DRM_RECT_FP_FMT, 304 DRM_RECT_FP_ARG(&src)); 305 return -ERANGE; 306 } 307 308 min_scale = FRAC_16_16(1, 8); 309 max_scale = FRAC_16_16(8, 1); 310 311 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 312 min_scale, max_scale, 313 true, true); 314 if (ret) 315 return ret; 316 317 if (plane_enabled(state)) { 318 unsigned int rotation; 319 const struct mdp_format *format; 320 struct mdp5_kms *mdp5_kms = get_kms(plane); 321 uint32_t blkcfg = 0; 322 323 format = to_mdp_format(msm_framebuffer_format(state->fb)); 324 if (MDP_FORMAT_IS_YUV(format)) 325 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC; 326 327 if (((state->src_w >> 16) != state->crtc_w) || 328 ((state->src_h >> 16) != state->crtc_h)) 329 caps |= MDP_PIPE_CAP_SCALE; 330 331 rotation = drm_rotation_simplify(state->rotation, 332 DRM_MODE_ROTATE_0 | 333 DRM_MODE_REFLECT_X | 334 DRM_MODE_REFLECT_Y); 335 336 if (rotation & DRM_MODE_REFLECT_X) 337 caps |= MDP_PIPE_CAP_HFLIP; 338 339 if (rotation & DRM_MODE_REFLECT_Y) 340 caps |= MDP_PIPE_CAP_VFLIP; 341 342 if (plane->type == DRM_PLANE_TYPE_CURSOR) 343 caps |= MDP_PIPE_CAP_CURSOR; 344 345 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */ 346 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps)) 347 new_hwpipe = true; 348 349 /* 350 * (re)allocte hw pipe if we're either requesting for 2 hw pipes 351 * or we're switching from 2 hw pipes to 1 hw pipe because the 352 * new src_w can be supported by 1 hw pipe itself. 353 */ 354 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) || 355 (!need_right_hwpipe && mdp5_state->r_hwpipe)) 356 new_hwpipe = true; 357 358 if (mdp5_kms->smp) { 359 const struct mdp_format *format = 360 to_mdp_format(msm_framebuffer_format(state->fb)); 361 362 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, 363 state->src_w >> 16, false); 364 365 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg)) 366 new_hwpipe = true; 367 } 368 369 /* (re)assign hwpipe if needed, otherwise keep old one: */ 370 if (new_hwpipe) { 371 /* TODO maybe we want to re-assign hwpipe sometimes 372 * in cases when we no-longer need some caps to make 373 * it available for other planes? 374 */ 375 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe; 376 struct mdp5_hw_pipe *old_right_hwpipe = 377 mdp5_state->r_hwpipe; 378 struct mdp5_hw_pipe *new_hwpipe = NULL; 379 struct mdp5_hw_pipe *new_right_hwpipe = NULL; 380 381 ret = mdp5_pipe_assign(state->state, plane, caps, 382 blkcfg, &new_hwpipe, 383 need_right_hwpipe ? 384 &new_right_hwpipe : NULL); 385 if (ret) { 386 DBG("%s: failed to assign hwpipe(s)!", 387 plane->name); 388 return ret; 389 } 390 391 mdp5_state->hwpipe = new_hwpipe; 392 if (need_right_hwpipe) 393 mdp5_state->r_hwpipe = new_right_hwpipe; 394 else 395 /* 396 * set it to NULL so that the driver knows we 397 * don't have a right hwpipe when committing a 398 * new state 399 */ 400 mdp5_state->r_hwpipe = NULL; 401 402 403 mdp5_pipe_release(state->state, old_hwpipe); 404 mdp5_pipe_release(state->state, old_right_hwpipe); 405 } 406 } else { 407 mdp5_pipe_release(state->state, mdp5_state->hwpipe); 408 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe); 409 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL; 410 } 411 412 return 0; 413 } 414 415 static int mdp5_plane_atomic_check(struct drm_plane *plane, 416 struct drm_plane_state *state) 417 { 418 struct drm_crtc *crtc; 419 struct drm_crtc_state *crtc_state; 420 421 crtc = state->crtc ? state->crtc : plane->state->crtc; 422 if (!crtc) 423 return 0; 424 425 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 426 if (WARN_ON(!crtc_state)) 427 return -EINVAL; 428 429 return mdp5_plane_atomic_check_with_state(crtc_state, state); 430 } 431 432 static void mdp5_plane_atomic_update(struct drm_plane *plane, 433 struct drm_plane_state *old_state) 434 { 435 struct drm_plane_state *state = plane->state; 436 437 DBG("%s: update", plane->name); 438 439 if (plane_enabled(state)) { 440 int ret; 441 442 ret = mdp5_plane_mode_set(plane, 443 state->crtc, state->fb, 444 &state->src, &state->dst); 445 /* atomic_check should have ensured that this doesn't fail */ 446 WARN_ON(ret < 0); 447 } 448 } 449 450 static int mdp5_plane_atomic_async_check(struct drm_plane *plane, 451 struct drm_plane_state *state) 452 { 453 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 454 struct drm_crtc_state *crtc_state; 455 int min_scale, max_scale; 456 int ret; 457 458 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 459 state->crtc); 460 if (WARN_ON(!crtc_state)) 461 return -EINVAL; 462 463 if (!crtc_state->active) 464 return -EINVAL; 465 466 mdp5_state = to_mdp5_plane_state(state); 467 468 /* don't use fast path if we don't have a hwpipe allocated yet */ 469 if (!mdp5_state->hwpipe) 470 return -EINVAL; 471 472 /* only allow changing of position(crtc x/y or src x/y) in fast path */ 473 if (plane->state->crtc != state->crtc || 474 plane->state->src_w != state->src_w || 475 plane->state->src_h != state->src_h || 476 plane->state->crtc_w != state->crtc_w || 477 plane->state->crtc_h != state->crtc_h || 478 !plane->state->fb || 479 plane->state->fb != state->fb) 480 return -EINVAL; 481 482 min_scale = FRAC_16_16(1, 8); 483 max_scale = FRAC_16_16(8, 1); 484 485 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 486 min_scale, max_scale, 487 true, true); 488 if (ret) 489 return ret; 490 491 /* 492 * if the visibility of the plane changes (i.e, if the cursor is 493 * clipped out completely, we can't take the async path because 494 * we need to stage/unstage the plane from the Layer Mixer(s). We 495 * also assign/unassign the hwpipe(s) tied to the plane. We avoid 496 * taking the fast path for both these reasons. 497 */ 498 if (state->visible != plane->state->visible) 499 return -EINVAL; 500 501 return 0; 502 } 503 504 static void mdp5_plane_atomic_async_update(struct drm_plane *plane, 505 struct drm_plane_state *new_state) 506 { 507 plane->state->src_x = new_state->src_x; 508 plane->state->src_y = new_state->src_y; 509 plane->state->crtc_x = new_state->crtc_x; 510 plane->state->crtc_y = new_state->crtc_y; 511 512 if (plane_enabled(new_state)) { 513 struct mdp5_ctl *ctl; 514 struct mdp5_pipeline *pipeline = 515 mdp5_crtc_get_pipeline(new_state->crtc); 516 int ret; 517 518 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb, 519 &new_state->src, &new_state->dst); 520 WARN_ON(ret < 0); 521 522 ctl = mdp5_crtc_get_ctl(new_state->crtc); 523 524 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true); 525 } 526 527 *to_mdp5_plane_state(plane->state) = 528 *to_mdp5_plane_state(new_state); 529 } 530 531 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { 532 .prepare_fb = msm_atomic_prepare_fb, 533 .cleanup_fb = mdp5_plane_cleanup_fb, 534 .atomic_check = mdp5_plane_atomic_check, 535 .atomic_update = mdp5_plane_atomic_update, 536 .atomic_async_check = mdp5_plane_atomic_async_check, 537 .atomic_async_update = mdp5_plane_atomic_async_update, 538 }; 539 540 static void set_scanout_locked(struct mdp5_kms *mdp5_kms, 541 enum mdp5_pipe pipe, 542 struct drm_framebuffer *fb) 543 { 544 struct msm_kms *kms = &mdp5_kms->base.base; 545 546 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), 547 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | 548 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1])); 549 550 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), 551 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) | 552 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); 553 554 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), 555 msm_framebuffer_iova(fb, kms->aspace, 0)); 556 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), 557 msm_framebuffer_iova(fb, kms->aspace, 1)); 558 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), 559 msm_framebuffer_iova(fb, kms->aspace, 2)); 560 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), 561 msm_framebuffer_iova(fb, kms->aspace, 3)); 562 } 563 564 /* Note: mdp5_plane->pipe_lock must be locked */ 565 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) 566 { 567 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & 568 ~MDP5_PIPE_OP_MODE_CSC_1_EN; 569 570 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); 571 } 572 573 /* Note: mdp5_plane->pipe_lock must be locked */ 574 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 575 struct csc_cfg *csc) 576 { 577 uint32_t i, mode = 0; /* RGB, no CSC */ 578 uint32_t *matrix; 579 580 if (unlikely(!csc)) 581 return; 582 583 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) 584 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV); 585 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) 586 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); 587 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN; 588 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); 589 590 matrix = csc->matrix; 591 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), 592 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) | 593 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1])); 594 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), 595 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) | 596 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3])); 597 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), 598 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) | 599 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5])); 600 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), 601 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) | 602 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7])); 603 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), 604 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8])); 605 606 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { 607 uint32_t *pre_clamp = csc->pre_clamp; 608 uint32_t *post_clamp = csc->post_clamp; 609 610 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), 611 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) | 612 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i])); 613 614 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), 615 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) | 616 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i])); 617 618 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), 619 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); 620 621 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), 622 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); 623 } 624 } 625 626 #define PHASE_STEP_SHIFT 21 627 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */ 628 629 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) 630 { 631 uint32_t unit; 632 633 if (src == 0 || dst == 0) 634 return -EINVAL; 635 636 /* 637 * PHASE_STEP_X/Y is coded on 26 bits (25:0), 638 * where 2^21 represents the unity "1" in fixed-point hardware design. 639 * This leaves 5 bits for the integer part (downscale case): 640 * -> maximum downscale ratio = 0b1_1111 = 31 641 */ 642 if (src > (dst * DOWN_SCALE_RATIO_MAX)) 643 return -EOVERFLOW; 644 645 unit = 1 << PHASE_STEP_SHIFT; 646 *out_phase = mult_frac(unit, src, dst); 647 648 return 0; 649 } 650 651 static int calc_scalex_steps(struct drm_plane *plane, 652 uint32_t pixel_format, uint32_t src, uint32_t dest, 653 uint32_t phasex_steps[COMP_MAX]) 654 { 655 struct mdp5_kms *mdp5_kms = get_kms(plane); 656 struct device *dev = mdp5_kms->dev->dev; 657 uint32_t phasex_step; 658 unsigned int hsub; 659 int ret; 660 661 ret = calc_phase_step(src, dest, &phasex_step); 662 if (ret) { 663 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); 664 return ret; 665 } 666 667 hsub = drm_format_horz_chroma_subsampling(pixel_format); 668 669 phasex_steps[COMP_0] = phasex_step; 670 phasex_steps[COMP_3] = phasex_step; 671 phasex_steps[COMP_1_2] = phasex_step / hsub; 672 673 return 0; 674 } 675 676 static int calc_scaley_steps(struct drm_plane *plane, 677 uint32_t pixel_format, uint32_t src, uint32_t dest, 678 uint32_t phasey_steps[COMP_MAX]) 679 { 680 struct mdp5_kms *mdp5_kms = get_kms(plane); 681 struct device *dev = mdp5_kms->dev->dev; 682 uint32_t phasey_step; 683 unsigned int vsub; 684 int ret; 685 686 ret = calc_phase_step(src, dest, &phasey_step); 687 if (ret) { 688 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); 689 return ret; 690 } 691 692 vsub = drm_format_vert_chroma_subsampling(pixel_format); 693 694 phasey_steps[COMP_0] = phasey_step; 695 phasey_steps[COMP_3] = phasey_step; 696 phasey_steps[COMP_1_2] = phasey_step / vsub; 697 698 return 0; 699 } 700 701 static uint32_t get_scale_config(const struct mdp_format *format, 702 uint32_t src, uint32_t dst, bool horz) 703 { 704 bool scaling = format->is_yuv ? true : (src != dst); 705 uint32_t sub, pix_fmt = format->base.pixel_format; 706 uint32_t ya_filter, uv_filter; 707 bool yuv = format->is_yuv; 708 709 if (!scaling) 710 return 0; 711 712 if (yuv) { 713 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) : 714 drm_format_vert_chroma_subsampling(pix_fmt); 715 uv_filter = ((src / sub) <= dst) ? 716 SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 717 } 718 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 719 720 if (horz) 721 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | 722 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | 723 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | 724 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); 725 else 726 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | 727 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | 728 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | 729 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); 730 } 731 732 static void calc_pixel_ext(const struct mdp_format *format, 733 uint32_t src, uint32_t dst, uint32_t phase_step[2], 734 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], 735 bool horz) 736 { 737 bool scaling = format->is_yuv ? true : (src != dst); 738 int i; 739 740 /* 741 * Note: 742 * We assume here that: 743 * 1. PCMN filter is used for downscale 744 * 2. bilinear filter is used for upscale 745 * 3. we are in a single pipe configuration 746 */ 747 748 for (i = 0; i < COMP_MAX; i++) { 749 pix_ext_edge1[i] = 0; 750 pix_ext_edge2[i] = scaling ? 1 : 0; 751 } 752 } 753 754 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 755 const struct mdp_format *format, 756 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], 757 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) 758 { 759 uint32_t pix_fmt = format->base.pixel_format; 760 uint32_t lr, tb, req; 761 int i; 762 763 for (i = 0; i < COMP_MAX; i++) { 764 uint32_t roi_w = src_w; 765 uint32_t roi_h = src_h; 766 767 if (format->is_yuv && i == COMP_1_2) { 768 roi_w /= drm_format_horz_chroma_subsampling(pix_fmt); 769 roi_h /= drm_format_vert_chroma_subsampling(pix_fmt); 770 } 771 772 lr = (pe_left[i] >= 0) ? 773 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : 774 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); 775 776 lr |= (pe_right[i] >= 0) ? 777 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : 778 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); 779 780 tb = (pe_top[i] >= 0) ? 781 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : 782 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); 783 784 tb |= (pe_bottom[i] >= 0) ? 785 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : 786 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); 787 788 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + 789 pe_left[i] + pe_right[i]); 790 791 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + 792 pe_top[i] + pe_bottom[i]); 793 794 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); 795 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); 796 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); 797 798 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, 799 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), 800 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), 801 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), 802 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), 803 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); 804 805 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, 806 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), 807 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), 808 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), 809 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), 810 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); 811 } 812 } 813 814 struct pixel_ext { 815 int left[COMP_MAX]; 816 int right[COMP_MAX]; 817 int top[COMP_MAX]; 818 int bottom[COMP_MAX]; 819 }; 820 821 struct phase_step { 822 u32 x[COMP_MAX]; 823 u32 y[COMP_MAX]; 824 }; 825 826 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms, 827 struct mdp5_hw_pipe *hwpipe, 828 struct drm_framebuffer *fb, 829 struct phase_step *step, 830 struct pixel_ext *pe, 831 u32 scale_config, u32 hdecm, u32 vdecm, 832 bool hflip, bool vflip, 833 int crtc_x, int crtc_y, 834 unsigned int crtc_w, unsigned int crtc_h, 835 u32 src_img_w, u32 src_img_h, 836 u32 src_x, u32 src_y, 837 u32 src_w, u32 src_h) 838 { 839 enum mdp5_pipe pipe = hwpipe->pipe; 840 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT; 841 const struct mdp_format *format = 842 to_mdp_format(msm_framebuffer_format(fb)); 843 844 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), 845 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) | 846 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h)); 847 848 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), 849 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | 850 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); 851 852 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), 853 MDP5_PIPE_SRC_XY_X(src_x) | 854 MDP5_PIPE_SRC_XY_Y(src_y)); 855 856 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), 857 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | 858 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); 859 860 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), 861 MDP5_PIPE_OUT_XY_X(crtc_x) | 862 MDP5_PIPE_OUT_XY_Y(crtc_y)); 863 864 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), 865 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) | 866 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) | 867 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) | 868 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) | 869 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) | 870 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) | 871 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | 872 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) | 873 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) | 874 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample)); 875 876 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), 877 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) | 878 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) | 879 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) | 880 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3])); 881 882 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), 883 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | 884 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | 885 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | 886 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); 887 888 /* not using secure mode: */ 889 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); 890 891 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) 892 mdp5_write_pixel_ext(mdp5_kms, pipe, format, 893 src_w, pe->left, pe->right, 894 src_h, pe->top, pe->bottom); 895 896 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) { 897 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), 898 step->x[COMP_0]); 899 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), 900 step->y[COMP_0]); 901 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), 902 step->x[COMP_1_2]); 903 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), 904 step->y[COMP_1_2]); 905 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), 906 MDP5_PIPE_DECIMATION_VERT(vdecm) | 907 MDP5_PIPE_DECIMATION_HORZ(hdecm)); 908 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), 909 scale_config); 910 } 911 912 if (hwpipe->caps & MDP_PIPE_CAP_CSC) { 913 if (MDP_FORMAT_IS_YUV(format)) 914 csc_enable(mdp5_kms, pipe, 915 mdp_get_default_csc_cfg(CSC_YUV2RGB)); 916 else 917 csc_disable(mdp5_kms, pipe); 918 } 919 920 set_scanout_locked(mdp5_kms, pipe, fb); 921 } 922 923 static int mdp5_plane_mode_set(struct drm_plane *plane, 924 struct drm_crtc *crtc, struct drm_framebuffer *fb, 925 struct drm_rect *src, struct drm_rect *dest) 926 { 927 struct drm_plane_state *pstate = plane->state; 928 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; 929 struct mdp5_kms *mdp5_kms = get_kms(plane); 930 enum mdp5_pipe pipe = hwpipe->pipe; 931 struct mdp5_hw_pipe *right_hwpipe; 932 const struct mdp_format *format; 933 uint32_t nplanes, config = 0; 934 struct phase_step step = { { 0 } }; 935 struct pixel_ext pe = { { 0 } }; 936 uint32_t hdecm = 0, vdecm = 0; 937 uint32_t pix_format; 938 unsigned int rotation; 939 bool vflip, hflip; 940 int crtc_x, crtc_y; 941 unsigned int crtc_w, crtc_h; 942 uint32_t src_x, src_y; 943 uint32_t src_w, src_h; 944 uint32_t src_img_w, src_img_h; 945 int ret; 946 947 nplanes = fb->format->num_planes; 948 949 /* bad formats should already be rejected: */ 950 if (WARN_ON(nplanes > pipe2nclients(pipe))) 951 return -EINVAL; 952 953 format = to_mdp_format(msm_framebuffer_format(fb)); 954 pix_format = format->base.pixel_format; 955 956 src_x = src->x1; 957 src_y = src->y1; 958 src_w = drm_rect_width(src); 959 src_h = drm_rect_height(src); 960 961 crtc_x = dest->x1; 962 crtc_y = dest->y1; 963 crtc_w = drm_rect_width(dest); 964 crtc_h = drm_rect_height(dest); 965 966 /* src values are in Q16 fixed point, convert to integer: */ 967 src_x = src_x >> 16; 968 src_y = src_y >> 16; 969 src_w = src_w >> 16; 970 src_h = src_h >> 16; 971 972 src_img_w = min(fb->width, src_w); 973 src_img_h = min(fb->height, src_h); 974 975 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name, 976 fb->base.id, src_x, src_y, src_w, src_h, 977 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); 978 979 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe; 980 if (right_hwpipe) { 981 /* 982 * if the plane comprises of 2 hw pipes, assume that the width 983 * is split equally across them. The only parameters that varies 984 * between the 2 pipes are src_x and crtc_x 985 */ 986 crtc_w /= 2; 987 src_w /= 2; 988 src_img_w /= 2; 989 } 990 991 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); 992 if (ret) 993 return ret; 994 995 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y); 996 if (ret) 997 return ret; 998 999 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) { 1000 calc_pixel_ext(format, src_w, crtc_w, step.x, 1001 pe.left, pe.right, true); 1002 calc_pixel_ext(format, src_h, crtc_h, step.y, 1003 pe.top, pe.bottom, false); 1004 } 1005 1006 /* TODO calc hdecm, vdecm */ 1007 1008 /* SCALE is used to both scale and up-sample chroma components */ 1009 config |= get_scale_config(format, src_w, crtc_w, true); 1010 config |= get_scale_config(format, src_h, crtc_h, false); 1011 DBG("scale config = %x", config); 1012 1013 rotation = drm_rotation_simplify(pstate->rotation, 1014 DRM_MODE_ROTATE_0 | 1015 DRM_MODE_REFLECT_X | 1016 DRM_MODE_REFLECT_Y); 1017 hflip = !!(rotation & DRM_MODE_REFLECT_X); 1018 vflip = !!(rotation & DRM_MODE_REFLECT_Y); 1019 1020 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe, 1021 config, hdecm, vdecm, hflip, vflip, 1022 crtc_x, crtc_y, crtc_w, crtc_h, 1023 src_img_w, src_img_h, 1024 src_x, src_y, src_w, src_h); 1025 if (right_hwpipe) 1026 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, 1027 config, hdecm, vdecm, hflip, vflip, 1028 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h, 1029 src_img_w, src_img_h, 1030 src_x + src_w, src_y, src_w, src_h); 1031 1032 return ret; 1033 } 1034 1035 /* 1036 * Use this func and the one below only after the atomic state has been 1037 * successfully swapped 1038 */ 1039 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) 1040 { 1041 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1042 1043 if (WARN_ON(!pstate->hwpipe)) 1044 return SSPP_NONE; 1045 1046 return pstate->hwpipe->pipe; 1047 } 1048 1049 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane) 1050 { 1051 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1052 1053 if (!pstate->r_hwpipe) 1054 return SSPP_NONE; 1055 1056 return pstate->r_hwpipe->pipe; 1057 } 1058 1059 uint32_t mdp5_plane_get_flush(struct drm_plane *plane) 1060 { 1061 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1062 u32 mask; 1063 1064 if (WARN_ON(!pstate->hwpipe)) 1065 return 0; 1066 1067 mask = pstate->hwpipe->flush_mask; 1068 1069 if (pstate->r_hwpipe) 1070 mask |= pstate->r_hwpipe->flush_mask; 1071 1072 return mask; 1073 } 1074 1075 /* initialize plane */ 1076 struct drm_plane *mdp5_plane_init(struct drm_device *dev, 1077 enum drm_plane_type type) 1078 { 1079 struct drm_plane *plane = NULL; 1080 struct mdp5_plane *mdp5_plane; 1081 int ret; 1082 1083 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL); 1084 if (!mdp5_plane) { 1085 ret = -ENOMEM; 1086 goto fail; 1087 } 1088 1089 plane = &mdp5_plane->base; 1090 1091 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats, 1092 ARRAY_SIZE(mdp5_plane->formats), false); 1093 1094 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs, 1095 mdp5_plane->formats, mdp5_plane->nformats, 1096 NULL, type, NULL); 1097 if (ret) 1098 goto fail; 1099 1100 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs); 1101 1102 mdp5_plane_install_properties(plane, &plane->base); 1103 1104 return plane; 1105 1106 fail: 1107 if (plane) 1108 mdp5_plane_destroy(plane); 1109 1110 return ERR_PTR(ret); 1111 } 1112