1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <drm/drm_damage_helper.h> 9 #include <drm/drm_print.h> 10 #include "mdp5_kms.h" 11 12 struct mdp5_plane { 13 struct drm_plane base; 14 15 uint32_t nformats; 16 uint32_t formats[32]; 17 }; 18 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) 19 20 static int mdp5_plane_mode_set(struct drm_plane *plane, 21 struct drm_crtc *crtc, struct drm_framebuffer *fb, 22 struct drm_rect *src, struct drm_rect *dest); 23 24 static struct mdp5_kms *get_kms(struct drm_plane *plane) 25 { 26 struct msm_drm_private *priv = plane->dev->dev_private; 27 return to_mdp5_kms(to_mdp_kms(priv->kms)); 28 } 29 30 static bool plane_enabled(struct drm_plane_state *state) 31 { 32 return state->visible; 33 } 34 35 static void mdp5_plane_destroy(struct drm_plane *plane) 36 { 37 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); 38 39 drm_plane_cleanup(plane); 40 41 kfree(mdp5_plane); 42 } 43 44 static void mdp5_plane_install_rotation_property(struct drm_device *dev, 45 struct drm_plane *plane) 46 { 47 drm_plane_create_rotation_property(plane, 48 DRM_MODE_ROTATE_0, 49 DRM_MODE_ROTATE_0 | 50 DRM_MODE_ROTATE_180 | 51 DRM_MODE_REFLECT_X | 52 DRM_MODE_REFLECT_Y); 53 } 54 55 /* helper to install properties which are common to planes and crtcs */ 56 static void mdp5_plane_install_properties(struct drm_plane *plane, 57 struct drm_mode_object *obj) 58 { 59 struct drm_device *dev = plane->dev; 60 struct msm_drm_private *dev_priv = dev->dev_private; 61 struct drm_property *prop; 62 63 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \ 64 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \ 65 if (!prop) { \ 66 prop = drm_property_##fnc(dev, 0, #name, \ 67 ##__VA_ARGS__); \ 68 if (!prop) { \ 69 dev_warn(dev->dev, \ 70 "Create property %s failed\n", \ 71 #name); \ 72 return; \ 73 } \ 74 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \ 75 } \ 76 drm_object_attach_property(&plane->base, prop, init_val); \ 77 } while (0) 78 79 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \ 80 INSTALL_PROPERTY(name, NAME, init_val, \ 81 create_range, min, max) 82 83 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \ 84 INSTALL_PROPERTY(name, NAME, init_val, \ 85 create_enum, name##_prop_enum_list, \ 86 ARRAY_SIZE(name##_prop_enum_list)) 87 88 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1); 89 90 mdp5_plane_install_rotation_property(dev, plane); 91 92 #undef INSTALL_RANGE_PROPERTY 93 #undef INSTALL_ENUM_PROPERTY 94 #undef INSTALL_PROPERTY 95 } 96 97 static int mdp5_plane_atomic_set_property(struct drm_plane *plane, 98 struct drm_plane_state *state, struct drm_property *property, 99 uint64_t val) 100 { 101 struct drm_device *dev = plane->dev; 102 struct mdp5_plane_state *pstate; 103 struct msm_drm_private *dev_priv = dev->dev_private; 104 int ret = 0; 105 106 pstate = to_mdp5_plane_state(state); 107 108 #define SET_PROPERTY(name, NAME, type) do { \ 109 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ 110 pstate->name = (type)val; \ 111 DBG("Set property %s %d", #name, (type)val); \ 112 goto done; \ 113 } \ 114 } while (0) 115 116 SET_PROPERTY(zpos, ZPOS, uint8_t); 117 118 DRM_DEV_ERROR(dev->dev, "Invalid property\n"); 119 ret = -EINVAL; 120 done: 121 return ret; 122 #undef SET_PROPERTY 123 } 124 125 static int mdp5_plane_atomic_get_property(struct drm_plane *plane, 126 const struct drm_plane_state *state, 127 struct drm_property *property, uint64_t *val) 128 { 129 struct drm_device *dev = plane->dev; 130 struct mdp5_plane_state *pstate; 131 struct msm_drm_private *dev_priv = dev->dev_private; 132 int ret = 0; 133 134 pstate = to_mdp5_plane_state(state); 135 136 #define GET_PROPERTY(name, NAME, type) do { \ 137 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ 138 *val = pstate->name; \ 139 DBG("Get property %s %lld", #name, *val); \ 140 goto done; \ 141 } \ 142 } while (0) 143 144 GET_PROPERTY(zpos, ZPOS, uint8_t); 145 146 DRM_DEV_ERROR(dev->dev, "Invalid property\n"); 147 ret = -EINVAL; 148 done: 149 return ret; 150 #undef SET_PROPERTY 151 } 152 153 static void 154 mdp5_plane_atomic_print_state(struct drm_printer *p, 155 const struct drm_plane_state *state) 156 { 157 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 158 struct mdp5_kms *mdp5_kms = get_kms(state->plane); 159 160 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? 161 pstate->hwpipe->name : "(null)"); 162 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) 163 drm_printf(p, "\tright-hwpipe=%s\n", 164 pstate->r_hwpipe ? pstate->r_hwpipe->name : 165 "(null)"); 166 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied); 167 drm_printf(p, "\tzpos=%u\n", pstate->zpos); 168 drm_printf(p, "\talpha=%u\n", pstate->alpha); 169 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); 170 } 171 172 static void mdp5_plane_reset(struct drm_plane *plane) 173 { 174 struct mdp5_plane_state *mdp5_state; 175 176 if (plane->state && plane->state->fb) 177 drm_framebuffer_put(plane->state->fb); 178 179 kfree(to_mdp5_plane_state(plane->state)); 180 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); 181 182 /* assign default blend parameters */ 183 mdp5_state->alpha = 255; 184 mdp5_state->premultiplied = 0; 185 186 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 187 mdp5_state->zpos = STAGE_BASE; 188 else 189 mdp5_state->zpos = STAGE0 + drm_plane_index(plane); 190 191 mdp5_state->base.plane = plane; 192 193 plane->state = &mdp5_state->base; 194 } 195 196 static struct drm_plane_state * 197 mdp5_plane_duplicate_state(struct drm_plane *plane) 198 { 199 struct mdp5_plane_state *mdp5_state; 200 201 if (WARN_ON(!plane->state)) 202 return NULL; 203 204 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state), 205 sizeof(*mdp5_state), GFP_KERNEL); 206 if (!mdp5_state) 207 return NULL; 208 209 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); 210 211 return &mdp5_state->base; 212 } 213 214 static void mdp5_plane_destroy_state(struct drm_plane *plane, 215 struct drm_plane_state *state) 216 { 217 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 218 219 if (state->fb) 220 drm_framebuffer_put(state->fb); 221 222 kfree(pstate); 223 } 224 225 static const struct drm_plane_funcs mdp5_plane_funcs = { 226 .update_plane = drm_atomic_helper_update_plane, 227 .disable_plane = drm_atomic_helper_disable_plane, 228 .destroy = mdp5_plane_destroy, 229 .atomic_set_property = mdp5_plane_atomic_set_property, 230 .atomic_get_property = mdp5_plane_atomic_get_property, 231 .reset = mdp5_plane_reset, 232 .atomic_duplicate_state = mdp5_plane_duplicate_state, 233 .atomic_destroy_state = mdp5_plane_destroy_state, 234 .atomic_print_state = mdp5_plane_atomic_print_state, 235 }; 236 237 static void mdp5_plane_cleanup_fb(struct drm_plane *plane, 238 struct drm_plane_state *old_state) 239 { 240 struct mdp5_kms *mdp5_kms = get_kms(plane); 241 struct msm_kms *kms = &mdp5_kms->base.base; 242 struct drm_framebuffer *fb = old_state->fb; 243 244 if (!fb) 245 return; 246 247 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); 248 msm_framebuffer_cleanup(fb, kms->aspace); 249 } 250 251 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, 252 struct drm_plane_state *state) 253 { 254 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 255 struct drm_plane *plane = state->plane; 256 struct drm_plane_state *old_state = plane->state; 257 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg); 258 bool new_hwpipe = false; 259 bool need_right_hwpipe = false; 260 uint32_t max_width, max_height; 261 bool out_of_bounds = false; 262 uint32_t caps = 0; 263 int min_scale, max_scale; 264 int ret; 265 266 DBG("%s: check (%d -> %d)", plane->name, 267 plane_enabled(old_state), plane_enabled(state)); 268 269 max_width = config->hw->lm.max_width << 16; 270 max_height = config->hw->lm.max_height << 16; 271 272 /* Make sure source dimensions are within bounds. */ 273 if (state->src_h > max_height) 274 out_of_bounds = true; 275 276 if (state->src_w > max_width) { 277 /* If source split is supported, we can go up to 2x 278 * the max LM width, but we'd need to stage another 279 * hwpipe to the right LM. So, the drm_plane would 280 * consist of 2 hwpipes. 281 */ 282 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT && 283 (state->src_w <= 2 * max_width)) 284 need_right_hwpipe = true; 285 else 286 out_of_bounds = true; 287 } 288 289 if (out_of_bounds) { 290 struct drm_rect src = drm_plane_state_src(state); 291 DBG("Invalid source size "DRM_RECT_FP_FMT, 292 DRM_RECT_FP_ARG(&src)); 293 return -ERANGE; 294 } 295 296 min_scale = FRAC_16_16(1, 8); 297 max_scale = FRAC_16_16(8, 1); 298 299 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 300 min_scale, max_scale, 301 true, true); 302 if (ret) 303 return ret; 304 305 if (plane_enabled(state)) { 306 unsigned int rotation; 307 const struct mdp_format *format; 308 struct mdp5_kms *mdp5_kms = get_kms(plane); 309 uint32_t blkcfg = 0; 310 311 format = to_mdp_format(msm_framebuffer_format(state->fb)); 312 if (MDP_FORMAT_IS_YUV(format)) 313 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC; 314 315 if (((state->src_w >> 16) != state->crtc_w) || 316 ((state->src_h >> 16) != state->crtc_h)) 317 caps |= MDP_PIPE_CAP_SCALE; 318 319 rotation = drm_rotation_simplify(state->rotation, 320 DRM_MODE_ROTATE_0 | 321 DRM_MODE_REFLECT_X | 322 DRM_MODE_REFLECT_Y); 323 324 if (rotation & DRM_MODE_REFLECT_X) 325 caps |= MDP_PIPE_CAP_HFLIP; 326 327 if (rotation & DRM_MODE_REFLECT_Y) 328 caps |= MDP_PIPE_CAP_VFLIP; 329 330 if (plane->type == DRM_PLANE_TYPE_CURSOR) 331 caps |= MDP_PIPE_CAP_CURSOR; 332 333 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */ 334 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps)) 335 new_hwpipe = true; 336 337 /* 338 * (re)allocte hw pipe if we're either requesting for 2 hw pipes 339 * or we're switching from 2 hw pipes to 1 hw pipe because the 340 * new src_w can be supported by 1 hw pipe itself. 341 */ 342 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) || 343 (!need_right_hwpipe && mdp5_state->r_hwpipe)) 344 new_hwpipe = true; 345 346 if (mdp5_kms->smp) { 347 const struct mdp_format *format = 348 to_mdp_format(msm_framebuffer_format(state->fb)); 349 350 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, 351 state->src_w >> 16, false); 352 353 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg)) 354 new_hwpipe = true; 355 } 356 357 /* (re)assign hwpipe if needed, otherwise keep old one: */ 358 if (new_hwpipe) { 359 /* TODO maybe we want to re-assign hwpipe sometimes 360 * in cases when we no-longer need some caps to make 361 * it available for other planes? 362 */ 363 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe; 364 struct mdp5_hw_pipe *old_right_hwpipe = 365 mdp5_state->r_hwpipe; 366 struct mdp5_hw_pipe *new_hwpipe = NULL; 367 struct mdp5_hw_pipe *new_right_hwpipe = NULL; 368 369 ret = mdp5_pipe_assign(state->state, plane, caps, 370 blkcfg, &new_hwpipe, 371 need_right_hwpipe ? 372 &new_right_hwpipe : NULL); 373 if (ret) { 374 DBG("%s: failed to assign hwpipe(s)!", 375 plane->name); 376 return ret; 377 } 378 379 mdp5_state->hwpipe = new_hwpipe; 380 if (need_right_hwpipe) 381 mdp5_state->r_hwpipe = new_right_hwpipe; 382 else 383 /* 384 * set it to NULL so that the driver knows we 385 * don't have a right hwpipe when committing a 386 * new state 387 */ 388 mdp5_state->r_hwpipe = NULL; 389 390 391 mdp5_pipe_release(state->state, old_hwpipe); 392 mdp5_pipe_release(state->state, old_right_hwpipe); 393 } 394 } else { 395 mdp5_pipe_release(state->state, mdp5_state->hwpipe); 396 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe); 397 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL; 398 } 399 400 return 0; 401 } 402 403 static int mdp5_plane_atomic_check(struct drm_plane *plane, 404 struct drm_plane_state *state) 405 { 406 struct drm_crtc *crtc; 407 struct drm_crtc_state *crtc_state; 408 409 crtc = state->crtc ? state->crtc : plane->state->crtc; 410 if (!crtc) 411 return 0; 412 413 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 414 if (WARN_ON(!crtc_state)) 415 return -EINVAL; 416 417 return mdp5_plane_atomic_check_with_state(crtc_state, state); 418 } 419 420 static void mdp5_plane_atomic_update(struct drm_plane *plane, 421 struct drm_plane_state *old_state) 422 { 423 struct drm_plane_state *state = plane->state; 424 425 DBG("%s: update", plane->name); 426 427 if (plane_enabled(state)) { 428 int ret; 429 430 ret = mdp5_plane_mode_set(plane, 431 state->crtc, state->fb, 432 &state->src, &state->dst); 433 /* atomic_check should have ensured that this doesn't fail */ 434 WARN_ON(ret < 0); 435 } 436 } 437 438 static int mdp5_plane_atomic_async_check(struct drm_plane *plane, 439 struct drm_plane_state *state) 440 { 441 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 442 struct drm_crtc_state *crtc_state; 443 int min_scale, max_scale; 444 int ret; 445 446 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 447 state->crtc); 448 if (WARN_ON(!crtc_state)) 449 return -EINVAL; 450 451 if (!crtc_state->active) 452 return -EINVAL; 453 454 mdp5_state = to_mdp5_plane_state(state); 455 456 /* don't use fast path if we don't have a hwpipe allocated yet */ 457 if (!mdp5_state->hwpipe) 458 return -EINVAL; 459 460 /* only allow changing of position(crtc x/y or src x/y) in fast path */ 461 if (plane->state->crtc != state->crtc || 462 plane->state->src_w != state->src_w || 463 plane->state->src_h != state->src_h || 464 plane->state->crtc_w != state->crtc_w || 465 plane->state->crtc_h != state->crtc_h || 466 !plane->state->fb || 467 plane->state->fb != state->fb) 468 return -EINVAL; 469 470 min_scale = FRAC_16_16(1, 8); 471 max_scale = FRAC_16_16(8, 1); 472 473 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 474 min_scale, max_scale, 475 true, true); 476 if (ret) 477 return ret; 478 479 /* 480 * if the visibility of the plane changes (i.e, if the cursor is 481 * clipped out completely, we can't take the async path because 482 * we need to stage/unstage the plane from the Layer Mixer(s). We 483 * also assign/unassign the hwpipe(s) tied to the plane. We avoid 484 * taking the fast path for both these reasons. 485 */ 486 if (state->visible != plane->state->visible) 487 return -EINVAL; 488 489 return 0; 490 } 491 492 static void mdp5_plane_atomic_async_update(struct drm_plane *plane, 493 struct drm_plane_state *new_state) 494 { 495 struct drm_framebuffer *old_fb = plane->state->fb; 496 497 plane->state->src_x = new_state->src_x; 498 plane->state->src_y = new_state->src_y; 499 plane->state->crtc_x = new_state->crtc_x; 500 plane->state->crtc_y = new_state->crtc_y; 501 502 if (plane_enabled(new_state)) { 503 struct mdp5_ctl *ctl; 504 struct mdp5_pipeline *pipeline = 505 mdp5_crtc_get_pipeline(new_state->crtc); 506 int ret; 507 508 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb, 509 &new_state->src, &new_state->dst); 510 WARN_ON(ret < 0); 511 512 ctl = mdp5_crtc_get_ctl(new_state->crtc); 513 514 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true); 515 } 516 517 *to_mdp5_plane_state(plane->state) = 518 *to_mdp5_plane_state(new_state); 519 520 new_state->fb = old_fb; 521 } 522 523 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { 524 .prepare_fb = msm_atomic_prepare_fb, 525 .cleanup_fb = mdp5_plane_cleanup_fb, 526 .atomic_check = mdp5_plane_atomic_check, 527 .atomic_update = mdp5_plane_atomic_update, 528 .atomic_async_check = mdp5_plane_atomic_async_check, 529 .atomic_async_update = mdp5_plane_atomic_async_update, 530 }; 531 532 static void set_scanout_locked(struct mdp5_kms *mdp5_kms, 533 enum mdp5_pipe pipe, 534 struct drm_framebuffer *fb) 535 { 536 struct msm_kms *kms = &mdp5_kms->base.base; 537 538 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), 539 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | 540 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1])); 541 542 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), 543 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) | 544 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); 545 546 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), 547 msm_framebuffer_iova(fb, kms->aspace, 0)); 548 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), 549 msm_framebuffer_iova(fb, kms->aspace, 1)); 550 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), 551 msm_framebuffer_iova(fb, kms->aspace, 2)); 552 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), 553 msm_framebuffer_iova(fb, kms->aspace, 3)); 554 } 555 556 /* Note: mdp5_plane->pipe_lock must be locked */ 557 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) 558 { 559 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & 560 ~MDP5_PIPE_OP_MODE_CSC_1_EN; 561 562 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); 563 } 564 565 /* Note: mdp5_plane->pipe_lock must be locked */ 566 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 567 struct csc_cfg *csc) 568 { 569 uint32_t i, mode = 0; /* RGB, no CSC */ 570 uint32_t *matrix; 571 572 if (unlikely(!csc)) 573 return; 574 575 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) 576 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV); 577 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) 578 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); 579 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN; 580 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); 581 582 matrix = csc->matrix; 583 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), 584 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) | 585 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1])); 586 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), 587 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) | 588 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3])); 589 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), 590 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) | 591 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5])); 592 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), 593 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) | 594 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7])); 595 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), 596 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8])); 597 598 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { 599 uint32_t *pre_clamp = csc->pre_clamp; 600 uint32_t *post_clamp = csc->post_clamp; 601 602 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), 603 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) | 604 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i])); 605 606 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), 607 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) | 608 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i])); 609 610 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), 611 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); 612 613 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), 614 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); 615 } 616 } 617 618 #define PHASE_STEP_SHIFT 21 619 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */ 620 621 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) 622 { 623 uint32_t unit; 624 625 if (src == 0 || dst == 0) 626 return -EINVAL; 627 628 /* 629 * PHASE_STEP_X/Y is coded on 26 bits (25:0), 630 * where 2^21 represents the unity "1" in fixed-point hardware design. 631 * This leaves 5 bits for the integer part (downscale case): 632 * -> maximum downscale ratio = 0b1_1111 = 31 633 */ 634 if (src > (dst * DOWN_SCALE_RATIO_MAX)) 635 return -EOVERFLOW; 636 637 unit = 1 << PHASE_STEP_SHIFT; 638 *out_phase = mult_frac(unit, src, dst); 639 640 return 0; 641 } 642 643 static int calc_scalex_steps(struct drm_plane *plane, 644 uint32_t pixel_format, uint32_t src, uint32_t dest, 645 uint32_t phasex_steps[COMP_MAX]) 646 { 647 const struct drm_format_info *info = drm_format_info(pixel_format); 648 struct mdp5_kms *mdp5_kms = get_kms(plane); 649 struct device *dev = mdp5_kms->dev->dev; 650 uint32_t phasex_step; 651 int ret; 652 653 ret = calc_phase_step(src, dest, &phasex_step); 654 if (ret) { 655 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); 656 return ret; 657 } 658 659 phasex_steps[COMP_0] = phasex_step; 660 phasex_steps[COMP_3] = phasex_step; 661 phasex_steps[COMP_1_2] = phasex_step / info->hsub; 662 663 return 0; 664 } 665 666 static int calc_scaley_steps(struct drm_plane *plane, 667 uint32_t pixel_format, uint32_t src, uint32_t dest, 668 uint32_t phasey_steps[COMP_MAX]) 669 { 670 const struct drm_format_info *info = drm_format_info(pixel_format); 671 struct mdp5_kms *mdp5_kms = get_kms(plane); 672 struct device *dev = mdp5_kms->dev->dev; 673 uint32_t phasey_step; 674 int ret; 675 676 ret = calc_phase_step(src, dest, &phasey_step); 677 if (ret) { 678 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); 679 return ret; 680 } 681 682 phasey_steps[COMP_0] = phasey_step; 683 phasey_steps[COMP_3] = phasey_step; 684 phasey_steps[COMP_1_2] = phasey_step / info->vsub; 685 686 return 0; 687 } 688 689 static uint32_t get_scale_config(const struct mdp_format *format, 690 uint32_t src, uint32_t dst, bool horz) 691 { 692 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 693 bool scaling = format->is_yuv ? true : (src != dst); 694 uint32_t sub; 695 uint32_t ya_filter, uv_filter; 696 bool yuv = format->is_yuv; 697 698 if (!scaling) 699 return 0; 700 701 if (yuv) { 702 sub = horz ? info->hsub : info->vsub; 703 uv_filter = ((src / sub) <= dst) ? 704 SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 705 } 706 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 707 708 if (horz) 709 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | 710 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | 711 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | 712 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); 713 else 714 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | 715 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | 716 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | 717 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); 718 } 719 720 static void calc_pixel_ext(const struct mdp_format *format, 721 uint32_t src, uint32_t dst, uint32_t phase_step[2], 722 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], 723 bool horz) 724 { 725 bool scaling = format->is_yuv ? true : (src != dst); 726 int i; 727 728 /* 729 * Note: 730 * We assume here that: 731 * 1. PCMN filter is used for downscale 732 * 2. bilinear filter is used for upscale 733 * 3. we are in a single pipe configuration 734 */ 735 736 for (i = 0; i < COMP_MAX; i++) { 737 pix_ext_edge1[i] = 0; 738 pix_ext_edge2[i] = scaling ? 1 : 0; 739 } 740 } 741 742 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 743 const struct mdp_format *format, 744 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], 745 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) 746 { 747 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 748 uint32_t lr, tb, req; 749 int i; 750 751 for (i = 0; i < COMP_MAX; i++) { 752 uint32_t roi_w = src_w; 753 uint32_t roi_h = src_h; 754 755 if (format->is_yuv && i == COMP_1_2) { 756 roi_w /= info->hsub; 757 roi_h /= info->vsub; 758 } 759 760 lr = (pe_left[i] >= 0) ? 761 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : 762 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); 763 764 lr |= (pe_right[i] >= 0) ? 765 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : 766 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); 767 768 tb = (pe_top[i] >= 0) ? 769 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : 770 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); 771 772 tb |= (pe_bottom[i] >= 0) ? 773 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : 774 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); 775 776 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + 777 pe_left[i] + pe_right[i]); 778 779 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + 780 pe_top[i] + pe_bottom[i]); 781 782 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); 783 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); 784 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); 785 786 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, 787 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), 788 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), 789 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), 790 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), 791 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); 792 793 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, 794 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), 795 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), 796 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), 797 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), 798 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); 799 } 800 } 801 802 struct pixel_ext { 803 int left[COMP_MAX]; 804 int right[COMP_MAX]; 805 int top[COMP_MAX]; 806 int bottom[COMP_MAX]; 807 }; 808 809 struct phase_step { 810 u32 x[COMP_MAX]; 811 u32 y[COMP_MAX]; 812 }; 813 814 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms, 815 struct mdp5_hw_pipe *hwpipe, 816 struct drm_framebuffer *fb, 817 struct phase_step *step, 818 struct pixel_ext *pe, 819 u32 scale_config, u32 hdecm, u32 vdecm, 820 bool hflip, bool vflip, 821 int crtc_x, int crtc_y, 822 unsigned int crtc_w, unsigned int crtc_h, 823 u32 src_img_w, u32 src_img_h, 824 u32 src_x, u32 src_y, 825 u32 src_w, u32 src_h) 826 { 827 enum mdp5_pipe pipe = hwpipe->pipe; 828 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT; 829 const struct mdp_format *format = 830 to_mdp_format(msm_framebuffer_format(fb)); 831 832 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), 833 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) | 834 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h)); 835 836 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), 837 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | 838 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); 839 840 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), 841 MDP5_PIPE_SRC_XY_X(src_x) | 842 MDP5_PIPE_SRC_XY_Y(src_y)); 843 844 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), 845 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | 846 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); 847 848 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), 849 MDP5_PIPE_OUT_XY_X(crtc_x) | 850 MDP5_PIPE_OUT_XY_Y(crtc_y)); 851 852 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), 853 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) | 854 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) | 855 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) | 856 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) | 857 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) | 858 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) | 859 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | 860 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) | 861 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) | 862 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample)); 863 864 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), 865 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) | 866 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) | 867 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) | 868 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3])); 869 870 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), 871 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | 872 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | 873 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | 874 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); 875 876 /* not using secure mode: */ 877 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); 878 879 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) 880 mdp5_write_pixel_ext(mdp5_kms, pipe, format, 881 src_w, pe->left, pe->right, 882 src_h, pe->top, pe->bottom); 883 884 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) { 885 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), 886 step->x[COMP_0]); 887 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), 888 step->y[COMP_0]); 889 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), 890 step->x[COMP_1_2]); 891 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), 892 step->y[COMP_1_2]); 893 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), 894 MDP5_PIPE_DECIMATION_VERT(vdecm) | 895 MDP5_PIPE_DECIMATION_HORZ(hdecm)); 896 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), 897 scale_config); 898 } 899 900 if (hwpipe->caps & MDP_PIPE_CAP_CSC) { 901 if (MDP_FORMAT_IS_YUV(format)) 902 csc_enable(mdp5_kms, pipe, 903 mdp_get_default_csc_cfg(CSC_YUV2RGB)); 904 else 905 csc_disable(mdp5_kms, pipe); 906 } 907 908 set_scanout_locked(mdp5_kms, pipe, fb); 909 } 910 911 static int mdp5_plane_mode_set(struct drm_plane *plane, 912 struct drm_crtc *crtc, struct drm_framebuffer *fb, 913 struct drm_rect *src, struct drm_rect *dest) 914 { 915 struct drm_plane_state *pstate = plane->state; 916 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; 917 struct mdp5_kms *mdp5_kms = get_kms(plane); 918 enum mdp5_pipe pipe = hwpipe->pipe; 919 struct mdp5_hw_pipe *right_hwpipe; 920 const struct mdp_format *format; 921 uint32_t nplanes, config = 0; 922 struct phase_step step = { { 0 } }; 923 struct pixel_ext pe = { { 0 } }; 924 uint32_t hdecm = 0, vdecm = 0; 925 uint32_t pix_format; 926 unsigned int rotation; 927 bool vflip, hflip; 928 int crtc_x, crtc_y; 929 unsigned int crtc_w, crtc_h; 930 uint32_t src_x, src_y; 931 uint32_t src_w, src_h; 932 uint32_t src_img_w, src_img_h; 933 int ret; 934 935 nplanes = fb->format->num_planes; 936 937 /* bad formats should already be rejected: */ 938 if (WARN_ON(nplanes > pipe2nclients(pipe))) 939 return -EINVAL; 940 941 format = to_mdp_format(msm_framebuffer_format(fb)); 942 pix_format = format->base.pixel_format; 943 944 src_x = src->x1; 945 src_y = src->y1; 946 src_w = drm_rect_width(src); 947 src_h = drm_rect_height(src); 948 949 crtc_x = dest->x1; 950 crtc_y = dest->y1; 951 crtc_w = drm_rect_width(dest); 952 crtc_h = drm_rect_height(dest); 953 954 /* src values are in Q16 fixed point, convert to integer: */ 955 src_x = src_x >> 16; 956 src_y = src_y >> 16; 957 src_w = src_w >> 16; 958 src_h = src_h >> 16; 959 960 src_img_w = min(fb->width, src_w); 961 src_img_h = min(fb->height, src_h); 962 963 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name, 964 fb->base.id, src_x, src_y, src_w, src_h, 965 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); 966 967 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe; 968 if (right_hwpipe) { 969 /* 970 * if the plane comprises of 2 hw pipes, assume that the width 971 * is split equally across them. The only parameters that varies 972 * between the 2 pipes are src_x and crtc_x 973 */ 974 crtc_w /= 2; 975 src_w /= 2; 976 src_img_w /= 2; 977 } 978 979 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); 980 if (ret) 981 return ret; 982 983 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y); 984 if (ret) 985 return ret; 986 987 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) { 988 calc_pixel_ext(format, src_w, crtc_w, step.x, 989 pe.left, pe.right, true); 990 calc_pixel_ext(format, src_h, crtc_h, step.y, 991 pe.top, pe.bottom, false); 992 } 993 994 /* TODO calc hdecm, vdecm */ 995 996 /* SCALE is used to both scale and up-sample chroma components */ 997 config |= get_scale_config(format, src_w, crtc_w, true); 998 config |= get_scale_config(format, src_h, crtc_h, false); 999 DBG("scale config = %x", config); 1000 1001 rotation = drm_rotation_simplify(pstate->rotation, 1002 DRM_MODE_ROTATE_0 | 1003 DRM_MODE_REFLECT_X | 1004 DRM_MODE_REFLECT_Y); 1005 hflip = !!(rotation & DRM_MODE_REFLECT_X); 1006 vflip = !!(rotation & DRM_MODE_REFLECT_Y); 1007 1008 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe, 1009 config, hdecm, vdecm, hflip, vflip, 1010 crtc_x, crtc_y, crtc_w, crtc_h, 1011 src_img_w, src_img_h, 1012 src_x, src_y, src_w, src_h); 1013 if (right_hwpipe) 1014 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, 1015 config, hdecm, vdecm, hflip, vflip, 1016 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h, 1017 src_img_w, src_img_h, 1018 src_x + src_w, src_y, src_w, src_h); 1019 1020 return ret; 1021 } 1022 1023 /* 1024 * Use this func and the one below only after the atomic state has been 1025 * successfully swapped 1026 */ 1027 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) 1028 { 1029 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1030 1031 if (WARN_ON(!pstate->hwpipe)) 1032 return SSPP_NONE; 1033 1034 return pstate->hwpipe->pipe; 1035 } 1036 1037 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane) 1038 { 1039 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1040 1041 if (!pstate->r_hwpipe) 1042 return SSPP_NONE; 1043 1044 return pstate->r_hwpipe->pipe; 1045 } 1046 1047 uint32_t mdp5_plane_get_flush(struct drm_plane *plane) 1048 { 1049 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1050 u32 mask; 1051 1052 if (WARN_ON(!pstate->hwpipe)) 1053 return 0; 1054 1055 mask = pstate->hwpipe->flush_mask; 1056 1057 if (pstate->r_hwpipe) 1058 mask |= pstate->r_hwpipe->flush_mask; 1059 1060 return mask; 1061 } 1062 1063 /* initialize plane */ 1064 struct drm_plane *mdp5_plane_init(struct drm_device *dev, 1065 enum drm_plane_type type) 1066 { 1067 struct drm_plane *plane = NULL; 1068 struct mdp5_plane *mdp5_plane; 1069 int ret; 1070 1071 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL); 1072 if (!mdp5_plane) { 1073 ret = -ENOMEM; 1074 goto fail; 1075 } 1076 1077 plane = &mdp5_plane->base; 1078 1079 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats, 1080 ARRAY_SIZE(mdp5_plane->formats), false); 1081 1082 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs, 1083 mdp5_plane->formats, mdp5_plane->nformats, 1084 NULL, type, NULL); 1085 if (ret) 1086 goto fail; 1087 1088 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs); 1089 1090 mdp5_plane_install_properties(plane, &plane->base); 1091 1092 drm_plane_enable_fb_damage_clips(plane); 1093 1094 return plane; 1095 1096 fail: 1097 if (plane) 1098 mdp5_plane_destroy(plane); 1099 1100 return ERR_PTR(ret); 1101 } 1102