1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <drm/drm_damage_helper.h> 9 #include <drm/drm_fourcc.h> 10 #include <drm/drm_print.h> 11 12 #include "mdp5_kms.h" 13 14 struct mdp5_plane { 15 struct drm_plane base; 16 17 uint32_t nformats; 18 uint32_t formats[32]; 19 }; 20 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) 21 22 static int mdp5_plane_mode_set(struct drm_plane *plane, 23 struct drm_crtc *crtc, struct drm_framebuffer *fb, 24 struct drm_rect *src, struct drm_rect *dest); 25 26 static struct mdp5_kms *get_kms(struct drm_plane *plane) 27 { 28 struct msm_drm_private *priv = plane->dev->dev_private; 29 return to_mdp5_kms(to_mdp_kms(priv->kms)); 30 } 31 32 static bool plane_enabled(struct drm_plane_state *state) 33 { 34 return state->visible; 35 } 36 37 static void mdp5_plane_destroy(struct drm_plane *plane) 38 { 39 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); 40 41 drm_plane_cleanup(plane); 42 43 kfree(mdp5_plane); 44 } 45 46 static void mdp5_plane_install_rotation_property(struct drm_device *dev, 47 struct drm_plane *plane) 48 { 49 drm_plane_create_rotation_property(plane, 50 DRM_MODE_ROTATE_0, 51 DRM_MODE_ROTATE_0 | 52 DRM_MODE_ROTATE_180 | 53 DRM_MODE_REFLECT_X | 54 DRM_MODE_REFLECT_Y); 55 } 56 57 /* helper to install properties which are common to planes and crtcs */ 58 static void mdp5_plane_install_properties(struct drm_plane *plane, 59 struct drm_mode_object *obj) 60 { 61 struct drm_device *dev = plane->dev; 62 struct msm_drm_private *dev_priv = dev->dev_private; 63 struct drm_property *prop; 64 65 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \ 66 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \ 67 if (!prop) { \ 68 prop = drm_property_##fnc(dev, 0, #name, \ 69 ##__VA_ARGS__); \ 70 if (!prop) { \ 71 dev_warn(dev->dev, \ 72 "Create property %s failed\n", \ 73 #name); \ 74 return; \ 75 } \ 76 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \ 77 } \ 78 drm_object_attach_property(&plane->base, prop, init_val); \ 79 } while (0) 80 81 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \ 82 INSTALL_PROPERTY(name, NAME, init_val, \ 83 create_range, min, max) 84 85 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \ 86 INSTALL_PROPERTY(name, NAME, init_val, \ 87 create_enum, name##_prop_enum_list, \ 88 ARRAY_SIZE(name##_prop_enum_list)) 89 90 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1); 91 92 mdp5_plane_install_rotation_property(dev, plane); 93 94 #undef INSTALL_RANGE_PROPERTY 95 #undef INSTALL_ENUM_PROPERTY 96 #undef INSTALL_PROPERTY 97 } 98 99 static int mdp5_plane_atomic_set_property(struct drm_plane *plane, 100 struct drm_plane_state *state, struct drm_property *property, 101 uint64_t val) 102 { 103 struct drm_device *dev = plane->dev; 104 struct mdp5_plane_state *pstate; 105 struct msm_drm_private *dev_priv = dev->dev_private; 106 int ret = 0; 107 108 pstate = to_mdp5_plane_state(state); 109 110 #define SET_PROPERTY(name, NAME, type) do { \ 111 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ 112 pstate->name = (type)val; \ 113 DBG("Set property %s %d", #name, (type)val); \ 114 goto done; \ 115 } \ 116 } while (0) 117 118 SET_PROPERTY(zpos, ZPOS, uint8_t); 119 120 DRM_DEV_ERROR(dev->dev, "Invalid property\n"); 121 ret = -EINVAL; 122 done: 123 return ret; 124 #undef SET_PROPERTY 125 } 126 127 static int mdp5_plane_atomic_get_property(struct drm_plane *plane, 128 const struct drm_plane_state *state, 129 struct drm_property *property, uint64_t *val) 130 { 131 struct drm_device *dev = plane->dev; 132 struct mdp5_plane_state *pstate; 133 struct msm_drm_private *dev_priv = dev->dev_private; 134 int ret = 0; 135 136 pstate = to_mdp5_plane_state(state); 137 138 #define GET_PROPERTY(name, NAME, type) do { \ 139 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ 140 *val = pstate->name; \ 141 DBG("Get property %s %lld", #name, *val); \ 142 goto done; \ 143 } \ 144 } while (0) 145 146 GET_PROPERTY(zpos, ZPOS, uint8_t); 147 148 DRM_DEV_ERROR(dev->dev, "Invalid property\n"); 149 ret = -EINVAL; 150 done: 151 return ret; 152 #undef SET_PROPERTY 153 } 154 155 static void 156 mdp5_plane_atomic_print_state(struct drm_printer *p, 157 const struct drm_plane_state *state) 158 { 159 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 160 struct mdp5_kms *mdp5_kms = get_kms(state->plane); 161 162 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? 163 pstate->hwpipe->name : "(null)"); 164 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) 165 drm_printf(p, "\tright-hwpipe=%s\n", 166 pstate->r_hwpipe ? pstate->r_hwpipe->name : 167 "(null)"); 168 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied); 169 drm_printf(p, "\tzpos=%u\n", pstate->zpos); 170 drm_printf(p, "\talpha=%u\n", pstate->alpha); 171 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); 172 } 173 174 static void mdp5_plane_reset(struct drm_plane *plane) 175 { 176 struct mdp5_plane_state *mdp5_state; 177 178 if (plane->state && plane->state->fb) 179 drm_framebuffer_put(plane->state->fb); 180 181 kfree(to_mdp5_plane_state(plane->state)); 182 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); 183 184 /* assign default blend parameters */ 185 mdp5_state->alpha = 255; 186 mdp5_state->premultiplied = 0; 187 188 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 189 mdp5_state->zpos = STAGE_BASE; 190 else 191 mdp5_state->zpos = STAGE0 + drm_plane_index(plane); 192 193 mdp5_state->base.plane = plane; 194 195 plane->state = &mdp5_state->base; 196 } 197 198 static struct drm_plane_state * 199 mdp5_plane_duplicate_state(struct drm_plane *plane) 200 { 201 struct mdp5_plane_state *mdp5_state; 202 203 if (WARN_ON(!plane->state)) 204 return NULL; 205 206 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state), 207 sizeof(*mdp5_state), GFP_KERNEL); 208 if (!mdp5_state) 209 return NULL; 210 211 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); 212 213 return &mdp5_state->base; 214 } 215 216 static void mdp5_plane_destroy_state(struct drm_plane *plane, 217 struct drm_plane_state *state) 218 { 219 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 220 221 if (state->fb) 222 drm_framebuffer_put(state->fb); 223 224 kfree(pstate); 225 } 226 227 static const struct drm_plane_funcs mdp5_plane_funcs = { 228 .update_plane = drm_atomic_helper_update_plane, 229 .disable_plane = drm_atomic_helper_disable_plane, 230 .destroy = mdp5_plane_destroy, 231 .atomic_set_property = mdp5_plane_atomic_set_property, 232 .atomic_get_property = mdp5_plane_atomic_get_property, 233 .reset = mdp5_plane_reset, 234 .atomic_duplicate_state = mdp5_plane_duplicate_state, 235 .atomic_destroy_state = mdp5_plane_destroy_state, 236 .atomic_print_state = mdp5_plane_atomic_print_state, 237 }; 238 239 static void mdp5_plane_cleanup_fb(struct drm_plane *plane, 240 struct drm_plane_state *old_state) 241 { 242 struct mdp5_kms *mdp5_kms = get_kms(plane); 243 struct msm_kms *kms = &mdp5_kms->base.base; 244 struct drm_framebuffer *fb = old_state->fb; 245 246 if (!fb) 247 return; 248 249 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); 250 msm_framebuffer_cleanup(fb, kms->aspace); 251 } 252 253 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, 254 struct drm_plane_state *state) 255 { 256 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 257 struct drm_plane *plane = state->plane; 258 struct drm_plane_state *old_state = plane->state; 259 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg); 260 bool new_hwpipe = false; 261 bool need_right_hwpipe = false; 262 uint32_t max_width, max_height; 263 bool out_of_bounds = false; 264 uint32_t caps = 0; 265 int min_scale, max_scale; 266 int ret; 267 268 DBG("%s: check (%d -> %d)", plane->name, 269 plane_enabled(old_state), plane_enabled(state)); 270 271 max_width = config->hw->lm.max_width << 16; 272 max_height = config->hw->lm.max_height << 16; 273 274 /* Make sure source dimensions are within bounds. */ 275 if (state->src_h > max_height) 276 out_of_bounds = true; 277 278 if (state->src_w > max_width) { 279 /* If source split is supported, we can go up to 2x 280 * the max LM width, but we'd need to stage another 281 * hwpipe to the right LM. So, the drm_plane would 282 * consist of 2 hwpipes. 283 */ 284 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT && 285 (state->src_w <= 2 * max_width)) 286 need_right_hwpipe = true; 287 else 288 out_of_bounds = true; 289 } 290 291 if (out_of_bounds) { 292 struct drm_rect src = drm_plane_state_src(state); 293 DBG("Invalid source size "DRM_RECT_FP_FMT, 294 DRM_RECT_FP_ARG(&src)); 295 return -ERANGE; 296 } 297 298 min_scale = FRAC_16_16(1, 8); 299 max_scale = FRAC_16_16(8, 1); 300 301 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 302 min_scale, max_scale, 303 true, true); 304 if (ret) 305 return ret; 306 307 if (plane_enabled(state)) { 308 unsigned int rotation; 309 const struct mdp_format *format; 310 struct mdp5_kms *mdp5_kms = get_kms(plane); 311 uint32_t blkcfg = 0; 312 313 format = to_mdp_format(msm_framebuffer_format(state->fb)); 314 if (MDP_FORMAT_IS_YUV(format)) 315 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC; 316 317 if (((state->src_w >> 16) != state->crtc_w) || 318 ((state->src_h >> 16) != state->crtc_h)) 319 caps |= MDP_PIPE_CAP_SCALE; 320 321 rotation = drm_rotation_simplify(state->rotation, 322 DRM_MODE_ROTATE_0 | 323 DRM_MODE_REFLECT_X | 324 DRM_MODE_REFLECT_Y); 325 326 if (rotation & DRM_MODE_REFLECT_X) 327 caps |= MDP_PIPE_CAP_HFLIP; 328 329 if (rotation & DRM_MODE_REFLECT_Y) 330 caps |= MDP_PIPE_CAP_VFLIP; 331 332 if (plane->type == DRM_PLANE_TYPE_CURSOR) 333 caps |= MDP_PIPE_CAP_CURSOR; 334 335 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */ 336 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps)) 337 new_hwpipe = true; 338 339 /* 340 * (re)allocte hw pipe if we're either requesting for 2 hw pipes 341 * or we're switching from 2 hw pipes to 1 hw pipe because the 342 * new src_w can be supported by 1 hw pipe itself. 343 */ 344 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) || 345 (!need_right_hwpipe && mdp5_state->r_hwpipe)) 346 new_hwpipe = true; 347 348 if (mdp5_kms->smp) { 349 const struct mdp_format *format = 350 to_mdp_format(msm_framebuffer_format(state->fb)); 351 352 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, 353 state->src_w >> 16, false); 354 355 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg)) 356 new_hwpipe = true; 357 } 358 359 /* (re)assign hwpipe if needed, otherwise keep old one: */ 360 if (new_hwpipe) { 361 /* TODO maybe we want to re-assign hwpipe sometimes 362 * in cases when we no-longer need some caps to make 363 * it available for other planes? 364 */ 365 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe; 366 struct mdp5_hw_pipe *old_right_hwpipe = 367 mdp5_state->r_hwpipe; 368 struct mdp5_hw_pipe *new_hwpipe = NULL; 369 struct mdp5_hw_pipe *new_right_hwpipe = NULL; 370 371 ret = mdp5_pipe_assign(state->state, plane, caps, 372 blkcfg, &new_hwpipe, 373 need_right_hwpipe ? 374 &new_right_hwpipe : NULL); 375 if (ret) { 376 DBG("%s: failed to assign hwpipe(s)!", 377 plane->name); 378 return ret; 379 } 380 381 mdp5_state->hwpipe = new_hwpipe; 382 if (need_right_hwpipe) 383 mdp5_state->r_hwpipe = new_right_hwpipe; 384 else 385 /* 386 * set it to NULL so that the driver knows we 387 * don't have a right hwpipe when committing a 388 * new state 389 */ 390 mdp5_state->r_hwpipe = NULL; 391 392 393 mdp5_pipe_release(state->state, old_hwpipe); 394 mdp5_pipe_release(state->state, old_right_hwpipe); 395 } 396 } else { 397 mdp5_pipe_release(state->state, mdp5_state->hwpipe); 398 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe); 399 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL; 400 } 401 402 return 0; 403 } 404 405 static int mdp5_plane_atomic_check(struct drm_plane *plane, 406 struct drm_plane_state *state) 407 { 408 struct drm_crtc *crtc; 409 struct drm_crtc_state *crtc_state; 410 411 crtc = state->crtc ? state->crtc : plane->state->crtc; 412 if (!crtc) 413 return 0; 414 415 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 416 if (WARN_ON(!crtc_state)) 417 return -EINVAL; 418 419 return mdp5_plane_atomic_check_with_state(crtc_state, state); 420 } 421 422 static void mdp5_plane_atomic_update(struct drm_plane *plane, 423 struct drm_plane_state *old_state) 424 { 425 struct drm_plane_state *state = plane->state; 426 427 DBG("%s: update", plane->name); 428 429 if (plane_enabled(state)) { 430 int ret; 431 432 ret = mdp5_plane_mode_set(plane, 433 state->crtc, state->fb, 434 &state->src, &state->dst); 435 /* atomic_check should have ensured that this doesn't fail */ 436 WARN_ON(ret < 0); 437 } 438 } 439 440 static int mdp5_plane_atomic_async_check(struct drm_plane *plane, 441 struct drm_plane_state *state) 442 { 443 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 444 struct drm_crtc_state *crtc_state; 445 int min_scale, max_scale; 446 int ret; 447 448 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 449 state->crtc); 450 if (WARN_ON(!crtc_state)) 451 return -EINVAL; 452 453 if (!crtc_state->active) 454 return -EINVAL; 455 456 mdp5_state = to_mdp5_plane_state(state); 457 458 /* don't use fast path if we don't have a hwpipe allocated yet */ 459 if (!mdp5_state->hwpipe) 460 return -EINVAL; 461 462 /* only allow changing of position(crtc x/y or src x/y) in fast path */ 463 if (plane->state->crtc != state->crtc || 464 plane->state->src_w != state->src_w || 465 plane->state->src_h != state->src_h || 466 plane->state->crtc_w != state->crtc_w || 467 plane->state->crtc_h != state->crtc_h || 468 !plane->state->fb || 469 plane->state->fb != state->fb) 470 return -EINVAL; 471 472 min_scale = FRAC_16_16(1, 8); 473 max_scale = FRAC_16_16(8, 1); 474 475 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 476 min_scale, max_scale, 477 true, true); 478 if (ret) 479 return ret; 480 481 /* 482 * if the visibility of the plane changes (i.e, if the cursor is 483 * clipped out completely, we can't take the async path because 484 * we need to stage/unstage the plane from the Layer Mixer(s). We 485 * also assign/unassign the hwpipe(s) tied to the plane. We avoid 486 * taking the fast path for both these reasons. 487 */ 488 if (state->visible != plane->state->visible) 489 return -EINVAL; 490 491 return 0; 492 } 493 494 static void mdp5_plane_atomic_async_update(struct drm_plane *plane, 495 struct drm_plane_state *new_state) 496 { 497 struct drm_framebuffer *old_fb = plane->state->fb; 498 499 plane->state->src_x = new_state->src_x; 500 plane->state->src_y = new_state->src_y; 501 plane->state->crtc_x = new_state->crtc_x; 502 plane->state->crtc_y = new_state->crtc_y; 503 504 if (plane_enabled(new_state)) { 505 struct mdp5_ctl *ctl; 506 struct mdp5_pipeline *pipeline = 507 mdp5_crtc_get_pipeline(new_state->crtc); 508 int ret; 509 510 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb, 511 &new_state->src, &new_state->dst); 512 WARN_ON(ret < 0); 513 514 ctl = mdp5_crtc_get_ctl(new_state->crtc); 515 516 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true); 517 } 518 519 *to_mdp5_plane_state(plane->state) = 520 *to_mdp5_plane_state(new_state); 521 522 new_state->fb = old_fb; 523 } 524 525 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { 526 .prepare_fb = msm_atomic_prepare_fb, 527 .cleanup_fb = mdp5_plane_cleanup_fb, 528 .atomic_check = mdp5_plane_atomic_check, 529 .atomic_update = mdp5_plane_atomic_update, 530 .atomic_async_check = mdp5_plane_atomic_async_check, 531 .atomic_async_update = mdp5_plane_atomic_async_update, 532 }; 533 534 static void set_scanout_locked(struct mdp5_kms *mdp5_kms, 535 enum mdp5_pipe pipe, 536 struct drm_framebuffer *fb) 537 { 538 struct msm_kms *kms = &mdp5_kms->base.base; 539 540 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), 541 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | 542 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1])); 543 544 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), 545 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) | 546 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); 547 548 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), 549 msm_framebuffer_iova(fb, kms->aspace, 0)); 550 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), 551 msm_framebuffer_iova(fb, kms->aspace, 1)); 552 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), 553 msm_framebuffer_iova(fb, kms->aspace, 2)); 554 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), 555 msm_framebuffer_iova(fb, kms->aspace, 3)); 556 } 557 558 /* Note: mdp5_plane->pipe_lock must be locked */ 559 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) 560 { 561 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & 562 ~MDP5_PIPE_OP_MODE_CSC_1_EN; 563 564 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); 565 } 566 567 /* Note: mdp5_plane->pipe_lock must be locked */ 568 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 569 struct csc_cfg *csc) 570 { 571 uint32_t i, mode = 0; /* RGB, no CSC */ 572 uint32_t *matrix; 573 574 if (unlikely(!csc)) 575 return; 576 577 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) 578 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV); 579 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) 580 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); 581 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN; 582 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); 583 584 matrix = csc->matrix; 585 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), 586 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) | 587 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1])); 588 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), 589 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) | 590 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3])); 591 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), 592 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) | 593 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5])); 594 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), 595 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) | 596 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7])); 597 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), 598 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8])); 599 600 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { 601 uint32_t *pre_clamp = csc->pre_clamp; 602 uint32_t *post_clamp = csc->post_clamp; 603 604 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), 605 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) | 606 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i])); 607 608 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), 609 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) | 610 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i])); 611 612 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), 613 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); 614 615 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), 616 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); 617 } 618 } 619 620 #define PHASE_STEP_SHIFT 21 621 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */ 622 623 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) 624 { 625 uint32_t unit; 626 627 if (src == 0 || dst == 0) 628 return -EINVAL; 629 630 /* 631 * PHASE_STEP_X/Y is coded on 26 bits (25:0), 632 * where 2^21 represents the unity "1" in fixed-point hardware design. 633 * This leaves 5 bits for the integer part (downscale case): 634 * -> maximum downscale ratio = 0b1_1111 = 31 635 */ 636 if (src > (dst * DOWN_SCALE_RATIO_MAX)) 637 return -EOVERFLOW; 638 639 unit = 1 << PHASE_STEP_SHIFT; 640 *out_phase = mult_frac(unit, src, dst); 641 642 return 0; 643 } 644 645 static int calc_scalex_steps(struct drm_plane *plane, 646 uint32_t pixel_format, uint32_t src, uint32_t dest, 647 uint32_t phasex_steps[COMP_MAX]) 648 { 649 const struct drm_format_info *info = drm_format_info(pixel_format); 650 struct mdp5_kms *mdp5_kms = get_kms(plane); 651 struct device *dev = mdp5_kms->dev->dev; 652 uint32_t phasex_step; 653 int ret; 654 655 ret = calc_phase_step(src, dest, &phasex_step); 656 if (ret) { 657 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); 658 return ret; 659 } 660 661 phasex_steps[COMP_0] = phasex_step; 662 phasex_steps[COMP_3] = phasex_step; 663 phasex_steps[COMP_1_2] = phasex_step / info->hsub; 664 665 return 0; 666 } 667 668 static int calc_scaley_steps(struct drm_plane *plane, 669 uint32_t pixel_format, uint32_t src, uint32_t dest, 670 uint32_t phasey_steps[COMP_MAX]) 671 { 672 const struct drm_format_info *info = drm_format_info(pixel_format); 673 struct mdp5_kms *mdp5_kms = get_kms(plane); 674 struct device *dev = mdp5_kms->dev->dev; 675 uint32_t phasey_step; 676 int ret; 677 678 ret = calc_phase_step(src, dest, &phasey_step); 679 if (ret) { 680 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); 681 return ret; 682 } 683 684 phasey_steps[COMP_0] = phasey_step; 685 phasey_steps[COMP_3] = phasey_step; 686 phasey_steps[COMP_1_2] = phasey_step / info->vsub; 687 688 return 0; 689 } 690 691 static uint32_t get_scale_config(const struct mdp_format *format, 692 uint32_t src, uint32_t dst, bool horz) 693 { 694 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 695 bool scaling = format->is_yuv ? true : (src != dst); 696 uint32_t sub; 697 uint32_t ya_filter, uv_filter; 698 bool yuv = format->is_yuv; 699 700 if (!scaling) 701 return 0; 702 703 if (yuv) { 704 sub = horz ? info->hsub : info->vsub; 705 uv_filter = ((src / sub) <= dst) ? 706 SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 707 } 708 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 709 710 if (horz) 711 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | 712 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | 713 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | 714 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); 715 else 716 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | 717 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | 718 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | 719 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); 720 } 721 722 static void calc_pixel_ext(const struct mdp_format *format, 723 uint32_t src, uint32_t dst, uint32_t phase_step[2], 724 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], 725 bool horz) 726 { 727 bool scaling = format->is_yuv ? true : (src != dst); 728 int i; 729 730 /* 731 * Note: 732 * We assume here that: 733 * 1. PCMN filter is used for downscale 734 * 2. bilinear filter is used for upscale 735 * 3. we are in a single pipe configuration 736 */ 737 738 for (i = 0; i < COMP_MAX; i++) { 739 pix_ext_edge1[i] = 0; 740 pix_ext_edge2[i] = scaling ? 1 : 0; 741 } 742 } 743 744 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 745 const struct mdp_format *format, 746 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], 747 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) 748 { 749 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 750 uint32_t lr, tb, req; 751 int i; 752 753 for (i = 0; i < COMP_MAX; i++) { 754 uint32_t roi_w = src_w; 755 uint32_t roi_h = src_h; 756 757 if (format->is_yuv && i == COMP_1_2) { 758 roi_w /= info->hsub; 759 roi_h /= info->vsub; 760 } 761 762 lr = (pe_left[i] >= 0) ? 763 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : 764 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); 765 766 lr |= (pe_right[i] >= 0) ? 767 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : 768 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); 769 770 tb = (pe_top[i] >= 0) ? 771 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : 772 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); 773 774 tb |= (pe_bottom[i] >= 0) ? 775 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : 776 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); 777 778 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + 779 pe_left[i] + pe_right[i]); 780 781 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + 782 pe_top[i] + pe_bottom[i]); 783 784 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); 785 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); 786 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); 787 788 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, 789 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), 790 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), 791 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), 792 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), 793 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); 794 795 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, 796 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), 797 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), 798 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), 799 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), 800 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); 801 } 802 } 803 804 struct pixel_ext { 805 int left[COMP_MAX]; 806 int right[COMP_MAX]; 807 int top[COMP_MAX]; 808 int bottom[COMP_MAX]; 809 }; 810 811 struct phase_step { 812 u32 x[COMP_MAX]; 813 u32 y[COMP_MAX]; 814 }; 815 816 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms, 817 struct mdp5_hw_pipe *hwpipe, 818 struct drm_framebuffer *fb, 819 struct phase_step *step, 820 struct pixel_ext *pe, 821 u32 scale_config, u32 hdecm, u32 vdecm, 822 bool hflip, bool vflip, 823 int crtc_x, int crtc_y, 824 unsigned int crtc_w, unsigned int crtc_h, 825 u32 src_img_w, u32 src_img_h, 826 u32 src_x, u32 src_y, 827 u32 src_w, u32 src_h) 828 { 829 enum mdp5_pipe pipe = hwpipe->pipe; 830 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT; 831 const struct mdp_format *format = 832 to_mdp_format(msm_framebuffer_format(fb)); 833 834 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), 835 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) | 836 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h)); 837 838 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), 839 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | 840 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); 841 842 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), 843 MDP5_PIPE_SRC_XY_X(src_x) | 844 MDP5_PIPE_SRC_XY_Y(src_y)); 845 846 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), 847 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | 848 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); 849 850 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), 851 MDP5_PIPE_OUT_XY_X(crtc_x) | 852 MDP5_PIPE_OUT_XY_Y(crtc_y)); 853 854 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), 855 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) | 856 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) | 857 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) | 858 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) | 859 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) | 860 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) | 861 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | 862 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) | 863 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) | 864 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample)); 865 866 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), 867 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) | 868 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) | 869 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) | 870 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3])); 871 872 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), 873 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | 874 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | 875 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | 876 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); 877 878 /* not using secure mode: */ 879 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); 880 881 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) 882 mdp5_write_pixel_ext(mdp5_kms, pipe, format, 883 src_w, pe->left, pe->right, 884 src_h, pe->top, pe->bottom); 885 886 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) { 887 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), 888 step->x[COMP_0]); 889 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), 890 step->y[COMP_0]); 891 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), 892 step->x[COMP_1_2]); 893 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), 894 step->y[COMP_1_2]); 895 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), 896 MDP5_PIPE_DECIMATION_VERT(vdecm) | 897 MDP5_PIPE_DECIMATION_HORZ(hdecm)); 898 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), 899 scale_config); 900 } 901 902 if (hwpipe->caps & MDP_PIPE_CAP_CSC) { 903 if (MDP_FORMAT_IS_YUV(format)) 904 csc_enable(mdp5_kms, pipe, 905 mdp_get_default_csc_cfg(CSC_YUV2RGB)); 906 else 907 csc_disable(mdp5_kms, pipe); 908 } 909 910 set_scanout_locked(mdp5_kms, pipe, fb); 911 } 912 913 static int mdp5_plane_mode_set(struct drm_plane *plane, 914 struct drm_crtc *crtc, struct drm_framebuffer *fb, 915 struct drm_rect *src, struct drm_rect *dest) 916 { 917 struct drm_plane_state *pstate = plane->state; 918 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; 919 struct mdp5_kms *mdp5_kms = get_kms(plane); 920 enum mdp5_pipe pipe = hwpipe->pipe; 921 struct mdp5_hw_pipe *right_hwpipe; 922 const struct mdp_format *format; 923 uint32_t nplanes, config = 0; 924 struct phase_step step = { { 0 } }; 925 struct pixel_ext pe = { { 0 } }; 926 uint32_t hdecm = 0, vdecm = 0; 927 uint32_t pix_format; 928 unsigned int rotation; 929 bool vflip, hflip; 930 int crtc_x, crtc_y; 931 unsigned int crtc_w, crtc_h; 932 uint32_t src_x, src_y; 933 uint32_t src_w, src_h; 934 uint32_t src_img_w, src_img_h; 935 int ret; 936 937 nplanes = fb->format->num_planes; 938 939 /* bad formats should already be rejected: */ 940 if (WARN_ON(nplanes > pipe2nclients(pipe))) 941 return -EINVAL; 942 943 format = to_mdp_format(msm_framebuffer_format(fb)); 944 pix_format = format->base.pixel_format; 945 946 src_x = src->x1; 947 src_y = src->y1; 948 src_w = drm_rect_width(src); 949 src_h = drm_rect_height(src); 950 951 crtc_x = dest->x1; 952 crtc_y = dest->y1; 953 crtc_w = drm_rect_width(dest); 954 crtc_h = drm_rect_height(dest); 955 956 /* src values are in Q16 fixed point, convert to integer: */ 957 src_x = src_x >> 16; 958 src_y = src_y >> 16; 959 src_w = src_w >> 16; 960 src_h = src_h >> 16; 961 962 src_img_w = min(fb->width, src_w); 963 src_img_h = min(fb->height, src_h); 964 965 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name, 966 fb->base.id, src_x, src_y, src_w, src_h, 967 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); 968 969 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe; 970 if (right_hwpipe) { 971 /* 972 * if the plane comprises of 2 hw pipes, assume that the width 973 * is split equally across them. The only parameters that varies 974 * between the 2 pipes are src_x and crtc_x 975 */ 976 crtc_w /= 2; 977 src_w /= 2; 978 src_img_w /= 2; 979 } 980 981 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); 982 if (ret) 983 return ret; 984 985 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y); 986 if (ret) 987 return ret; 988 989 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) { 990 calc_pixel_ext(format, src_w, crtc_w, step.x, 991 pe.left, pe.right, true); 992 calc_pixel_ext(format, src_h, crtc_h, step.y, 993 pe.top, pe.bottom, false); 994 } 995 996 /* TODO calc hdecm, vdecm */ 997 998 /* SCALE is used to both scale and up-sample chroma components */ 999 config |= get_scale_config(format, src_w, crtc_w, true); 1000 config |= get_scale_config(format, src_h, crtc_h, false); 1001 DBG("scale config = %x", config); 1002 1003 rotation = drm_rotation_simplify(pstate->rotation, 1004 DRM_MODE_ROTATE_0 | 1005 DRM_MODE_REFLECT_X | 1006 DRM_MODE_REFLECT_Y); 1007 hflip = !!(rotation & DRM_MODE_REFLECT_X); 1008 vflip = !!(rotation & DRM_MODE_REFLECT_Y); 1009 1010 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe, 1011 config, hdecm, vdecm, hflip, vflip, 1012 crtc_x, crtc_y, crtc_w, crtc_h, 1013 src_img_w, src_img_h, 1014 src_x, src_y, src_w, src_h); 1015 if (right_hwpipe) 1016 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, 1017 config, hdecm, vdecm, hflip, vflip, 1018 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h, 1019 src_img_w, src_img_h, 1020 src_x + src_w, src_y, src_w, src_h); 1021 1022 return ret; 1023 } 1024 1025 /* 1026 * Use this func and the one below only after the atomic state has been 1027 * successfully swapped 1028 */ 1029 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) 1030 { 1031 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1032 1033 if (WARN_ON(!pstate->hwpipe)) 1034 return SSPP_NONE; 1035 1036 return pstate->hwpipe->pipe; 1037 } 1038 1039 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane) 1040 { 1041 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1042 1043 if (!pstate->r_hwpipe) 1044 return SSPP_NONE; 1045 1046 return pstate->r_hwpipe->pipe; 1047 } 1048 1049 uint32_t mdp5_plane_get_flush(struct drm_plane *plane) 1050 { 1051 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 1052 u32 mask; 1053 1054 if (WARN_ON(!pstate->hwpipe)) 1055 return 0; 1056 1057 mask = pstate->hwpipe->flush_mask; 1058 1059 if (pstate->r_hwpipe) 1060 mask |= pstate->r_hwpipe->flush_mask; 1061 1062 return mask; 1063 } 1064 1065 /* initialize plane */ 1066 struct drm_plane *mdp5_plane_init(struct drm_device *dev, 1067 enum drm_plane_type type) 1068 { 1069 struct drm_plane *plane = NULL; 1070 struct mdp5_plane *mdp5_plane; 1071 int ret; 1072 1073 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL); 1074 if (!mdp5_plane) { 1075 ret = -ENOMEM; 1076 goto fail; 1077 } 1078 1079 plane = &mdp5_plane->base; 1080 1081 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats, 1082 ARRAY_SIZE(mdp5_plane->formats), false); 1083 1084 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs, 1085 mdp5_plane->formats, mdp5_plane->nformats, 1086 NULL, type, NULL); 1087 if (ret) 1088 goto fail; 1089 1090 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs); 1091 1092 mdp5_plane_install_properties(plane, &plane->base); 1093 1094 drm_plane_enable_fb_damage_clips(plane); 1095 1096 return plane; 1097 1098 fail: 1099 if (plane) 1100 mdp5_plane_destroy(plane); 1101 1102 return ERR_PTR(ret); 1103 } 1104