1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <drm/drm_atomic.h> 9 #include <drm/drm_damage_helper.h> 10 #include <drm/drm_fourcc.h> 11 #include <drm/drm_gem_atomic_helper.h> 12 #include <drm/drm_print.h> 13 14 #include "mdp5_kms.h" 15 16 struct mdp5_plane { 17 struct drm_plane base; 18 19 uint32_t nformats; 20 uint32_t formats[32]; 21 }; 22 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) 23 24 static int mdp5_plane_mode_set(struct drm_plane *plane, 25 struct drm_crtc *crtc, struct drm_framebuffer *fb, 26 struct drm_rect *src, struct drm_rect *dest); 27 28 static struct mdp5_kms *get_kms(struct drm_plane *plane) 29 { 30 struct msm_drm_private *priv = plane->dev->dev_private; 31 return to_mdp5_kms(to_mdp_kms(priv->kms)); 32 } 33 34 static bool plane_enabled(struct drm_plane_state *state) 35 { 36 return state->visible; 37 } 38 39 static void mdp5_plane_destroy(struct drm_plane *plane) 40 { 41 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); 42 43 drm_plane_cleanup(plane); 44 45 kfree(mdp5_plane); 46 } 47 48 /* helper to install properties which are common to planes and crtcs */ 49 static void mdp5_plane_install_properties(struct drm_plane *plane, 50 struct drm_mode_object *obj) 51 { 52 unsigned int zpos; 53 54 drm_plane_create_rotation_property(plane, 55 DRM_MODE_ROTATE_0, 56 DRM_MODE_ROTATE_0 | 57 DRM_MODE_ROTATE_180 | 58 DRM_MODE_REFLECT_X | 59 DRM_MODE_REFLECT_Y); 60 drm_plane_create_alpha_property(plane); 61 drm_plane_create_blend_mode_property(plane, 62 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 63 BIT(DRM_MODE_BLEND_PREMULTI) | 64 BIT(DRM_MODE_BLEND_COVERAGE)); 65 66 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 67 zpos = STAGE_BASE; 68 else 69 zpos = STAGE0 + drm_plane_index(plane); 70 drm_plane_create_zpos_property(plane, zpos, 1, 255); 71 } 72 73 static void 74 mdp5_plane_atomic_print_state(struct drm_printer *p, 75 const struct drm_plane_state *state) 76 { 77 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 78 struct mdp5_kms *mdp5_kms = get_kms(state->plane); 79 80 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? 81 pstate->hwpipe->name : "(null)"); 82 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) 83 drm_printf(p, "\tright-hwpipe=%s\n", 84 pstate->r_hwpipe ? pstate->r_hwpipe->name : 85 "(null)"); 86 drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode); 87 drm_printf(p, "\tzpos=%u\n", pstate->base.zpos); 88 drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos); 89 drm_printf(p, "\talpha=%u\n", pstate->base.alpha); 90 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); 91 } 92 93 static void mdp5_plane_reset(struct drm_plane *plane) 94 { 95 struct mdp5_plane_state *mdp5_state; 96 97 if (plane->state) 98 __drm_atomic_helper_plane_destroy_state(plane->state); 99 100 kfree(to_mdp5_plane_state(plane->state)); 101 plane->state = NULL; 102 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); 103 if (!mdp5_state) 104 return; 105 __drm_atomic_helper_plane_reset(plane, &mdp5_state->base); 106 } 107 108 static struct drm_plane_state * 109 mdp5_plane_duplicate_state(struct drm_plane *plane) 110 { 111 struct mdp5_plane_state *mdp5_state; 112 113 if (WARN_ON(!plane->state)) 114 return NULL; 115 116 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state), 117 sizeof(*mdp5_state), GFP_KERNEL); 118 if (!mdp5_state) 119 return NULL; 120 121 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); 122 123 return &mdp5_state->base; 124 } 125 126 static void mdp5_plane_destroy_state(struct drm_plane *plane, 127 struct drm_plane_state *state) 128 { 129 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 130 131 if (state->fb) 132 drm_framebuffer_put(state->fb); 133 134 kfree(pstate); 135 } 136 137 static const struct drm_plane_funcs mdp5_plane_funcs = { 138 .update_plane = drm_atomic_helper_update_plane, 139 .disable_plane = drm_atomic_helper_disable_plane, 140 .destroy = mdp5_plane_destroy, 141 .reset = mdp5_plane_reset, 142 .atomic_duplicate_state = mdp5_plane_duplicate_state, 143 .atomic_destroy_state = mdp5_plane_destroy_state, 144 .atomic_print_state = mdp5_plane_atomic_print_state, 145 }; 146 147 static int mdp5_plane_prepare_fb(struct drm_plane *plane, 148 struct drm_plane_state *new_state) 149 { 150 struct msm_drm_private *priv = plane->dev->dev_private; 151 struct msm_kms *kms = priv->kms; 152 bool needs_dirtyfb = to_mdp5_plane_state(new_state)->needs_dirtyfb; 153 154 if (!new_state->fb) 155 return 0; 156 157 drm_gem_plane_helper_prepare_fb(plane, new_state); 158 159 return msm_framebuffer_prepare(new_state->fb, kms->aspace, needs_dirtyfb); 160 } 161 162 static void mdp5_plane_cleanup_fb(struct drm_plane *plane, 163 struct drm_plane_state *old_state) 164 { 165 struct mdp5_kms *mdp5_kms = get_kms(plane); 166 struct msm_kms *kms = &mdp5_kms->base.base; 167 struct drm_framebuffer *fb = old_state->fb; 168 bool needed_dirtyfb = to_mdp5_plane_state(old_state)->needs_dirtyfb; 169 170 if (!fb) 171 return; 172 173 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); 174 msm_framebuffer_cleanup(fb, kms->aspace, needed_dirtyfb); 175 } 176 177 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, 178 struct drm_plane_state *state) 179 { 180 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 181 struct drm_plane *plane = state->plane; 182 struct drm_plane_state *old_state = plane->state; 183 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg); 184 bool new_hwpipe = false; 185 bool need_right_hwpipe = false; 186 uint32_t max_width, max_height; 187 bool out_of_bounds = false; 188 uint32_t caps = 0; 189 int min_scale, max_scale; 190 int ret; 191 192 DBG("%s: check (%d -> %d)", plane->name, 193 plane_enabled(old_state), plane_enabled(state)); 194 195 max_width = config->hw->lm.max_width << 16; 196 max_height = config->hw->lm.max_height << 16; 197 198 /* Make sure source dimensions are within bounds. */ 199 if (state->src_h > max_height) 200 out_of_bounds = true; 201 202 if (state->src_w > max_width) { 203 /* If source split is supported, we can go up to 2x 204 * the max LM width, but we'd need to stage another 205 * hwpipe to the right LM. So, the drm_plane would 206 * consist of 2 hwpipes. 207 */ 208 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT && 209 (state->src_w <= 2 * max_width)) 210 need_right_hwpipe = true; 211 else 212 out_of_bounds = true; 213 } 214 215 if (out_of_bounds) { 216 struct drm_rect src = drm_plane_state_src(state); 217 DBG("Invalid source size "DRM_RECT_FP_FMT, 218 DRM_RECT_FP_ARG(&src)); 219 return -ERANGE; 220 } 221 222 min_scale = FRAC_16_16(1, 8); 223 max_scale = FRAC_16_16(8, 1); 224 225 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 226 min_scale, max_scale, 227 true, true); 228 if (ret) 229 return ret; 230 231 if (plane_enabled(state)) { 232 unsigned int rotation; 233 const struct mdp_format *format; 234 struct mdp5_kms *mdp5_kms = get_kms(plane); 235 uint32_t blkcfg = 0; 236 237 format = to_mdp_format(msm_framebuffer_format(state->fb)); 238 if (MDP_FORMAT_IS_YUV(format)) 239 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC; 240 241 if (((state->src_w >> 16) != state->crtc_w) || 242 ((state->src_h >> 16) != state->crtc_h)) 243 caps |= MDP_PIPE_CAP_SCALE; 244 245 rotation = drm_rotation_simplify(state->rotation, 246 DRM_MODE_ROTATE_0 | 247 DRM_MODE_REFLECT_X | 248 DRM_MODE_REFLECT_Y); 249 250 if (rotation & DRM_MODE_REFLECT_X) 251 caps |= MDP_PIPE_CAP_HFLIP; 252 253 if (rotation & DRM_MODE_REFLECT_Y) 254 caps |= MDP_PIPE_CAP_VFLIP; 255 256 if (plane->type == DRM_PLANE_TYPE_CURSOR) 257 caps |= MDP_PIPE_CAP_CURSOR; 258 259 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */ 260 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps)) 261 new_hwpipe = true; 262 263 /* 264 * (re)allocte hw pipe if we're either requesting for 2 hw pipes 265 * or we're switching from 2 hw pipes to 1 hw pipe because the 266 * new src_w can be supported by 1 hw pipe itself. 267 */ 268 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) || 269 (!need_right_hwpipe && mdp5_state->r_hwpipe)) 270 new_hwpipe = true; 271 272 if (mdp5_kms->smp) { 273 const struct mdp_format *format = 274 to_mdp_format(msm_framebuffer_format(state->fb)); 275 276 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, 277 state->src_w >> 16, false); 278 279 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg)) 280 new_hwpipe = true; 281 } 282 283 /* (re)assign hwpipe if needed, otherwise keep old one: */ 284 if (new_hwpipe) { 285 /* TODO maybe we want to re-assign hwpipe sometimes 286 * in cases when we no-longer need some caps to make 287 * it available for other planes? 288 */ 289 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe; 290 struct mdp5_hw_pipe *old_right_hwpipe = 291 mdp5_state->r_hwpipe; 292 struct mdp5_hw_pipe *new_hwpipe = NULL; 293 struct mdp5_hw_pipe *new_right_hwpipe = NULL; 294 295 ret = mdp5_pipe_assign(state->state, plane, caps, 296 blkcfg, &new_hwpipe, 297 need_right_hwpipe ? 298 &new_right_hwpipe : NULL); 299 if (ret) { 300 DBG("%s: failed to assign hwpipe(s)!", 301 plane->name); 302 return ret; 303 } 304 305 mdp5_state->hwpipe = new_hwpipe; 306 if (need_right_hwpipe) 307 mdp5_state->r_hwpipe = new_right_hwpipe; 308 else 309 /* 310 * set it to NULL so that the driver knows we 311 * don't have a right hwpipe when committing a 312 * new state 313 */ 314 mdp5_state->r_hwpipe = NULL; 315 316 317 mdp5_pipe_release(state->state, old_hwpipe); 318 mdp5_pipe_release(state->state, old_right_hwpipe); 319 } 320 } else { 321 mdp5_pipe_release(state->state, mdp5_state->hwpipe); 322 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe); 323 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL; 324 } 325 326 return 0; 327 } 328 329 static int mdp5_plane_atomic_check(struct drm_plane *plane, 330 struct drm_atomic_state *state) 331 { 332 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 333 plane); 334 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 335 plane); 336 struct drm_crtc *crtc; 337 struct drm_crtc_state *crtc_state; 338 339 crtc = new_plane_state->crtc ? new_plane_state->crtc : old_plane_state->crtc; 340 if (!crtc) 341 return 0; 342 343 crtc_state = drm_atomic_get_existing_crtc_state(state, 344 crtc); 345 if (WARN_ON(!crtc_state)) 346 return -EINVAL; 347 348 return mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state); 349 } 350 351 static void mdp5_plane_atomic_update(struct drm_plane *plane, 352 struct drm_atomic_state *state) 353 { 354 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 355 plane); 356 357 DBG("%s: update", plane->name); 358 359 if (plane_enabled(new_state)) { 360 int ret; 361 362 ret = mdp5_plane_mode_set(plane, 363 new_state->crtc, new_state->fb, 364 &new_state->src, &new_state->dst); 365 /* atomic_check should have ensured that this doesn't fail */ 366 WARN_ON(ret < 0); 367 } 368 } 369 370 static int mdp5_plane_atomic_async_check(struct drm_plane *plane, 371 struct drm_atomic_state *state) 372 { 373 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 374 plane); 375 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(new_plane_state); 376 struct drm_crtc_state *crtc_state; 377 int min_scale, max_scale; 378 int ret; 379 380 crtc_state = drm_atomic_get_existing_crtc_state(state, 381 new_plane_state->crtc); 382 if (WARN_ON(!crtc_state)) 383 return -EINVAL; 384 385 if (!crtc_state->active) 386 return -EINVAL; 387 388 mdp5_state = to_mdp5_plane_state(new_plane_state); 389 390 /* don't use fast path if we don't have a hwpipe allocated yet */ 391 if (!mdp5_state->hwpipe) 392 return -EINVAL; 393 394 /* only allow changing of position(crtc x/y or src x/y) in fast path */ 395 if (plane->state->crtc != new_plane_state->crtc || 396 plane->state->src_w != new_plane_state->src_w || 397 plane->state->src_h != new_plane_state->src_h || 398 plane->state->crtc_w != new_plane_state->crtc_w || 399 plane->state->crtc_h != new_plane_state->crtc_h || 400 !plane->state->fb || 401 plane->state->fb != new_plane_state->fb) 402 return -EINVAL; 403 404 min_scale = FRAC_16_16(1, 8); 405 max_scale = FRAC_16_16(8, 1); 406 407 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 408 min_scale, max_scale, 409 true, true); 410 if (ret) 411 return ret; 412 413 /* 414 * if the visibility of the plane changes (i.e, if the cursor is 415 * clipped out completely, we can't take the async path because 416 * we need to stage/unstage the plane from the Layer Mixer(s). We 417 * also assign/unassign the hwpipe(s) tied to the plane. We avoid 418 * taking the fast path for both these reasons. 419 */ 420 if (new_plane_state->visible != plane->state->visible) 421 return -EINVAL; 422 423 return 0; 424 } 425 426 static void mdp5_plane_atomic_async_update(struct drm_plane *plane, 427 struct drm_atomic_state *state) 428 { 429 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 430 plane); 431 struct drm_framebuffer *old_fb = plane->state->fb; 432 433 plane->state->src_x = new_state->src_x; 434 plane->state->src_y = new_state->src_y; 435 plane->state->crtc_x = new_state->crtc_x; 436 plane->state->crtc_y = new_state->crtc_y; 437 438 if (plane_enabled(new_state)) { 439 struct mdp5_ctl *ctl; 440 struct mdp5_pipeline *pipeline = 441 mdp5_crtc_get_pipeline(new_state->crtc); 442 int ret; 443 444 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb, 445 &new_state->src, &new_state->dst); 446 WARN_ON(ret < 0); 447 448 ctl = mdp5_crtc_get_ctl(new_state->crtc); 449 450 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true); 451 } 452 453 *to_mdp5_plane_state(plane->state) = 454 *to_mdp5_plane_state(new_state); 455 456 new_state->fb = old_fb; 457 } 458 459 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { 460 .prepare_fb = mdp5_plane_prepare_fb, 461 .cleanup_fb = mdp5_plane_cleanup_fb, 462 .atomic_check = mdp5_plane_atomic_check, 463 .atomic_update = mdp5_plane_atomic_update, 464 .atomic_async_check = mdp5_plane_atomic_async_check, 465 .atomic_async_update = mdp5_plane_atomic_async_update, 466 }; 467 468 static void set_scanout_locked(struct mdp5_kms *mdp5_kms, 469 enum mdp5_pipe pipe, 470 struct drm_framebuffer *fb) 471 { 472 struct msm_kms *kms = &mdp5_kms->base.base; 473 474 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), 475 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | 476 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1])); 477 478 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), 479 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) | 480 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); 481 482 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), 483 msm_framebuffer_iova(fb, kms->aspace, 0)); 484 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), 485 msm_framebuffer_iova(fb, kms->aspace, 1)); 486 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), 487 msm_framebuffer_iova(fb, kms->aspace, 2)); 488 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), 489 msm_framebuffer_iova(fb, kms->aspace, 3)); 490 } 491 492 /* Note: mdp5_plane->pipe_lock must be locked */ 493 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) 494 { 495 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & 496 ~MDP5_PIPE_OP_MODE_CSC_1_EN; 497 498 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); 499 } 500 501 /* Note: mdp5_plane->pipe_lock must be locked */ 502 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 503 struct csc_cfg *csc) 504 { 505 uint32_t i, mode = 0; /* RGB, no CSC */ 506 uint32_t *matrix; 507 508 if (unlikely(!csc)) 509 return; 510 511 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) 512 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV); 513 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) 514 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); 515 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN; 516 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); 517 518 matrix = csc->matrix; 519 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), 520 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) | 521 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1])); 522 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), 523 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) | 524 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3])); 525 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), 526 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) | 527 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5])); 528 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), 529 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) | 530 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7])); 531 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), 532 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8])); 533 534 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { 535 uint32_t *pre_clamp = csc->pre_clamp; 536 uint32_t *post_clamp = csc->post_clamp; 537 538 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), 539 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) | 540 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i])); 541 542 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), 543 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) | 544 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i])); 545 546 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), 547 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); 548 549 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), 550 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); 551 } 552 } 553 554 #define PHASE_STEP_SHIFT 21 555 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */ 556 557 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) 558 { 559 uint32_t unit; 560 561 if (src == 0 || dst == 0) 562 return -EINVAL; 563 564 /* 565 * PHASE_STEP_X/Y is coded on 26 bits (25:0), 566 * where 2^21 represents the unity "1" in fixed-point hardware design. 567 * This leaves 5 bits for the integer part (downscale case): 568 * -> maximum downscale ratio = 0b1_1111 = 31 569 */ 570 if (src > (dst * DOWN_SCALE_RATIO_MAX)) 571 return -EOVERFLOW; 572 573 unit = 1 << PHASE_STEP_SHIFT; 574 *out_phase = mult_frac(unit, src, dst); 575 576 return 0; 577 } 578 579 static int calc_scalex_steps(struct drm_plane *plane, 580 uint32_t pixel_format, uint32_t src, uint32_t dest, 581 uint32_t phasex_steps[COMP_MAX]) 582 { 583 const struct drm_format_info *info = drm_format_info(pixel_format); 584 struct mdp5_kms *mdp5_kms = get_kms(plane); 585 struct device *dev = mdp5_kms->dev->dev; 586 uint32_t phasex_step; 587 int ret; 588 589 ret = calc_phase_step(src, dest, &phasex_step); 590 if (ret) { 591 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); 592 return ret; 593 } 594 595 phasex_steps[COMP_0] = phasex_step; 596 phasex_steps[COMP_3] = phasex_step; 597 phasex_steps[COMP_1_2] = phasex_step / info->hsub; 598 599 return 0; 600 } 601 602 static int calc_scaley_steps(struct drm_plane *plane, 603 uint32_t pixel_format, uint32_t src, uint32_t dest, 604 uint32_t phasey_steps[COMP_MAX]) 605 { 606 const struct drm_format_info *info = drm_format_info(pixel_format); 607 struct mdp5_kms *mdp5_kms = get_kms(plane); 608 struct device *dev = mdp5_kms->dev->dev; 609 uint32_t phasey_step; 610 int ret; 611 612 ret = calc_phase_step(src, dest, &phasey_step); 613 if (ret) { 614 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); 615 return ret; 616 } 617 618 phasey_steps[COMP_0] = phasey_step; 619 phasey_steps[COMP_3] = phasey_step; 620 phasey_steps[COMP_1_2] = phasey_step / info->vsub; 621 622 return 0; 623 } 624 625 static uint32_t get_scale_config(const struct mdp_format *format, 626 uint32_t src, uint32_t dst, bool horz) 627 { 628 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 629 bool scaling = format->is_yuv ? true : (src != dst); 630 uint32_t sub; 631 uint32_t ya_filter, uv_filter; 632 bool yuv = format->is_yuv; 633 634 if (!scaling) 635 return 0; 636 637 if (yuv) { 638 sub = horz ? info->hsub : info->vsub; 639 uv_filter = ((src / sub) <= dst) ? 640 SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 641 } 642 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 643 644 if (horz) 645 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | 646 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | 647 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | 648 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); 649 else 650 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | 651 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | 652 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | 653 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); 654 } 655 656 static void calc_pixel_ext(const struct mdp_format *format, 657 uint32_t src, uint32_t dst, uint32_t phase_step[2], 658 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], 659 bool horz) 660 { 661 bool scaling = format->is_yuv ? true : (src != dst); 662 int i; 663 664 /* 665 * Note: 666 * We assume here that: 667 * 1. PCMN filter is used for downscale 668 * 2. bilinear filter is used for upscale 669 * 3. we are in a single pipe configuration 670 */ 671 672 for (i = 0; i < COMP_MAX; i++) { 673 pix_ext_edge1[i] = 0; 674 pix_ext_edge2[i] = scaling ? 1 : 0; 675 } 676 } 677 678 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 679 const struct mdp_format *format, 680 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], 681 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) 682 { 683 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 684 uint32_t lr, tb, req; 685 int i; 686 687 for (i = 0; i < COMP_MAX; i++) { 688 uint32_t roi_w = src_w; 689 uint32_t roi_h = src_h; 690 691 if (format->is_yuv && i == COMP_1_2) { 692 roi_w /= info->hsub; 693 roi_h /= info->vsub; 694 } 695 696 lr = (pe_left[i] >= 0) ? 697 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : 698 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); 699 700 lr |= (pe_right[i] >= 0) ? 701 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : 702 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); 703 704 tb = (pe_top[i] >= 0) ? 705 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : 706 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); 707 708 tb |= (pe_bottom[i] >= 0) ? 709 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : 710 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); 711 712 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + 713 pe_left[i] + pe_right[i]); 714 715 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + 716 pe_top[i] + pe_bottom[i]); 717 718 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); 719 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); 720 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); 721 722 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, 723 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), 724 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), 725 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), 726 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), 727 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); 728 729 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, 730 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), 731 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), 732 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), 733 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), 734 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); 735 } 736 } 737 738 struct pixel_ext { 739 int left[COMP_MAX]; 740 int right[COMP_MAX]; 741 int top[COMP_MAX]; 742 int bottom[COMP_MAX]; 743 }; 744 745 struct phase_step { 746 u32 x[COMP_MAX]; 747 u32 y[COMP_MAX]; 748 }; 749 750 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms, 751 struct mdp5_hw_pipe *hwpipe, 752 struct drm_framebuffer *fb, 753 struct phase_step *step, 754 struct pixel_ext *pe, 755 u32 scale_config, u32 hdecm, u32 vdecm, 756 bool hflip, bool vflip, 757 int crtc_x, int crtc_y, 758 unsigned int crtc_w, unsigned int crtc_h, 759 u32 src_img_w, u32 src_img_h, 760 u32 src_x, u32 src_y, 761 u32 src_w, u32 src_h) 762 { 763 enum mdp5_pipe pipe = hwpipe->pipe; 764 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT; 765 const struct mdp_format *format = 766 to_mdp_format(msm_framebuffer_format(fb)); 767 768 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), 769 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) | 770 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h)); 771 772 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), 773 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | 774 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); 775 776 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), 777 MDP5_PIPE_SRC_XY_X(src_x) | 778 MDP5_PIPE_SRC_XY_Y(src_y)); 779 780 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), 781 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | 782 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); 783 784 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), 785 MDP5_PIPE_OUT_XY_X(crtc_x) | 786 MDP5_PIPE_OUT_XY_Y(crtc_y)); 787 788 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), 789 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) | 790 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) | 791 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) | 792 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) | 793 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) | 794 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) | 795 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | 796 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) | 797 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) | 798 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample)); 799 800 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), 801 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) | 802 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) | 803 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) | 804 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3])); 805 806 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), 807 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | 808 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | 809 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | 810 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); 811 812 /* not using secure mode: */ 813 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); 814 815 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) 816 mdp5_write_pixel_ext(mdp5_kms, pipe, format, 817 src_w, pe->left, pe->right, 818 src_h, pe->top, pe->bottom); 819 820 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) { 821 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), 822 step->x[COMP_0]); 823 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), 824 step->y[COMP_0]); 825 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), 826 step->x[COMP_1_2]); 827 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), 828 step->y[COMP_1_2]); 829 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), 830 MDP5_PIPE_DECIMATION_VERT(vdecm) | 831 MDP5_PIPE_DECIMATION_HORZ(hdecm)); 832 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), 833 scale_config); 834 } 835 836 if (hwpipe->caps & MDP_PIPE_CAP_CSC) { 837 if (MDP_FORMAT_IS_YUV(format)) 838 csc_enable(mdp5_kms, pipe, 839 mdp_get_default_csc_cfg(CSC_YUV2RGB)); 840 else 841 csc_disable(mdp5_kms, pipe); 842 } 843 844 set_scanout_locked(mdp5_kms, pipe, fb); 845 } 846 847 static int mdp5_plane_mode_set(struct drm_plane *plane, 848 struct drm_crtc *crtc, struct drm_framebuffer *fb, 849 struct drm_rect *src, struct drm_rect *dest) 850 { 851 struct drm_plane_state *pstate = plane->state; 852 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; 853 struct mdp5_kms *mdp5_kms = get_kms(plane); 854 enum mdp5_pipe pipe = hwpipe->pipe; 855 struct mdp5_hw_pipe *right_hwpipe; 856 const struct mdp_format *format; 857 uint32_t nplanes, config = 0; 858 struct phase_step step = { { 0 } }; 859 struct pixel_ext pe = { { 0 } }; 860 uint32_t hdecm = 0, vdecm = 0; 861 uint32_t pix_format; 862 unsigned int rotation; 863 bool vflip, hflip; 864 int crtc_x, crtc_y; 865 unsigned int crtc_w, crtc_h; 866 uint32_t src_x, src_y; 867 uint32_t src_w, src_h; 868 uint32_t src_img_w, src_img_h; 869 int ret; 870 871 nplanes = fb->format->num_planes; 872 873 /* bad formats should already be rejected: */ 874 if (WARN_ON(nplanes > pipe2nclients(pipe))) 875 return -EINVAL; 876 877 format = to_mdp_format(msm_framebuffer_format(fb)); 878 pix_format = format->base.pixel_format; 879 880 src_x = src->x1; 881 src_y = src->y1; 882 src_w = drm_rect_width(src); 883 src_h = drm_rect_height(src); 884 885 crtc_x = dest->x1; 886 crtc_y = dest->y1; 887 crtc_w = drm_rect_width(dest); 888 crtc_h = drm_rect_height(dest); 889 890 /* src values are in Q16 fixed point, convert to integer: */ 891 src_x = src_x >> 16; 892 src_y = src_y >> 16; 893 src_w = src_w >> 16; 894 src_h = src_h >> 16; 895 896 src_img_w = min(fb->width, src_w); 897 src_img_h = min(fb->height, src_h); 898 899 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name, 900 fb->base.id, src_x, src_y, src_w, src_h, 901 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); 902 903 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe; 904 if (right_hwpipe) { 905 /* 906 * if the plane comprises of 2 hw pipes, assume that the width 907 * is split equally across them. The only parameters that varies 908 * between the 2 pipes are src_x and crtc_x 909 */ 910 crtc_w /= 2; 911 src_w /= 2; 912 src_img_w /= 2; 913 } 914 915 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); 916 if (ret) 917 return ret; 918 919 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y); 920 if (ret) 921 return ret; 922 923 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) { 924 calc_pixel_ext(format, src_w, crtc_w, step.x, 925 pe.left, pe.right, true); 926 calc_pixel_ext(format, src_h, crtc_h, step.y, 927 pe.top, pe.bottom, false); 928 } 929 930 /* TODO calc hdecm, vdecm */ 931 932 /* SCALE is used to both scale and up-sample chroma components */ 933 config |= get_scale_config(format, src_w, crtc_w, true); 934 config |= get_scale_config(format, src_h, crtc_h, false); 935 DBG("scale config = %x", config); 936 937 rotation = drm_rotation_simplify(pstate->rotation, 938 DRM_MODE_ROTATE_0 | 939 DRM_MODE_REFLECT_X | 940 DRM_MODE_REFLECT_Y); 941 hflip = !!(rotation & DRM_MODE_REFLECT_X); 942 vflip = !!(rotation & DRM_MODE_REFLECT_Y); 943 944 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe, 945 config, hdecm, vdecm, hflip, vflip, 946 crtc_x, crtc_y, crtc_w, crtc_h, 947 src_img_w, src_img_h, 948 src_x, src_y, src_w, src_h); 949 if (right_hwpipe) 950 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, 951 config, hdecm, vdecm, hflip, vflip, 952 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h, 953 src_img_w, src_img_h, 954 src_x + src_w, src_y, src_w, src_h); 955 956 return ret; 957 } 958 959 /* 960 * Use this func and the one below only after the atomic state has been 961 * successfully swapped 962 */ 963 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) 964 { 965 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 966 967 if (WARN_ON(!pstate->hwpipe)) 968 return SSPP_NONE; 969 970 return pstate->hwpipe->pipe; 971 } 972 973 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane) 974 { 975 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 976 977 if (!pstate->r_hwpipe) 978 return SSPP_NONE; 979 980 return pstate->r_hwpipe->pipe; 981 } 982 983 uint32_t mdp5_plane_get_flush(struct drm_plane *plane) 984 { 985 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 986 u32 mask; 987 988 if (WARN_ON(!pstate->hwpipe)) 989 return 0; 990 991 mask = pstate->hwpipe->flush_mask; 992 993 if (pstate->r_hwpipe) 994 mask |= pstate->r_hwpipe->flush_mask; 995 996 return mask; 997 } 998 999 /* initialize plane */ 1000 struct drm_plane *mdp5_plane_init(struct drm_device *dev, 1001 enum drm_plane_type type) 1002 { 1003 struct drm_plane *plane = NULL; 1004 struct mdp5_plane *mdp5_plane; 1005 int ret; 1006 1007 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL); 1008 if (!mdp5_plane) { 1009 ret = -ENOMEM; 1010 goto fail; 1011 } 1012 1013 plane = &mdp5_plane->base; 1014 1015 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats, 1016 ARRAY_SIZE(mdp5_plane->formats), false); 1017 1018 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs, 1019 mdp5_plane->formats, mdp5_plane->nformats, 1020 NULL, type, NULL); 1021 if (ret) 1022 goto fail; 1023 1024 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs); 1025 1026 mdp5_plane_install_properties(plane, &plane->base); 1027 1028 drm_plane_enable_fb_damage_clips(plane); 1029 1030 return plane; 1031 1032 fail: 1033 if (plane) 1034 mdp5_plane_destroy(plane); 1035 1036 return ERR_PTR(ret); 1037 } 1038