1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MDP5_KMS_H__ 19 #define __MDP5_KMS_H__ 20 21 #include "msm_drv.h" 22 #include "msm_kms.h" 23 #include "disp/mdp_kms.h" 24 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */ 25 #include "mdp5.xml.h" 26 #include "mdp5_pipe.h" 27 #include "mdp5_mixer.h" 28 #include "mdp5_ctl.h" 29 #include "mdp5_smp.h" 30 31 struct mdp5_state; 32 33 struct mdp5_kms { 34 struct mdp_kms base; 35 36 struct drm_device *dev; 37 38 struct platform_device *pdev; 39 40 unsigned num_hwpipes; 41 struct mdp5_hw_pipe *hwpipes[SSPP_MAX]; 42 43 unsigned num_hwmixers; 44 struct mdp5_hw_mixer *hwmixers[8]; 45 46 unsigned num_intfs; 47 struct mdp5_interface *intfs[5]; 48 49 struct mdp5_cfg_handler *cfg; 50 uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */ 51 52 /** 53 * Global atomic state. Do not access directly, use mdp5_get_state() 54 */ 55 struct mdp5_state *state; 56 struct drm_modeset_lock state_lock; 57 58 struct mdp5_smp *smp; 59 struct mdp5_ctl_manager *ctlm; 60 61 /* io/register spaces: */ 62 void __iomem *mmio; 63 64 struct clk *axi_clk; 65 struct clk *ahb_clk; 66 struct clk *core_clk; 67 struct clk *lut_clk; 68 struct clk *vsync_clk; 69 70 /* 71 * lock to protect access to global resources: ie., following register: 72 * - REG_MDP5_DISP_INTF_SEL 73 */ 74 spinlock_t resource_lock; 75 76 bool rpm_enabled; 77 78 struct mdp_irq error_handler; 79 80 int enable_count; 81 }; 82 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) 83 84 /* Global atomic state for tracking resources that are shared across 85 * multiple kms objects (planes/crtcs/etc). 86 * 87 * For atomic updates which require modifying global state, 88 */ 89 struct mdp5_state { 90 struct mdp5_hw_pipe_state hwpipe; 91 struct mdp5_hw_mixer_state hwmixer; 92 struct mdp5_smp_state smp; 93 }; 94 95 struct mdp5_state *__must_check 96 mdp5_get_state(struct drm_atomic_state *s); 97 98 /* Atomic plane state. Subclasses the base drm_plane_state in order to 99 * track assigned hwpipe and hw specific state. 100 */ 101 struct mdp5_plane_state { 102 struct drm_plane_state base; 103 104 struct mdp5_hw_pipe *hwpipe; 105 struct mdp5_hw_pipe *r_hwpipe; /* right hwpipe */ 106 107 /* aligned with property */ 108 uint8_t premultiplied; 109 uint8_t zpos; 110 uint8_t alpha; 111 112 /* assigned by crtc blender */ 113 enum mdp_mixer_stage_id stage; 114 }; 115 #define to_mdp5_plane_state(x) \ 116 container_of(x, struct mdp5_plane_state, base) 117 118 struct mdp5_pipeline { 119 struct mdp5_interface *intf; 120 struct mdp5_hw_mixer *mixer; 121 struct mdp5_hw_mixer *r_mixer; /* right mixer */ 122 }; 123 124 struct mdp5_crtc_state { 125 struct drm_crtc_state base; 126 127 struct mdp5_ctl *ctl; 128 struct mdp5_pipeline pipeline; 129 130 /* these are derivatives of intf/mixer state in mdp5_pipeline */ 131 u32 vblank_irqmask; 132 u32 err_irqmask; 133 u32 pp_done_irqmask; 134 135 bool cmd_mode; 136 137 /* should we not write CTL[n].START register on flush? If the 138 * encoder has changed this is set to true, since encoder->enable() 139 * is called after crtc state is committed, but we only want to 140 * write the CTL[n].START register once. This lets us defer 141 * writing CTL[n].START until encoder->enable() 142 */ 143 bool defer_start; 144 }; 145 #define to_mdp5_crtc_state(x) \ 146 container_of(x, struct mdp5_crtc_state, base) 147 148 enum mdp5_intf_mode { 149 MDP5_INTF_MODE_NONE = 0, 150 151 /* Modes used for DSI interface (INTF_DSI type): */ 152 MDP5_INTF_DSI_MODE_VIDEO, 153 MDP5_INTF_DSI_MODE_COMMAND, 154 155 /* Modes used for WB interface (INTF_WB type): */ 156 MDP5_INTF_WB_MODE_BLOCK, 157 MDP5_INTF_WB_MODE_LINE, 158 }; 159 160 struct mdp5_interface { 161 int idx; 162 int num; /* display interface number */ 163 enum mdp5_intf_type type; 164 enum mdp5_intf_mode mode; 165 }; 166 167 struct mdp5_encoder { 168 struct drm_encoder base; 169 spinlock_t intf_lock; /* protect REG_MDP5_INTF_* registers */ 170 bool enabled; 171 uint32_t bsc; 172 173 struct mdp5_interface *intf; 174 struct mdp5_ctl *ctl; 175 }; 176 #define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base) 177 178 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) 179 { 180 WARN_ON(mdp5_kms->enable_count <= 0); 181 msm_writel(data, mdp5_kms->mmio + reg); 182 } 183 184 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg) 185 { 186 WARN_ON(mdp5_kms->enable_count <= 0); 187 return msm_readl(mdp5_kms->mmio + reg); 188 } 189 190 static inline const char *stage2name(enum mdp_mixer_stage_id stage) 191 { 192 static const char *names[] = { 193 #define NAME(n) [n] = #n 194 NAME(STAGE_UNUSED), NAME(STAGE_BASE), 195 NAME(STAGE0), NAME(STAGE1), NAME(STAGE2), 196 NAME(STAGE3), NAME(STAGE4), NAME(STAGE6), 197 #undef NAME 198 }; 199 return names[stage]; 200 } 201 202 static inline const char *pipe2name(enum mdp5_pipe pipe) 203 { 204 static const char *names[] = { 205 #define NAME(n) [SSPP_ ## n] = #n 206 NAME(VIG0), NAME(VIG1), NAME(VIG2), 207 NAME(RGB0), NAME(RGB1), NAME(RGB2), 208 NAME(DMA0), NAME(DMA1), 209 NAME(VIG3), NAME(RGB3), 210 NAME(CURSOR0), NAME(CURSOR1), 211 #undef NAME 212 }; 213 return names[pipe]; 214 } 215 216 static inline int pipe2nclients(enum mdp5_pipe pipe) 217 { 218 switch (pipe) { 219 case SSPP_RGB0: 220 case SSPP_RGB1: 221 case SSPP_RGB2: 222 case SSPP_RGB3: 223 return 1; 224 default: 225 return 3; 226 } 227 } 228 229 static inline uint32_t intf2err(int intf_num) 230 { 231 switch (intf_num) { 232 case 0: return MDP5_IRQ_INTF0_UNDER_RUN; 233 case 1: return MDP5_IRQ_INTF1_UNDER_RUN; 234 case 2: return MDP5_IRQ_INTF2_UNDER_RUN; 235 case 3: return MDP5_IRQ_INTF3_UNDER_RUN; 236 default: return 0; 237 } 238 } 239 240 static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer, 241 struct mdp5_interface *intf) 242 { 243 /* 244 * In case of DSI Command Mode, the Ping Pong's read pointer IRQ 245 * acts as a Vblank signal. The Ping Pong buffer used is bound to 246 * layer mixer. 247 */ 248 249 if ((intf->type == INTF_DSI) && 250 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) 251 return MDP5_IRQ_PING_PONG_0_RD_PTR << mixer->pp; 252 253 if (intf->type == INTF_WB) 254 return MDP5_IRQ_WB_2_DONE; 255 256 switch (intf->num) { 257 case 0: return MDP5_IRQ_INTF0_VSYNC; 258 case 1: return MDP5_IRQ_INTF1_VSYNC; 259 case 2: return MDP5_IRQ_INTF2_VSYNC; 260 case 3: return MDP5_IRQ_INTF3_VSYNC; 261 default: return 0; 262 } 263 } 264 265 static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer) 266 { 267 return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp; 268 } 269 270 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, 271 uint32_t old_irqmask); 272 void mdp5_irq_preinstall(struct msm_kms *kms); 273 int mdp5_irq_postinstall(struct msm_kms *kms); 274 void mdp5_irq_uninstall(struct msm_kms *kms); 275 irqreturn_t mdp5_irq(struct msm_kms *kms); 276 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc); 277 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc); 278 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms); 279 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms); 280 281 uint32_t mdp5_plane_get_flush(struct drm_plane *plane); 282 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane); 283 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane); 284 struct drm_plane *mdp5_plane_init(struct drm_device *dev, 285 enum drm_plane_type type); 286 287 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc); 288 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc); 289 290 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc); 291 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc); 292 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc); 293 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc); 294 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, 295 struct drm_plane *plane, 296 struct drm_plane *cursor_plane, int id); 297 298 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, 299 struct mdp5_interface *intf, struct mdp5_ctl *ctl); 300 int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, 301 struct drm_encoder *slave_encoder); 302 void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode); 303 int mdp5_encoder_get_linecount(struct drm_encoder *encoder); 304 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder); 305 306 #ifdef CONFIG_DRM_MSM_DSI 307 void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder, 308 struct drm_display_mode *mode, 309 struct drm_display_mode *adjusted_mode); 310 void mdp5_cmd_encoder_disable(struct drm_encoder *encoder); 311 void mdp5_cmd_encoder_enable(struct drm_encoder *encoder); 312 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, 313 struct drm_encoder *slave_encoder); 314 #else 315 static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder, 316 struct drm_display_mode *mode, 317 struct drm_display_mode *adjusted_mode) 318 { 319 } 320 static inline void mdp5_cmd_encoder_disable(struct drm_encoder *encoder) 321 { 322 } 323 static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder) 324 { 325 } 326 static inline int mdp5_cmd_encoder_set_split_display( 327 struct drm_encoder *encoder, struct drm_encoder *slave_encoder) 328 { 329 return -EINVAL; 330 } 331 #endif 332 333 #endif /* __MDP5_KMS_H__ */ 334