1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/of_irq.h> 11 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_vblank.h> 16 17 #include "msm_drv.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 #include "mdp5_kms.h" 21 22 static int mdp5_hw_init(struct msm_kms *kms) 23 { 24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 25 struct device *dev = &mdp5_kms->pdev->dev; 26 unsigned long flags; 27 28 pm_runtime_get_sync(dev); 29 30 /* Magic unknown register writes: 31 * 32 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) 34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) 35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) 36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) 37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) 38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) 39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) 40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) 41 * 42 * Downstream fbdev driver gets these register offsets/values 43 * from DT.. not really sure what these registers are or if 44 * different values for different boards/SoC's, etc. I guess 45 * they are the golden registers. 46 * 47 * Not setting these does not seem to cause any problem. But 48 * we may be getting lucky with the bootloader initializing 49 * them for us. OTOH, if we can always count on the bootloader 50 * setting the golden registers, then perhaps we don't need to 51 * care. 52 */ 53 54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); 55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); 56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); 57 58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); 59 60 pm_runtime_put_sync(dev); 61 62 return 0; 63 } 64 65 /* Global/shared object state funcs */ 66 67 /* 68 * This is a helper that returns the private state currently in operation. 69 * Note that this would return the "old_state" if called in the atomic check 70 * path, and the "new_state" after the atomic swap has been done. 71 */ 72 struct mdp5_global_state * 73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) 74 { 75 return to_mdp5_global_state(mdp5_kms->glob_state.state); 76 } 77 78 /* 79 * This acquires the modeset lock set aside for global state, creates 80 * a new duplicated private object state. 81 */ 82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) 83 { 84 struct msm_drm_private *priv = s->dev->dev_private; 85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 86 struct drm_private_state *priv_state; 87 int ret; 88 89 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx); 90 if (ret) 91 return ERR_PTR(ret); 92 93 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); 94 if (IS_ERR(priv_state)) 95 return ERR_CAST(priv_state); 96 97 return to_mdp5_global_state(priv_state); 98 } 99 100 static struct drm_private_state * 101 mdp5_global_duplicate_state(struct drm_private_obj *obj) 102 { 103 struct mdp5_global_state *state; 104 105 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 106 if (!state) 107 return NULL; 108 109 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 110 111 return &state->base; 112 } 113 114 static void mdp5_global_destroy_state(struct drm_private_obj *obj, 115 struct drm_private_state *state) 116 { 117 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); 118 119 kfree(mdp5_state); 120 } 121 122 static const struct drm_private_state_funcs mdp5_global_state_funcs = { 123 .atomic_duplicate_state = mdp5_global_duplicate_state, 124 .atomic_destroy_state = mdp5_global_destroy_state, 125 }; 126 127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) 128 { 129 struct mdp5_global_state *state; 130 131 drm_modeset_lock_init(&mdp5_kms->glob_state_lock); 132 133 state = kzalloc(sizeof(*state), GFP_KERNEL); 134 if (!state) 135 return -ENOMEM; 136 137 state->mdp5_kms = mdp5_kms; 138 139 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, 140 &state->base, 141 &mdp5_global_state_funcs); 142 return 0; 143 } 144 145 static void mdp5_enable_commit(struct msm_kms *kms) 146 { 147 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 148 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 149 } 150 151 static void mdp5_disable_commit(struct msm_kms *kms) 152 { 153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 154 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 155 } 156 157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 158 { 159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 160 struct mdp5_global_state *global_state; 161 162 global_state = mdp5_get_existing_global_state(mdp5_kms); 163 164 if (mdp5_kms->smp) 165 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp); 166 } 167 168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 169 { 170 /* TODO */ 171 } 172 173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 174 { 175 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 176 struct drm_crtc *crtc; 177 178 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask) 179 mdp5_crtc_wait_for_commit_done(crtc); 180 } 181 182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 183 { 184 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 185 struct mdp5_global_state *global_state; 186 187 global_state = mdp5_get_existing_global_state(mdp5_kms); 188 189 if (mdp5_kms->smp) 190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); 191 } 192 193 static int mdp5_set_split_display(struct msm_kms *kms, 194 struct drm_encoder *encoder, 195 struct drm_encoder *slave_encoder, 196 bool is_cmd_mode) 197 { 198 if (is_cmd_mode) 199 return mdp5_cmd_encoder_set_split_display(encoder, 200 slave_encoder); 201 else 202 return mdp5_vid_encoder_set_split_display(encoder, 203 slave_encoder); 204 } 205 206 static void mdp5_destroy(struct mdp5_kms *mdp5_kms); 207 208 static void mdp5_kms_destroy(struct msm_kms *kms) 209 { 210 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 211 struct msm_gem_address_space *aspace = kms->aspace; 212 int i; 213 214 for (i = 0; i < mdp5_kms->num_hwmixers; i++) 215 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]); 216 217 for (i = 0; i < mdp5_kms->num_hwpipes; i++) 218 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); 219 220 if (aspace) { 221 aspace->mmu->funcs->detach(aspace->mmu); 222 msm_gem_address_space_put(aspace); 223 } 224 225 mdp_kms_destroy(&mdp5_kms->base); 226 mdp5_destroy(mdp5_kms); 227 } 228 229 #ifdef CONFIG_DEBUG_FS 230 static int smp_show(struct seq_file *m, void *arg) 231 { 232 struct drm_info_node *node = (struct drm_info_node *) m->private; 233 struct drm_device *dev = node->minor->dev; 234 struct msm_drm_private *priv = dev->dev_private; 235 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 236 struct drm_printer p = drm_seq_file_printer(m); 237 238 if (!mdp5_kms->smp) { 239 drm_printf(&p, "no SMP pool\n"); 240 return 0; 241 } 242 243 mdp5_smp_dump(mdp5_kms->smp, &p); 244 245 return 0; 246 } 247 248 static struct drm_info_list mdp5_debugfs_list[] = { 249 {"smp", smp_show }, 250 }; 251 252 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 253 { 254 drm_debugfs_create_files(mdp5_debugfs_list, 255 ARRAY_SIZE(mdp5_debugfs_list), 256 minor->debugfs_root, minor); 257 258 return 0; 259 } 260 #endif 261 262 static const struct mdp_kms_funcs kms_funcs = { 263 .base = { 264 .hw_init = mdp5_hw_init, 265 .irq_preinstall = mdp5_irq_preinstall, 266 .irq_postinstall = mdp5_irq_postinstall, 267 .irq_uninstall = mdp5_irq_uninstall, 268 .irq = mdp5_irq, 269 .enable_vblank = mdp5_enable_vblank, 270 .disable_vblank = mdp5_disable_vblank, 271 .flush_commit = mdp5_flush_commit, 272 .enable_commit = mdp5_enable_commit, 273 .disable_commit = mdp5_disable_commit, 274 .prepare_commit = mdp5_prepare_commit, 275 .wait_flush = mdp5_wait_flush, 276 .complete_commit = mdp5_complete_commit, 277 .get_format = mdp_get_format, 278 .set_split_display = mdp5_set_split_display, 279 .destroy = mdp5_kms_destroy, 280 #ifdef CONFIG_DEBUG_FS 281 .debugfs_init = mdp5_kms_debugfs_init, 282 #endif 283 }, 284 .set_irqmask = mdp5_set_irqmask, 285 }; 286 287 static int mdp5_disable(struct mdp5_kms *mdp5_kms) 288 { 289 DBG(""); 290 291 mdp5_kms->enable_count--; 292 WARN_ON(mdp5_kms->enable_count < 0); 293 294 clk_disable_unprepare(mdp5_kms->tbu_rt_clk); 295 clk_disable_unprepare(mdp5_kms->tbu_clk); 296 clk_disable_unprepare(mdp5_kms->ahb_clk); 297 clk_disable_unprepare(mdp5_kms->axi_clk); 298 clk_disable_unprepare(mdp5_kms->core_clk); 299 clk_disable_unprepare(mdp5_kms->lut_clk); 300 301 return 0; 302 } 303 304 static int mdp5_enable(struct mdp5_kms *mdp5_kms) 305 { 306 DBG(""); 307 308 mdp5_kms->enable_count++; 309 310 clk_prepare_enable(mdp5_kms->ahb_clk); 311 clk_prepare_enable(mdp5_kms->axi_clk); 312 clk_prepare_enable(mdp5_kms->core_clk); 313 clk_prepare_enable(mdp5_kms->lut_clk); 314 clk_prepare_enable(mdp5_kms->tbu_clk); 315 clk_prepare_enable(mdp5_kms->tbu_rt_clk); 316 317 return 0; 318 } 319 320 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 321 struct mdp5_interface *intf, 322 struct mdp5_ctl *ctl) 323 { 324 struct drm_device *dev = mdp5_kms->dev; 325 struct drm_encoder *encoder; 326 327 encoder = mdp5_encoder_init(dev, intf, ctl); 328 if (IS_ERR(encoder)) { 329 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n"); 330 return encoder; 331 } 332 333 return encoder; 334 } 335 336 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 337 { 338 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; 339 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); 340 int id = 0, i; 341 342 for (i = 0; i < intf_cnt; i++) { 343 if (intfs[i] == INTF_DSI) { 344 if (intf_num == i) 345 return id; 346 347 id++; 348 } 349 } 350 351 return -EINVAL; 352 } 353 354 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, 355 struct mdp5_interface *intf) 356 { 357 struct drm_device *dev = mdp5_kms->dev; 358 struct msm_drm_private *priv = dev->dev_private; 359 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; 360 struct mdp5_ctl *ctl; 361 struct drm_encoder *encoder; 362 int ret = 0; 363 364 switch (intf->type) { 365 case INTF_eDP: 366 DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num); 367 break; 368 case INTF_HDMI: 369 if (!priv->hdmi) 370 break; 371 372 ctl = mdp5_ctlm_request(ctlm, intf->num); 373 if (!ctl) { 374 ret = -EINVAL; 375 break; 376 } 377 378 encoder = construct_encoder(mdp5_kms, intf, ctl); 379 if (IS_ERR(encoder)) { 380 ret = PTR_ERR(encoder); 381 break; 382 } 383 384 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 385 break; 386 case INTF_DSI: 387 { 388 const struct mdp5_cfg_hw *hw_cfg = 389 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 390 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); 391 392 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { 393 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", 394 intf->num); 395 ret = -EINVAL; 396 break; 397 } 398 399 if (!priv->dsi[dsi_id]) 400 break; 401 402 ctl = mdp5_ctlm_request(ctlm, intf->num); 403 if (!ctl) { 404 ret = -EINVAL; 405 break; 406 } 407 408 encoder = construct_encoder(mdp5_kms, intf, ctl); 409 if (IS_ERR(encoder)) { 410 ret = PTR_ERR(encoder); 411 break; 412 } 413 414 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 415 if (!ret) 416 mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_id])); 417 418 break; 419 } 420 default: 421 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type); 422 ret = -EINVAL; 423 break; 424 } 425 426 return ret; 427 } 428 429 static int modeset_init(struct mdp5_kms *mdp5_kms) 430 { 431 struct drm_device *dev = mdp5_kms->dev; 432 struct msm_drm_private *priv = dev->dev_private; 433 unsigned int num_crtcs; 434 int i, ret, pi = 0, ci = 0; 435 struct drm_plane *primary[MAX_BASES] = { NULL }; 436 struct drm_plane *cursor[MAX_BASES] = { NULL }; 437 struct drm_encoder *encoder; 438 unsigned int num_encoders; 439 440 /* 441 * Construct encoders and modeset initialize connector devices 442 * for each external display interface. 443 */ 444 for (i = 0; i < mdp5_kms->num_intfs; i++) { 445 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); 446 if (ret) 447 goto fail; 448 } 449 450 num_encoders = 0; 451 drm_for_each_encoder(encoder, dev) 452 num_encoders++; 453 454 /* 455 * We should ideally have less number of encoders (set up by parsing 456 * the MDP5 interfaces) than the number of layer mixers present in HW, 457 * but let's be safe here anyway 458 */ 459 num_crtcs = min(num_encoders, mdp5_kms->num_hwmixers); 460 461 /* 462 * Construct planes equaling the number of hw pipes, and CRTCs for the 463 * N encoders set up by the driver. The first N planes become primary 464 * planes for the CRTCs, with the remainder as overlay planes: 465 */ 466 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { 467 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; 468 struct drm_plane *plane; 469 enum drm_plane_type type; 470 471 if (i < num_crtcs) 472 type = DRM_PLANE_TYPE_PRIMARY; 473 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR) 474 type = DRM_PLANE_TYPE_CURSOR; 475 else 476 type = DRM_PLANE_TYPE_OVERLAY; 477 478 plane = mdp5_plane_init(dev, type); 479 if (IS_ERR(plane)) { 480 ret = PTR_ERR(plane); 481 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret); 482 goto fail; 483 } 484 485 if (type == DRM_PLANE_TYPE_PRIMARY) 486 primary[pi++] = plane; 487 if (type == DRM_PLANE_TYPE_CURSOR) 488 cursor[ci++] = plane; 489 } 490 491 for (i = 0; i < num_crtcs; i++) { 492 struct drm_crtc *crtc; 493 494 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); 495 if (IS_ERR(crtc)) { 496 ret = PTR_ERR(crtc); 497 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); 498 goto fail; 499 } 500 priv->crtcs[priv->num_crtcs++] = crtc; 501 } 502 503 /* 504 * Now that we know the number of crtcs we've created, set the possible 505 * crtcs for the encoders 506 */ 507 drm_for_each_encoder(encoder, dev) 508 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 509 510 return 0; 511 512 fail: 513 return ret; 514 } 515 516 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, 517 u32 *major, u32 *minor) 518 { 519 struct device *dev = &mdp5_kms->pdev->dev; 520 u32 version; 521 522 pm_runtime_get_sync(dev); 523 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); 524 pm_runtime_put_sync(dev); 525 526 *major = FIELD(version, MDP5_HW_VERSION_MAJOR); 527 *minor = FIELD(version, MDP5_HW_VERSION_MINOR); 528 529 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); 530 } 531 532 static int get_clk(struct platform_device *pdev, struct clk **clkp, 533 const char *name, bool mandatory) 534 { 535 struct device *dev = &pdev->dev; 536 struct clk *clk = msm_clk_get(pdev, name); 537 if (IS_ERR(clk) && mandatory) { 538 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 539 return PTR_ERR(clk); 540 } 541 if (IS_ERR(clk)) 542 DBG("skipping %s", name); 543 else 544 *clkp = clk; 545 546 return 0; 547 } 548 549 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev); 550 551 static int mdp5_kms_init(struct drm_device *dev) 552 { 553 struct msm_drm_private *priv = dev->dev_private; 554 struct platform_device *pdev; 555 struct mdp5_kms *mdp5_kms; 556 struct mdp5_cfg *config; 557 struct msm_kms *kms; 558 struct msm_gem_address_space *aspace; 559 int irq, i, ret; 560 561 ret = mdp5_init(to_platform_device(dev->dev), dev); 562 if (ret) 563 return ret; 564 565 /* priv->kms would have been populated by the MDP5 driver */ 566 kms = priv->kms; 567 if (!kms) 568 return -ENOMEM; 569 570 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 571 pdev = mdp5_kms->pdev; 572 573 ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs); 574 if (ret) { 575 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n"); 576 goto fail; 577 } 578 579 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 580 if (!irq) { 581 ret = -EINVAL; 582 DRM_DEV_ERROR(&pdev->dev, "failed to get irq\n"); 583 goto fail; 584 } 585 586 kms->irq = irq; 587 588 config = mdp5_cfg_get_config(mdp5_kms->cfg); 589 590 /* make sure things are off before attaching iommu (bootloader could 591 * have left things on, in which case we'll start getting faults if 592 * we don't disable): 593 */ 594 pm_runtime_get_sync(&pdev->dev); 595 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 596 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || 597 !config->hw->intf.base[i]) 598 continue; 599 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 600 601 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); 602 } 603 mdelay(16); 604 605 aspace = msm_kms_init_aspace(mdp5_kms->dev); 606 if (IS_ERR(aspace)) { 607 ret = PTR_ERR(aspace); 608 goto fail; 609 } 610 611 kms->aspace = aspace; 612 613 pm_runtime_put_sync(&pdev->dev); 614 615 ret = modeset_init(mdp5_kms); 616 if (ret) { 617 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret); 618 goto fail; 619 } 620 621 dev->mode_config.min_width = 0; 622 dev->mode_config.min_height = 0; 623 dev->mode_config.max_width = 0xffff; 624 dev->mode_config.max_height = 0xffff; 625 626 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */ 627 dev->vblank_disable_immediate = true; 628 629 return 0; 630 fail: 631 if (kms) 632 mdp5_kms_destroy(kms); 633 634 return ret; 635 } 636 637 static void mdp5_destroy(struct mdp5_kms *mdp5_kms) 638 { 639 int i; 640 641 if (mdp5_kms->ctlm) 642 mdp5_ctlm_destroy(mdp5_kms->ctlm); 643 if (mdp5_kms->smp) 644 mdp5_smp_destroy(mdp5_kms->smp); 645 if (mdp5_kms->cfg) 646 mdp5_cfg_destroy(mdp5_kms->cfg); 647 648 for (i = 0; i < mdp5_kms->num_intfs; i++) 649 kfree(mdp5_kms->intfs[i]); 650 651 if (mdp5_kms->rpm_enabled) 652 pm_runtime_disable(&mdp5_kms->pdev->dev); 653 654 drm_atomic_private_obj_fini(&mdp5_kms->glob_state); 655 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); 656 } 657 658 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, 659 const enum mdp5_pipe *pipes, const uint32_t *offsets, 660 uint32_t caps) 661 { 662 struct drm_device *dev = mdp5_kms->dev; 663 int i, ret; 664 665 for (i = 0; i < cnt; i++) { 666 struct mdp5_hw_pipe *hwpipe; 667 668 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); 669 if (IS_ERR(hwpipe)) { 670 ret = PTR_ERR(hwpipe); 671 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n", 672 pipe2name(pipes[i]), ret); 673 return ret; 674 } 675 hwpipe->idx = mdp5_kms->num_hwpipes; 676 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; 677 } 678 679 return 0; 680 } 681 682 static int hwpipe_init(struct mdp5_kms *mdp5_kms) 683 { 684 static const enum mdp5_pipe rgb_planes[] = { 685 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, 686 }; 687 static const enum mdp5_pipe vig_planes[] = { 688 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, 689 }; 690 static const enum mdp5_pipe dma_planes[] = { 691 SSPP_DMA0, SSPP_DMA1, 692 }; 693 static const enum mdp5_pipe cursor_planes[] = { 694 SSPP_CURSOR0, SSPP_CURSOR1, 695 }; 696 const struct mdp5_cfg_hw *hw_cfg; 697 int ret; 698 699 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 700 701 /* Construct RGB pipes: */ 702 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, 703 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); 704 if (ret) 705 return ret; 706 707 /* Construct video (VIG) pipes: */ 708 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, 709 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); 710 if (ret) 711 return ret; 712 713 /* Construct DMA pipes: */ 714 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, 715 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); 716 if (ret) 717 return ret; 718 719 /* Construct cursor pipes: */ 720 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, 721 cursor_planes, hw_cfg->pipe_cursor.base, 722 hw_cfg->pipe_cursor.caps); 723 if (ret) 724 return ret; 725 726 return 0; 727 } 728 729 static int hwmixer_init(struct mdp5_kms *mdp5_kms) 730 { 731 struct drm_device *dev = mdp5_kms->dev; 732 const struct mdp5_cfg_hw *hw_cfg; 733 int i, ret; 734 735 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 736 737 for (i = 0; i < hw_cfg->lm.count; i++) { 738 struct mdp5_hw_mixer *mixer; 739 740 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]); 741 if (IS_ERR(mixer)) { 742 ret = PTR_ERR(mixer); 743 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n", 744 i, ret); 745 return ret; 746 } 747 748 mixer->idx = mdp5_kms->num_hwmixers; 749 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; 750 } 751 752 return 0; 753 } 754 755 static int interface_init(struct mdp5_kms *mdp5_kms) 756 { 757 struct drm_device *dev = mdp5_kms->dev; 758 const struct mdp5_cfg_hw *hw_cfg; 759 const enum mdp5_intf_type *intf_types; 760 int i; 761 762 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 763 intf_types = hw_cfg->intf.connect; 764 765 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 766 struct mdp5_interface *intf; 767 768 if (intf_types[i] == INTF_DISABLED) 769 continue; 770 771 intf = kzalloc(sizeof(*intf), GFP_KERNEL); 772 if (!intf) { 773 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i); 774 return -ENOMEM; 775 } 776 777 intf->num = i; 778 intf->type = intf_types[i]; 779 intf->mode = MDP5_INTF_MODE_NONE; 780 intf->idx = mdp5_kms->num_intfs; 781 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; 782 } 783 784 return 0; 785 } 786 787 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) 788 { 789 struct msm_drm_private *priv = dev->dev_private; 790 struct mdp5_kms *mdp5_kms; 791 struct mdp5_cfg *config; 792 u32 major, minor; 793 int ret; 794 795 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); 796 if (!mdp5_kms) { 797 ret = -ENOMEM; 798 goto fail; 799 } 800 801 spin_lock_init(&mdp5_kms->resource_lock); 802 803 mdp5_kms->dev = dev; 804 mdp5_kms->pdev = pdev; 805 806 ret = mdp5_global_obj_init(mdp5_kms); 807 if (ret) 808 goto fail; 809 810 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys"); 811 if (IS_ERR(mdp5_kms->mmio)) { 812 ret = PTR_ERR(mdp5_kms->mmio); 813 goto fail; 814 } 815 816 /* mandatory clocks: */ 817 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true); 818 if (ret) 819 goto fail; 820 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true); 821 if (ret) 822 goto fail; 823 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true); 824 if (ret) 825 goto fail; 826 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true); 827 if (ret) 828 goto fail; 829 830 /* optional clocks: */ 831 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); 832 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); 833 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); 834 835 /* we need to set a default rate before enabling. Set a safe 836 * rate first, then figure out hw revision, and then set a 837 * more optimal rate: 838 */ 839 clk_set_rate(mdp5_kms->core_clk, 200000000); 840 841 /* set uninit-ed kms */ 842 priv->kms = &mdp5_kms->base.base; 843 844 pm_runtime_enable(&pdev->dev); 845 mdp5_kms->rpm_enabled = true; 846 847 read_mdp_hw_revision(mdp5_kms, &major, &minor); 848 849 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); 850 if (IS_ERR(mdp5_kms->cfg)) { 851 ret = PTR_ERR(mdp5_kms->cfg); 852 mdp5_kms->cfg = NULL; 853 goto fail; 854 } 855 856 config = mdp5_cfg_get_config(mdp5_kms->cfg); 857 mdp5_kms->caps = config->hw->mdp.caps; 858 859 /* TODO: compute core clock rate at runtime */ 860 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); 861 862 /* 863 * Some chipsets have a Shared Memory Pool (SMP), while others 864 * have dedicated latency buffering per source pipe instead; 865 * this section initializes the SMP: 866 */ 867 if (mdp5_kms->caps & MDP_CAP_SMP) { 868 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); 869 if (IS_ERR(mdp5_kms->smp)) { 870 ret = PTR_ERR(mdp5_kms->smp); 871 mdp5_kms->smp = NULL; 872 goto fail; 873 } 874 } 875 876 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); 877 if (IS_ERR(mdp5_kms->ctlm)) { 878 ret = PTR_ERR(mdp5_kms->ctlm); 879 mdp5_kms->ctlm = NULL; 880 goto fail; 881 } 882 883 ret = hwpipe_init(mdp5_kms); 884 if (ret) 885 goto fail; 886 887 ret = hwmixer_init(mdp5_kms); 888 if (ret) 889 goto fail; 890 891 ret = interface_init(mdp5_kms); 892 if (ret) 893 goto fail; 894 895 return 0; 896 fail: 897 if (mdp5_kms) 898 mdp5_destroy(mdp5_kms); 899 return ret; 900 } 901 902 static int mdp5_setup_interconnect(struct platform_device *pdev) 903 { 904 struct icc_path *path0 = msm_icc_get(&pdev->dev, "mdp0-mem"); 905 struct icc_path *path1 = msm_icc_get(&pdev->dev, "mdp1-mem"); 906 struct icc_path *path_rot = msm_icc_get(&pdev->dev, "rotator-mem"); 907 908 if (IS_ERR(path0)) 909 return PTR_ERR(path0); 910 911 if (!path0) { 912 /* no interconnect support is not necessarily a fatal 913 * condition, the platform may simply not have an 914 * interconnect driver yet. But warn about it in case 915 * bootloader didn't setup bus clocks high enough for 916 * scanout. 917 */ 918 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n"); 919 return 0; 920 } 921 922 icc_set_bw(path0, 0, MBps_to_icc(6400)); 923 924 if (!IS_ERR_OR_NULL(path1)) 925 icc_set_bw(path1, 0, MBps_to_icc(6400)); 926 if (!IS_ERR_OR_NULL(path_rot)) 927 icc_set_bw(path_rot, 0, MBps_to_icc(6400)); 928 929 return 0; 930 } 931 932 static int mdp5_dev_probe(struct platform_device *pdev) 933 { 934 int ret; 935 936 DBG(""); 937 938 ret = mdp5_setup_interconnect(pdev); 939 if (ret) 940 return ret; 941 942 return msm_drv_probe(&pdev->dev, mdp5_kms_init); 943 } 944 945 static int mdp5_dev_remove(struct platform_device *pdev) 946 { 947 DBG(""); 948 component_master_del(&pdev->dev, &msm_drm_ops); 949 return 0; 950 } 951 952 static __maybe_unused int mdp5_runtime_suspend(struct device *dev) 953 { 954 struct platform_device *pdev = to_platform_device(dev); 955 struct msm_drm_private *priv = platform_get_drvdata(pdev); 956 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 957 958 DBG(""); 959 960 return mdp5_disable(mdp5_kms); 961 } 962 963 static __maybe_unused int mdp5_runtime_resume(struct device *dev) 964 { 965 struct platform_device *pdev = to_platform_device(dev); 966 struct msm_drm_private *priv = platform_get_drvdata(pdev); 967 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 968 969 DBG(""); 970 971 return mdp5_enable(mdp5_kms); 972 } 973 974 static const struct dev_pm_ops mdp5_pm_ops = { 975 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) 976 .prepare = msm_pm_prepare, 977 .complete = msm_pm_complete, 978 }; 979 980 static const struct of_device_id mdp5_dt_match[] = { 981 { .compatible = "qcom,mdp5", }, 982 /* to support downstream DT files */ 983 { .compatible = "qcom,mdss_mdp", }, 984 {} 985 }; 986 MODULE_DEVICE_TABLE(of, mdp5_dt_match); 987 988 static struct platform_driver mdp5_driver = { 989 .probe = mdp5_dev_probe, 990 .remove = mdp5_dev_remove, 991 .shutdown = msm_drv_shutdown, 992 .driver = { 993 .name = "msm_mdp", 994 .of_match_table = mdp5_dt_match, 995 .pm = &mdp5_pm_ops, 996 }, 997 }; 998 999 void __init msm_mdp_register(void) 1000 { 1001 DBG(""); 1002 platform_driver_register(&mdp5_driver); 1003 } 1004 1005 void __exit msm_mdp_unregister(void) 1006 { 1007 DBG(""); 1008 platform_driver_unregister(&mdp5_driver); 1009 } 1010