1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/of_irq.h> 11 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_vblank.h> 16 17 #include "msm_drv.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 #include "mdp5_kms.h" 21 22 static int mdp5_hw_init(struct msm_kms *kms) 23 { 24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 25 struct device *dev = &mdp5_kms->pdev->dev; 26 unsigned long flags; 27 28 pm_runtime_get_sync(dev); 29 30 /* Magic unknown register writes: 31 * 32 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) 34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) 35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) 36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) 37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) 38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) 39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) 40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) 41 * 42 * Downstream fbdev driver gets these register offsets/values 43 * from DT.. not really sure what these registers are or if 44 * different values for different boards/SoC's, etc. I guess 45 * they are the golden registers. 46 * 47 * Not setting these does not seem to cause any problem. But 48 * we may be getting lucky with the bootloader initializing 49 * them for us. OTOH, if we can always count on the bootloader 50 * setting the golden registers, then perhaps we don't need to 51 * care. 52 */ 53 54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); 55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); 56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); 57 58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); 59 60 pm_runtime_put_sync(dev); 61 62 return 0; 63 } 64 65 /* Global/shared object state funcs */ 66 67 /* 68 * This is a helper that returns the private state currently in operation. 69 * Note that this would return the "old_state" if called in the atomic check 70 * path, and the "new_state" after the atomic swap has been done. 71 */ 72 struct mdp5_global_state * 73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) 74 { 75 return to_mdp5_global_state(mdp5_kms->glob_state.state); 76 } 77 78 /* 79 * This acquires the modeset lock set aside for global state, creates 80 * a new duplicated private object state. 81 */ 82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) 83 { 84 struct msm_drm_private *priv = s->dev->dev_private; 85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 86 struct drm_private_state *priv_state; 87 int ret; 88 89 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx); 90 if (ret) 91 return ERR_PTR(ret); 92 93 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); 94 if (IS_ERR(priv_state)) 95 return ERR_CAST(priv_state); 96 97 return to_mdp5_global_state(priv_state); 98 } 99 100 static struct drm_private_state * 101 mdp5_global_duplicate_state(struct drm_private_obj *obj) 102 { 103 struct mdp5_global_state *state; 104 105 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 106 if (!state) 107 return NULL; 108 109 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 110 111 return &state->base; 112 } 113 114 static void mdp5_global_destroy_state(struct drm_private_obj *obj, 115 struct drm_private_state *state) 116 { 117 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); 118 119 kfree(mdp5_state); 120 } 121 122 static const struct drm_private_state_funcs mdp5_global_state_funcs = { 123 .atomic_duplicate_state = mdp5_global_duplicate_state, 124 .atomic_destroy_state = mdp5_global_destroy_state, 125 }; 126 127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) 128 { 129 struct mdp5_global_state *state; 130 131 drm_modeset_lock_init(&mdp5_kms->glob_state_lock); 132 133 state = kzalloc(sizeof(*state), GFP_KERNEL); 134 if (!state) 135 return -ENOMEM; 136 137 state->mdp5_kms = mdp5_kms; 138 139 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, 140 &state->base, 141 &mdp5_global_state_funcs); 142 return 0; 143 } 144 145 static void mdp5_enable_commit(struct msm_kms *kms) 146 { 147 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 148 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 149 } 150 151 static void mdp5_disable_commit(struct msm_kms *kms) 152 { 153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 154 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 155 } 156 157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 158 { 159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 160 struct mdp5_global_state *global_state; 161 162 global_state = mdp5_get_existing_global_state(mdp5_kms); 163 164 if (mdp5_kms->smp) 165 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp); 166 } 167 168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 169 { 170 /* TODO */ 171 } 172 173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 174 { 175 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 176 struct drm_crtc *crtc; 177 178 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask) 179 mdp5_crtc_wait_for_commit_done(crtc); 180 } 181 182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 183 { 184 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 185 struct mdp5_global_state *global_state; 186 187 global_state = mdp5_get_existing_global_state(mdp5_kms); 188 189 if (mdp5_kms->smp) 190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); 191 } 192 193 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, 194 struct drm_encoder *encoder) 195 { 196 return rate; 197 } 198 199 static int mdp5_set_split_display(struct msm_kms *kms, 200 struct drm_encoder *encoder, 201 struct drm_encoder *slave_encoder, 202 bool is_cmd_mode) 203 { 204 if (is_cmd_mode) 205 return mdp5_cmd_encoder_set_split_display(encoder, 206 slave_encoder); 207 else 208 return mdp5_vid_encoder_set_split_display(encoder, 209 slave_encoder); 210 } 211 212 static void mdp5_kms_destroy(struct msm_kms *kms) 213 { 214 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 215 struct msm_gem_address_space *aspace = kms->aspace; 216 int i; 217 218 for (i = 0; i < mdp5_kms->num_hwmixers; i++) 219 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]); 220 221 for (i = 0; i < mdp5_kms->num_hwpipes; i++) 222 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); 223 224 if (aspace) { 225 aspace->mmu->funcs->detach(aspace->mmu); 226 msm_gem_address_space_put(aspace); 227 } 228 229 mdp_kms_destroy(&mdp5_kms->base); 230 } 231 232 #ifdef CONFIG_DEBUG_FS 233 static int smp_show(struct seq_file *m, void *arg) 234 { 235 struct drm_info_node *node = (struct drm_info_node *) m->private; 236 struct drm_device *dev = node->minor->dev; 237 struct msm_drm_private *priv = dev->dev_private; 238 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 239 struct drm_printer p = drm_seq_file_printer(m); 240 241 if (!mdp5_kms->smp) { 242 drm_printf(&p, "no SMP pool\n"); 243 return 0; 244 } 245 246 mdp5_smp_dump(mdp5_kms->smp, &p); 247 248 return 0; 249 } 250 251 static struct drm_info_list mdp5_debugfs_list[] = { 252 {"smp", smp_show }, 253 }; 254 255 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 256 { 257 drm_debugfs_create_files(mdp5_debugfs_list, 258 ARRAY_SIZE(mdp5_debugfs_list), 259 minor->debugfs_root, minor); 260 261 return 0; 262 } 263 #endif 264 265 static const struct mdp_kms_funcs kms_funcs = { 266 .base = { 267 .hw_init = mdp5_hw_init, 268 .irq_preinstall = mdp5_irq_preinstall, 269 .irq_postinstall = mdp5_irq_postinstall, 270 .irq_uninstall = mdp5_irq_uninstall, 271 .irq = mdp5_irq, 272 .enable_vblank = mdp5_enable_vblank, 273 .disable_vblank = mdp5_disable_vblank, 274 .flush_commit = mdp5_flush_commit, 275 .enable_commit = mdp5_enable_commit, 276 .disable_commit = mdp5_disable_commit, 277 .prepare_commit = mdp5_prepare_commit, 278 .wait_flush = mdp5_wait_flush, 279 .complete_commit = mdp5_complete_commit, 280 .get_format = mdp_get_format, 281 .round_pixclk = mdp5_round_pixclk, 282 .set_split_display = mdp5_set_split_display, 283 .destroy = mdp5_kms_destroy, 284 #ifdef CONFIG_DEBUG_FS 285 .debugfs_init = mdp5_kms_debugfs_init, 286 #endif 287 }, 288 .set_irqmask = mdp5_set_irqmask, 289 }; 290 291 static int mdp5_disable(struct mdp5_kms *mdp5_kms) 292 { 293 DBG(""); 294 295 mdp5_kms->enable_count--; 296 WARN_ON(mdp5_kms->enable_count < 0); 297 298 clk_disable_unprepare(mdp5_kms->tbu_rt_clk); 299 clk_disable_unprepare(mdp5_kms->tbu_clk); 300 clk_disable_unprepare(mdp5_kms->ahb_clk); 301 clk_disable_unprepare(mdp5_kms->axi_clk); 302 clk_disable_unprepare(mdp5_kms->core_clk); 303 clk_disable_unprepare(mdp5_kms->lut_clk); 304 305 return 0; 306 } 307 308 static int mdp5_enable(struct mdp5_kms *mdp5_kms) 309 { 310 DBG(""); 311 312 mdp5_kms->enable_count++; 313 314 clk_prepare_enable(mdp5_kms->ahb_clk); 315 clk_prepare_enable(mdp5_kms->axi_clk); 316 clk_prepare_enable(mdp5_kms->core_clk); 317 clk_prepare_enable(mdp5_kms->lut_clk); 318 clk_prepare_enable(mdp5_kms->tbu_clk); 319 clk_prepare_enable(mdp5_kms->tbu_rt_clk); 320 321 return 0; 322 } 323 324 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 325 struct mdp5_interface *intf, 326 struct mdp5_ctl *ctl) 327 { 328 struct drm_device *dev = mdp5_kms->dev; 329 struct msm_drm_private *priv = dev->dev_private; 330 struct drm_encoder *encoder; 331 332 encoder = mdp5_encoder_init(dev, intf, ctl); 333 if (IS_ERR(encoder)) { 334 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n"); 335 return encoder; 336 } 337 338 priv->encoders[priv->num_encoders++] = encoder; 339 340 return encoder; 341 } 342 343 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 344 { 345 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; 346 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); 347 int id = 0, i; 348 349 for (i = 0; i < intf_cnt; i++) { 350 if (intfs[i] == INTF_DSI) { 351 if (intf_num == i) 352 return id; 353 354 id++; 355 } 356 } 357 358 return -EINVAL; 359 } 360 361 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, 362 struct mdp5_interface *intf) 363 { 364 struct drm_device *dev = mdp5_kms->dev; 365 struct msm_drm_private *priv = dev->dev_private; 366 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; 367 struct mdp5_ctl *ctl; 368 struct drm_encoder *encoder; 369 int ret = 0; 370 371 switch (intf->type) { 372 case INTF_eDP: 373 if (!priv->edp) 374 break; 375 376 ctl = mdp5_ctlm_request(ctlm, intf->num); 377 if (!ctl) { 378 ret = -EINVAL; 379 break; 380 } 381 382 encoder = construct_encoder(mdp5_kms, intf, ctl); 383 if (IS_ERR(encoder)) { 384 ret = PTR_ERR(encoder); 385 break; 386 } 387 388 ret = msm_edp_modeset_init(priv->edp, dev, encoder); 389 break; 390 case INTF_HDMI: 391 if (!priv->hdmi) 392 break; 393 394 ctl = mdp5_ctlm_request(ctlm, intf->num); 395 if (!ctl) { 396 ret = -EINVAL; 397 break; 398 } 399 400 encoder = construct_encoder(mdp5_kms, intf, ctl); 401 if (IS_ERR(encoder)) { 402 ret = PTR_ERR(encoder); 403 break; 404 } 405 406 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 407 break; 408 case INTF_DSI: 409 { 410 const struct mdp5_cfg_hw *hw_cfg = 411 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 412 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); 413 414 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { 415 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", 416 intf->num); 417 ret = -EINVAL; 418 break; 419 } 420 421 if (!priv->dsi[dsi_id]) 422 break; 423 424 ctl = mdp5_ctlm_request(ctlm, intf->num); 425 if (!ctl) { 426 ret = -EINVAL; 427 break; 428 } 429 430 encoder = construct_encoder(mdp5_kms, intf, ctl); 431 if (IS_ERR(encoder)) { 432 ret = PTR_ERR(encoder); 433 break; 434 } 435 436 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 437 if (!ret) 438 mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_id])); 439 440 break; 441 } 442 default: 443 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type); 444 ret = -EINVAL; 445 break; 446 } 447 448 return ret; 449 } 450 451 static int modeset_init(struct mdp5_kms *mdp5_kms) 452 { 453 struct drm_device *dev = mdp5_kms->dev; 454 struct msm_drm_private *priv = dev->dev_private; 455 unsigned int num_crtcs; 456 int i, ret, pi = 0, ci = 0; 457 struct drm_plane *primary[MAX_BASES] = { NULL }; 458 struct drm_plane *cursor[MAX_BASES] = { NULL }; 459 460 /* 461 * Construct encoders and modeset initialize connector devices 462 * for each external display interface. 463 */ 464 for (i = 0; i < mdp5_kms->num_intfs; i++) { 465 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); 466 if (ret) 467 goto fail; 468 } 469 470 /* 471 * We should ideally have less number of encoders (set up by parsing 472 * the MDP5 interfaces) than the number of layer mixers present in HW, 473 * but let's be safe here anyway 474 */ 475 num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers); 476 477 /* 478 * Construct planes equaling the number of hw pipes, and CRTCs for the 479 * N encoders set up by the driver. The first N planes become primary 480 * planes for the CRTCs, with the remainder as overlay planes: 481 */ 482 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { 483 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; 484 struct drm_plane *plane; 485 enum drm_plane_type type; 486 487 if (i < num_crtcs) 488 type = DRM_PLANE_TYPE_PRIMARY; 489 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR) 490 type = DRM_PLANE_TYPE_CURSOR; 491 else 492 type = DRM_PLANE_TYPE_OVERLAY; 493 494 plane = mdp5_plane_init(dev, type); 495 if (IS_ERR(plane)) { 496 ret = PTR_ERR(plane); 497 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret); 498 goto fail; 499 } 500 priv->planes[priv->num_planes++] = plane; 501 502 if (type == DRM_PLANE_TYPE_PRIMARY) 503 primary[pi++] = plane; 504 if (type == DRM_PLANE_TYPE_CURSOR) 505 cursor[ci++] = plane; 506 } 507 508 for (i = 0; i < num_crtcs; i++) { 509 struct drm_crtc *crtc; 510 511 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); 512 if (IS_ERR(crtc)) { 513 ret = PTR_ERR(crtc); 514 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); 515 goto fail; 516 } 517 priv->crtcs[priv->num_crtcs++] = crtc; 518 } 519 520 /* 521 * Now that we know the number of crtcs we've created, set the possible 522 * crtcs for the encoders 523 */ 524 for (i = 0; i < priv->num_encoders; i++) { 525 struct drm_encoder *encoder = priv->encoders[i]; 526 527 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 528 } 529 530 return 0; 531 532 fail: 533 return ret; 534 } 535 536 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, 537 u32 *major, u32 *minor) 538 { 539 struct device *dev = &mdp5_kms->pdev->dev; 540 u32 version; 541 542 pm_runtime_get_sync(dev); 543 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); 544 pm_runtime_put_sync(dev); 545 546 *major = FIELD(version, MDP5_HW_VERSION_MAJOR); 547 *minor = FIELD(version, MDP5_HW_VERSION_MINOR); 548 549 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); 550 } 551 552 static int get_clk(struct platform_device *pdev, struct clk **clkp, 553 const char *name, bool mandatory) 554 { 555 struct device *dev = &pdev->dev; 556 struct clk *clk = msm_clk_get(pdev, name); 557 if (IS_ERR(clk) && mandatory) { 558 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 559 return PTR_ERR(clk); 560 } 561 if (IS_ERR(clk)) 562 DBG("skipping %s", name); 563 else 564 *clkp = clk; 565 566 return 0; 567 } 568 569 struct msm_kms *mdp5_kms_init(struct drm_device *dev) 570 { 571 struct msm_drm_private *priv = dev->dev_private; 572 struct platform_device *pdev; 573 struct mdp5_kms *mdp5_kms; 574 struct mdp5_cfg *config; 575 struct msm_kms *kms; 576 struct msm_gem_address_space *aspace; 577 int irq, i, ret; 578 struct device *iommu_dev; 579 580 /* priv->kms would have been populated by the MDP5 driver */ 581 kms = priv->kms; 582 if (!kms) 583 return NULL; 584 585 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 586 pdev = mdp5_kms->pdev; 587 588 ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs); 589 if (ret) { 590 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n"); 591 goto fail; 592 } 593 594 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 595 if (irq < 0) { 596 ret = irq; 597 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret); 598 goto fail; 599 } 600 601 kms->irq = irq; 602 603 config = mdp5_cfg_get_config(mdp5_kms->cfg); 604 605 /* make sure things are off before attaching iommu (bootloader could 606 * have left things on, in which case we'll start getting faults if 607 * we don't disable): 608 */ 609 pm_runtime_get_sync(&pdev->dev); 610 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 611 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || 612 !config->hw->intf.base[i]) 613 continue; 614 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 615 616 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); 617 } 618 mdelay(16); 619 620 if (config->platform.iommu) { 621 struct msm_mmu *mmu; 622 623 iommu_dev = &pdev->dev; 624 if (!dev_iommu_fwspec_get(iommu_dev)) 625 iommu_dev = iommu_dev->parent; 626 627 mmu = msm_iommu_new(iommu_dev, config->platform.iommu); 628 629 aspace = msm_gem_address_space_create(mmu, "mdp5", 630 0x1000, 0x100000000 - 0x1000); 631 632 if (IS_ERR(aspace)) { 633 if (!IS_ERR(mmu)) 634 mmu->funcs->destroy(mmu); 635 ret = PTR_ERR(aspace); 636 goto fail; 637 } 638 639 kms->aspace = aspace; 640 } else { 641 DRM_DEV_INFO(&pdev->dev, 642 "no iommu, fallback to phys contig buffers for scanout\n"); 643 aspace = NULL; 644 } 645 646 pm_runtime_put_sync(&pdev->dev); 647 648 ret = modeset_init(mdp5_kms); 649 if (ret) { 650 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret); 651 goto fail; 652 } 653 654 dev->mode_config.min_width = 0; 655 dev->mode_config.min_height = 0; 656 dev->mode_config.max_width = 0xffff; 657 dev->mode_config.max_height = 0xffff; 658 659 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */ 660 dev->vblank_disable_immediate = true; 661 662 return kms; 663 fail: 664 if (kms) 665 mdp5_kms_destroy(kms); 666 return ERR_PTR(ret); 667 } 668 669 static void mdp5_destroy(struct platform_device *pdev) 670 { 671 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 672 int i; 673 674 if (mdp5_kms->ctlm) 675 mdp5_ctlm_destroy(mdp5_kms->ctlm); 676 if (mdp5_kms->smp) 677 mdp5_smp_destroy(mdp5_kms->smp); 678 if (mdp5_kms->cfg) 679 mdp5_cfg_destroy(mdp5_kms->cfg); 680 681 for (i = 0; i < mdp5_kms->num_intfs; i++) 682 kfree(mdp5_kms->intfs[i]); 683 684 if (mdp5_kms->rpm_enabled) 685 pm_runtime_disable(&pdev->dev); 686 687 drm_atomic_private_obj_fini(&mdp5_kms->glob_state); 688 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); 689 } 690 691 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, 692 const enum mdp5_pipe *pipes, const uint32_t *offsets, 693 uint32_t caps) 694 { 695 struct drm_device *dev = mdp5_kms->dev; 696 int i, ret; 697 698 for (i = 0; i < cnt; i++) { 699 struct mdp5_hw_pipe *hwpipe; 700 701 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); 702 if (IS_ERR(hwpipe)) { 703 ret = PTR_ERR(hwpipe); 704 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n", 705 pipe2name(pipes[i]), ret); 706 return ret; 707 } 708 hwpipe->idx = mdp5_kms->num_hwpipes; 709 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; 710 } 711 712 return 0; 713 } 714 715 static int hwpipe_init(struct mdp5_kms *mdp5_kms) 716 { 717 static const enum mdp5_pipe rgb_planes[] = { 718 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, 719 }; 720 static const enum mdp5_pipe vig_planes[] = { 721 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, 722 }; 723 static const enum mdp5_pipe dma_planes[] = { 724 SSPP_DMA0, SSPP_DMA1, 725 }; 726 static const enum mdp5_pipe cursor_planes[] = { 727 SSPP_CURSOR0, SSPP_CURSOR1, 728 }; 729 const struct mdp5_cfg_hw *hw_cfg; 730 int ret; 731 732 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 733 734 /* Construct RGB pipes: */ 735 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, 736 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); 737 if (ret) 738 return ret; 739 740 /* Construct video (VIG) pipes: */ 741 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, 742 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); 743 if (ret) 744 return ret; 745 746 /* Construct DMA pipes: */ 747 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, 748 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); 749 if (ret) 750 return ret; 751 752 /* Construct cursor pipes: */ 753 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, 754 cursor_planes, hw_cfg->pipe_cursor.base, 755 hw_cfg->pipe_cursor.caps); 756 if (ret) 757 return ret; 758 759 return 0; 760 } 761 762 static int hwmixer_init(struct mdp5_kms *mdp5_kms) 763 { 764 struct drm_device *dev = mdp5_kms->dev; 765 const struct mdp5_cfg_hw *hw_cfg; 766 int i, ret; 767 768 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 769 770 for (i = 0; i < hw_cfg->lm.count; i++) { 771 struct mdp5_hw_mixer *mixer; 772 773 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]); 774 if (IS_ERR(mixer)) { 775 ret = PTR_ERR(mixer); 776 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n", 777 i, ret); 778 return ret; 779 } 780 781 mixer->idx = mdp5_kms->num_hwmixers; 782 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; 783 } 784 785 return 0; 786 } 787 788 static int interface_init(struct mdp5_kms *mdp5_kms) 789 { 790 struct drm_device *dev = mdp5_kms->dev; 791 const struct mdp5_cfg_hw *hw_cfg; 792 const enum mdp5_intf_type *intf_types; 793 int i; 794 795 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 796 intf_types = hw_cfg->intf.connect; 797 798 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 799 struct mdp5_interface *intf; 800 801 if (intf_types[i] == INTF_DISABLED) 802 continue; 803 804 intf = kzalloc(sizeof(*intf), GFP_KERNEL); 805 if (!intf) { 806 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i); 807 return -ENOMEM; 808 } 809 810 intf->num = i; 811 intf->type = intf_types[i]; 812 intf->mode = MDP5_INTF_MODE_NONE; 813 intf->idx = mdp5_kms->num_intfs; 814 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; 815 } 816 817 return 0; 818 } 819 820 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) 821 { 822 struct msm_drm_private *priv = dev->dev_private; 823 struct mdp5_kms *mdp5_kms; 824 struct mdp5_cfg *config; 825 u32 major, minor; 826 int ret; 827 828 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); 829 if (!mdp5_kms) { 830 ret = -ENOMEM; 831 goto fail; 832 } 833 834 platform_set_drvdata(pdev, mdp5_kms); 835 836 spin_lock_init(&mdp5_kms->resource_lock); 837 838 mdp5_kms->dev = dev; 839 mdp5_kms->pdev = pdev; 840 841 ret = mdp5_global_obj_init(mdp5_kms); 842 if (ret) 843 goto fail; 844 845 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); 846 if (IS_ERR(mdp5_kms->mmio)) { 847 ret = PTR_ERR(mdp5_kms->mmio); 848 goto fail; 849 } 850 851 /* mandatory clocks: */ 852 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true); 853 if (ret) 854 goto fail; 855 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true); 856 if (ret) 857 goto fail; 858 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true); 859 if (ret) 860 goto fail; 861 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true); 862 if (ret) 863 goto fail; 864 865 /* optional clocks: */ 866 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); 867 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); 868 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); 869 870 /* we need to set a default rate before enabling. Set a safe 871 * rate first, then figure out hw revision, and then set a 872 * more optimal rate: 873 */ 874 clk_set_rate(mdp5_kms->core_clk, 200000000); 875 876 pm_runtime_enable(&pdev->dev); 877 mdp5_kms->rpm_enabled = true; 878 879 read_mdp_hw_revision(mdp5_kms, &major, &minor); 880 881 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); 882 if (IS_ERR(mdp5_kms->cfg)) { 883 ret = PTR_ERR(mdp5_kms->cfg); 884 mdp5_kms->cfg = NULL; 885 goto fail; 886 } 887 888 config = mdp5_cfg_get_config(mdp5_kms->cfg); 889 mdp5_kms->caps = config->hw->mdp.caps; 890 891 /* TODO: compute core clock rate at runtime */ 892 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); 893 894 /* 895 * Some chipsets have a Shared Memory Pool (SMP), while others 896 * have dedicated latency buffering per source pipe instead; 897 * this section initializes the SMP: 898 */ 899 if (mdp5_kms->caps & MDP_CAP_SMP) { 900 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); 901 if (IS_ERR(mdp5_kms->smp)) { 902 ret = PTR_ERR(mdp5_kms->smp); 903 mdp5_kms->smp = NULL; 904 goto fail; 905 } 906 } 907 908 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); 909 if (IS_ERR(mdp5_kms->ctlm)) { 910 ret = PTR_ERR(mdp5_kms->ctlm); 911 mdp5_kms->ctlm = NULL; 912 goto fail; 913 } 914 915 ret = hwpipe_init(mdp5_kms); 916 if (ret) 917 goto fail; 918 919 ret = hwmixer_init(mdp5_kms); 920 if (ret) 921 goto fail; 922 923 ret = interface_init(mdp5_kms); 924 if (ret) 925 goto fail; 926 927 /* set uninit-ed kms */ 928 priv->kms = &mdp5_kms->base.base; 929 930 return 0; 931 fail: 932 if (mdp5_kms) 933 mdp5_destroy(pdev); 934 return ret; 935 } 936 937 static int mdp5_bind(struct device *dev, struct device *master, void *data) 938 { 939 struct drm_device *ddev = dev_get_drvdata(master); 940 struct platform_device *pdev = to_platform_device(dev); 941 942 DBG(""); 943 944 return mdp5_init(pdev, ddev); 945 } 946 947 static void mdp5_unbind(struct device *dev, struct device *master, 948 void *data) 949 { 950 struct platform_device *pdev = to_platform_device(dev); 951 952 mdp5_destroy(pdev); 953 } 954 955 static const struct component_ops mdp5_ops = { 956 .bind = mdp5_bind, 957 .unbind = mdp5_unbind, 958 }; 959 960 static int mdp5_setup_interconnect(struct platform_device *pdev) 961 { 962 struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem"); 963 struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem"); 964 struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem"); 965 966 if (IS_ERR(path0)) 967 return PTR_ERR(path0); 968 969 if (!path0) { 970 /* no interconnect support is not necessarily a fatal 971 * condition, the platform may simply not have an 972 * interconnect driver yet. But warn about it in case 973 * bootloader didn't setup bus clocks high enough for 974 * scanout. 975 */ 976 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n"); 977 return 0; 978 } 979 980 icc_set_bw(path0, 0, MBps_to_icc(6400)); 981 982 if (!IS_ERR_OR_NULL(path1)) 983 icc_set_bw(path1, 0, MBps_to_icc(6400)); 984 if (!IS_ERR_OR_NULL(path_rot)) 985 icc_set_bw(path_rot, 0, MBps_to_icc(6400)); 986 987 return 0; 988 } 989 990 static int mdp5_dev_probe(struct platform_device *pdev) 991 { 992 int ret; 993 994 DBG(""); 995 996 ret = mdp5_setup_interconnect(pdev); 997 if (ret) 998 return ret; 999 1000 return component_add(&pdev->dev, &mdp5_ops); 1001 } 1002 1003 static int mdp5_dev_remove(struct platform_device *pdev) 1004 { 1005 DBG(""); 1006 component_del(&pdev->dev, &mdp5_ops); 1007 return 0; 1008 } 1009 1010 static __maybe_unused int mdp5_runtime_suspend(struct device *dev) 1011 { 1012 struct platform_device *pdev = to_platform_device(dev); 1013 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 1014 1015 DBG(""); 1016 1017 return mdp5_disable(mdp5_kms); 1018 } 1019 1020 static __maybe_unused int mdp5_runtime_resume(struct device *dev) 1021 { 1022 struct platform_device *pdev = to_platform_device(dev); 1023 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 1024 1025 DBG(""); 1026 1027 return mdp5_enable(mdp5_kms); 1028 } 1029 1030 static const struct dev_pm_ops mdp5_pm_ops = { 1031 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) 1032 }; 1033 1034 static const struct of_device_id mdp5_dt_match[] = { 1035 { .compatible = "qcom,mdp5", }, 1036 /* to support downstream DT files */ 1037 { .compatible = "qcom,mdss_mdp", }, 1038 {} 1039 }; 1040 MODULE_DEVICE_TABLE(of, mdp5_dt_match); 1041 1042 static struct platform_driver mdp5_driver = { 1043 .probe = mdp5_dev_probe, 1044 .remove = mdp5_dev_remove, 1045 .driver = { 1046 .name = "msm_mdp", 1047 .of_match_table = mdp5_dt_match, 1048 .pm = &mdp5_pm_ops, 1049 }, 1050 }; 1051 1052 void __init msm_mdp_register(void) 1053 { 1054 DBG(""); 1055 platform_driver_register(&mdp5_driver); 1056 } 1057 1058 void __exit msm_mdp_unregister(void) 1059 { 1060 DBG(""); 1061 platform_driver_unregister(&mdp5_driver); 1062 } 1063