1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/of_irq.h> 11 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_vblank.h> 16 17 #include "msm_drv.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 #include "mdp5_kms.h" 21 22 static int mdp5_hw_init(struct msm_kms *kms) 23 { 24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 25 struct device *dev = &mdp5_kms->pdev->dev; 26 unsigned long flags; 27 28 pm_runtime_get_sync(dev); 29 30 /* Magic unknown register writes: 31 * 32 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) 34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) 35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) 36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) 37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) 38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) 39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) 40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) 41 * 42 * Downstream fbdev driver gets these register offsets/values 43 * from DT.. not really sure what these registers are or if 44 * different values for different boards/SoC's, etc. I guess 45 * they are the golden registers. 46 * 47 * Not setting these does not seem to cause any problem. But 48 * we may be getting lucky with the bootloader initializing 49 * them for us. OTOH, if we can always count on the bootloader 50 * setting the golden registers, then perhaps we don't need to 51 * care. 52 */ 53 54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); 55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); 56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); 57 58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); 59 60 pm_runtime_put_sync(dev); 61 62 return 0; 63 } 64 65 /* Global/shared object state funcs */ 66 67 /* 68 * This is a helper that returns the private state currently in operation. 69 * Note that this would return the "old_state" if called in the atomic check 70 * path, and the "new_state" after the atomic swap has been done. 71 */ 72 struct mdp5_global_state * 73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) 74 { 75 return to_mdp5_global_state(mdp5_kms->glob_state.state); 76 } 77 78 /* 79 * This acquires the modeset lock set aside for global state, creates 80 * a new duplicated private object state. 81 */ 82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) 83 { 84 struct msm_drm_private *priv = s->dev->dev_private; 85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 86 struct drm_private_state *priv_state; 87 int ret; 88 89 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx); 90 if (ret) 91 return ERR_PTR(ret); 92 93 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); 94 if (IS_ERR(priv_state)) 95 return ERR_CAST(priv_state); 96 97 return to_mdp5_global_state(priv_state); 98 } 99 100 static struct drm_private_state * 101 mdp5_global_duplicate_state(struct drm_private_obj *obj) 102 { 103 struct mdp5_global_state *state; 104 105 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 106 if (!state) 107 return NULL; 108 109 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 110 111 return &state->base; 112 } 113 114 static void mdp5_global_destroy_state(struct drm_private_obj *obj, 115 struct drm_private_state *state) 116 { 117 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); 118 119 kfree(mdp5_state); 120 } 121 122 static const struct drm_private_state_funcs mdp5_global_state_funcs = { 123 .atomic_duplicate_state = mdp5_global_duplicate_state, 124 .atomic_destroy_state = mdp5_global_destroy_state, 125 }; 126 127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) 128 { 129 struct mdp5_global_state *state; 130 131 drm_modeset_lock_init(&mdp5_kms->glob_state_lock); 132 133 state = kzalloc(sizeof(*state), GFP_KERNEL); 134 if (!state) 135 return -ENOMEM; 136 137 state->mdp5_kms = mdp5_kms; 138 139 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, 140 &state->base, 141 &mdp5_global_state_funcs); 142 return 0; 143 } 144 145 static void mdp5_enable_commit(struct msm_kms *kms) 146 { 147 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 148 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 149 } 150 151 static void mdp5_disable_commit(struct msm_kms *kms) 152 { 153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 154 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 155 } 156 157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 158 { 159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 160 struct mdp5_global_state *global_state; 161 162 global_state = mdp5_get_existing_global_state(mdp5_kms); 163 164 if (mdp5_kms->smp) 165 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp); 166 } 167 168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 169 { 170 /* TODO */ 171 } 172 173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 174 { 175 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 176 struct drm_crtc *crtc; 177 178 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask) 179 mdp5_crtc_wait_for_commit_done(crtc); 180 } 181 182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 183 { 184 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 185 struct mdp5_global_state *global_state; 186 187 global_state = mdp5_get_existing_global_state(mdp5_kms); 188 189 if (mdp5_kms->smp) 190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); 191 } 192 193 static int mdp5_set_split_display(struct msm_kms *kms, 194 struct drm_encoder *encoder, 195 struct drm_encoder *slave_encoder, 196 bool is_cmd_mode) 197 { 198 if (is_cmd_mode) 199 return mdp5_cmd_encoder_set_split_display(encoder, 200 slave_encoder); 201 else 202 return mdp5_vid_encoder_set_split_display(encoder, 203 slave_encoder); 204 } 205 206 static void mdp5_kms_destroy(struct msm_kms *kms) 207 { 208 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 209 struct msm_gem_address_space *aspace = kms->aspace; 210 int i; 211 212 for (i = 0; i < mdp5_kms->num_hwmixers; i++) 213 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]); 214 215 for (i = 0; i < mdp5_kms->num_hwpipes; i++) 216 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); 217 218 if (aspace) { 219 aspace->mmu->funcs->detach(aspace->mmu); 220 msm_gem_address_space_put(aspace); 221 } 222 223 mdp_kms_destroy(&mdp5_kms->base); 224 } 225 226 #ifdef CONFIG_DEBUG_FS 227 static int smp_show(struct seq_file *m, void *arg) 228 { 229 struct drm_info_node *node = (struct drm_info_node *) m->private; 230 struct drm_device *dev = node->minor->dev; 231 struct msm_drm_private *priv = dev->dev_private; 232 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 233 struct drm_printer p = drm_seq_file_printer(m); 234 235 if (!mdp5_kms->smp) { 236 drm_printf(&p, "no SMP pool\n"); 237 return 0; 238 } 239 240 mdp5_smp_dump(mdp5_kms->smp, &p); 241 242 return 0; 243 } 244 245 static struct drm_info_list mdp5_debugfs_list[] = { 246 {"smp", smp_show }, 247 }; 248 249 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 250 { 251 drm_debugfs_create_files(mdp5_debugfs_list, 252 ARRAY_SIZE(mdp5_debugfs_list), 253 minor->debugfs_root, minor); 254 255 return 0; 256 } 257 #endif 258 259 static const struct mdp_kms_funcs kms_funcs = { 260 .base = { 261 .hw_init = mdp5_hw_init, 262 .irq_preinstall = mdp5_irq_preinstall, 263 .irq_postinstall = mdp5_irq_postinstall, 264 .irq_uninstall = mdp5_irq_uninstall, 265 .irq = mdp5_irq, 266 .enable_vblank = mdp5_enable_vblank, 267 .disable_vblank = mdp5_disable_vblank, 268 .flush_commit = mdp5_flush_commit, 269 .enable_commit = mdp5_enable_commit, 270 .disable_commit = mdp5_disable_commit, 271 .prepare_commit = mdp5_prepare_commit, 272 .wait_flush = mdp5_wait_flush, 273 .complete_commit = mdp5_complete_commit, 274 .get_format = mdp_get_format, 275 .set_split_display = mdp5_set_split_display, 276 .destroy = mdp5_kms_destroy, 277 #ifdef CONFIG_DEBUG_FS 278 .debugfs_init = mdp5_kms_debugfs_init, 279 #endif 280 }, 281 .set_irqmask = mdp5_set_irqmask, 282 }; 283 284 static int mdp5_disable(struct mdp5_kms *mdp5_kms) 285 { 286 DBG(""); 287 288 mdp5_kms->enable_count--; 289 WARN_ON(mdp5_kms->enable_count < 0); 290 291 clk_disable_unprepare(mdp5_kms->tbu_rt_clk); 292 clk_disable_unprepare(mdp5_kms->tbu_clk); 293 clk_disable_unprepare(mdp5_kms->ahb_clk); 294 clk_disable_unprepare(mdp5_kms->axi_clk); 295 clk_disable_unprepare(mdp5_kms->core_clk); 296 clk_disable_unprepare(mdp5_kms->lut_clk); 297 298 return 0; 299 } 300 301 static int mdp5_enable(struct mdp5_kms *mdp5_kms) 302 { 303 DBG(""); 304 305 mdp5_kms->enable_count++; 306 307 clk_prepare_enable(mdp5_kms->ahb_clk); 308 clk_prepare_enable(mdp5_kms->axi_clk); 309 clk_prepare_enable(mdp5_kms->core_clk); 310 clk_prepare_enable(mdp5_kms->lut_clk); 311 clk_prepare_enable(mdp5_kms->tbu_clk); 312 clk_prepare_enable(mdp5_kms->tbu_rt_clk); 313 314 return 0; 315 } 316 317 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 318 struct mdp5_interface *intf, 319 struct mdp5_ctl *ctl) 320 { 321 struct drm_device *dev = mdp5_kms->dev; 322 struct msm_drm_private *priv = dev->dev_private; 323 struct drm_encoder *encoder; 324 325 encoder = mdp5_encoder_init(dev, intf, ctl); 326 if (IS_ERR(encoder)) { 327 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n"); 328 return encoder; 329 } 330 331 priv->encoders[priv->num_encoders++] = encoder; 332 333 return encoder; 334 } 335 336 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 337 { 338 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; 339 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); 340 int id = 0, i; 341 342 for (i = 0; i < intf_cnt; i++) { 343 if (intfs[i] == INTF_DSI) { 344 if (intf_num == i) 345 return id; 346 347 id++; 348 } 349 } 350 351 return -EINVAL; 352 } 353 354 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, 355 struct mdp5_interface *intf) 356 { 357 struct drm_device *dev = mdp5_kms->dev; 358 struct msm_drm_private *priv = dev->dev_private; 359 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; 360 struct mdp5_ctl *ctl; 361 struct drm_encoder *encoder; 362 int ret = 0; 363 364 switch (intf->type) { 365 case INTF_eDP: 366 DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num); 367 break; 368 case INTF_HDMI: 369 if (!priv->hdmi) 370 break; 371 372 ctl = mdp5_ctlm_request(ctlm, intf->num); 373 if (!ctl) { 374 ret = -EINVAL; 375 break; 376 } 377 378 encoder = construct_encoder(mdp5_kms, intf, ctl); 379 if (IS_ERR(encoder)) { 380 ret = PTR_ERR(encoder); 381 break; 382 } 383 384 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 385 break; 386 case INTF_DSI: 387 { 388 const struct mdp5_cfg_hw *hw_cfg = 389 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 390 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); 391 392 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { 393 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", 394 intf->num); 395 ret = -EINVAL; 396 break; 397 } 398 399 if (!priv->dsi[dsi_id]) 400 break; 401 402 ctl = mdp5_ctlm_request(ctlm, intf->num); 403 if (!ctl) { 404 ret = -EINVAL; 405 break; 406 } 407 408 encoder = construct_encoder(mdp5_kms, intf, ctl); 409 if (IS_ERR(encoder)) { 410 ret = PTR_ERR(encoder); 411 break; 412 } 413 414 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 415 if (!ret) 416 mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_id])); 417 418 break; 419 } 420 default: 421 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type); 422 ret = -EINVAL; 423 break; 424 } 425 426 return ret; 427 } 428 429 static int modeset_init(struct mdp5_kms *mdp5_kms) 430 { 431 struct drm_device *dev = mdp5_kms->dev; 432 struct msm_drm_private *priv = dev->dev_private; 433 unsigned int num_crtcs; 434 int i, ret, pi = 0, ci = 0; 435 struct drm_plane *primary[MAX_BASES] = { NULL }; 436 struct drm_plane *cursor[MAX_BASES] = { NULL }; 437 438 /* 439 * Construct encoders and modeset initialize connector devices 440 * for each external display interface. 441 */ 442 for (i = 0; i < mdp5_kms->num_intfs; i++) { 443 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); 444 if (ret) 445 goto fail; 446 } 447 448 /* 449 * We should ideally have less number of encoders (set up by parsing 450 * the MDP5 interfaces) than the number of layer mixers present in HW, 451 * but let's be safe here anyway 452 */ 453 num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers); 454 455 /* 456 * Construct planes equaling the number of hw pipes, and CRTCs for the 457 * N encoders set up by the driver. The first N planes become primary 458 * planes for the CRTCs, with the remainder as overlay planes: 459 */ 460 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { 461 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; 462 struct drm_plane *plane; 463 enum drm_plane_type type; 464 465 if (i < num_crtcs) 466 type = DRM_PLANE_TYPE_PRIMARY; 467 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR) 468 type = DRM_PLANE_TYPE_CURSOR; 469 else 470 type = DRM_PLANE_TYPE_OVERLAY; 471 472 plane = mdp5_plane_init(dev, type); 473 if (IS_ERR(plane)) { 474 ret = PTR_ERR(plane); 475 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret); 476 goto fail; 477 } 478 priv->planes[priv->num_planes++] = plane; 479 480 if (type == DRM_PLANE_TYPE_PRIMARY) 481 primary[pi++] = plane; 482 if (type == DRM_PLANE_TYPE_CURSOR) 483 cursor[ci++] = plane; 484 } 485 486 for (i = 0; i < num_crtcs; i++) { 487 struct drm_crtc *crtc; 488 489 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); 490 if (IS_ERR(crtc)) { 491 ret = PTR_ERR(crtc); 492 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); 493 goto fail; 494 } 495 priv->crtcs[priv->num_crtcs++] = crtc; 496 } 497 498 /* 499 * Now that we know the number of crtcs we've created, set the possible 500 * crtcs for the encoders 501 */ 502 for (i = 0; i < priv->num_encoders; i++) { 503 struct drm_encoder *encoder = priv->encoders[i]; 504 505 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 506 } 507 508 return 0; 509 510 fail: 511 return ret; 512 } 513 514 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, 515 u32 *major, u32 *minor) 516 { 517 struct device *dev = &mdp5_kms->pdev->dev; 518 u32 version; 519 520 pm_runtime_get_sync(dev); 521 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); 522 pm_runtime_put_sync(dev); 523 524 *major = FIELD(version, MDP5_HW_VERSION_MAJOR); 525 *minor = FIELD(version, MDP5_HW_VERSION_MINOR); 526 527 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); 528 } 529 530 static int get_clk(struct platform_device *pdev, struct clk **clkp, 531 const char *name, bool mandatory) 532 { 533 struct device *dev = &pdev->dev; 534 struct clk *clk = msm_clk_get(pdev, name); 535 if (IS_ERR(clk) && mandatory) { 536 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 537 return PTR_ERR(clk); 538 } 539 if (IS_ERR(clk)) 540 DBG("skipping %s", name); 541 else 542 *clkp = clk; 543 544 return 0; 545 } 546 547 struct msm_kms *mdp5_kms_init(struct drm_device *dev) 548 { 549 struct msm_drm_private *priv = dev->dev_private; 550 struct platform_device *pdev; 551 struct mdp5_kms *mdp5_kms; 552 struct mdp5_cfg *config; 553 struct msm_kms *kms; 554 struct msm_gem_address_space *aspace; 555 int irq, i, ret; 556 struct device *iommu_dev; 557 558 /* priv->kms would have been populated by the MDP5 driver */ 559 kms = priv->kms; 560 if (!kms) 561 return NULL; 562 563 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 564 pdev = mdp5_kms->pdev; 565 566 ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs); 567 if (ret) { 568 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n"); 569 goto fail; 570 } 571 572 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 573 if (irq < 0) { 574 ret = irq; 575 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret); 576 goto fail; 577 } 578 579 kms->irq = irq; 580 581 config = mdp5_cfg_get_config(mdp5_kms->cfg); 582 583 /* make sure things are off before attaching iommu (bootloader could 584 * have left things on, in which case we'll start getting faults if 585 * we don't disable): 586 */ 587 pm_runtime_get_sync(&pdev->dev); 588 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 589 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || 590 !config->hw->intf.base[i]) 591 continue; 592 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 593 594 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); 595 } 596 mdelay(16); 597 598 if (config->platform.iommu) { 599 struct msm_mmu *mmu; 600 601 iommu_dev = &pdev->dev; 602 if (!dev_iommu_fwspec_get(iommu_dev)) 603 iommu_dev = iommu_dev->parent; 604 605 mmu = msm_iommu_new(iommu_dev, config->platform.iommu); 606 607 aspace = msm_gem_address_space_create(mmu, "mdp5", 608 0x1000, 0x100000000 - 0x1000); 609 610 if (IS_ERR(aspace)) { 611 if (!IS_ERR(mmu)) 612 mmu->funcs->destroy(mmu); 613 ret = PTR_ERR(aspace); 614 goto fail; 615 } 616 617 kms->aspace = aspace; 618 } else { 619 DRM_DEV_INFO(&pdev->dev, 620 "no iommu, fallback to phys contig buffers for scanout\n"); 621 aspace = NULL; 622 } 623 624 pm_runtime_put_sync(&pdev->dev); 625 626 ret = modeset_init(mdp5_kms); 627 if (ret) { 628 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret); 629 goto fail; 630 } 631 632 dev->mode_config.min_width = 0; 633 dev->mode_config.min_height = 0; 634 dev->mode_config.max_width = 0xffff; 635 dev->mode_config.max_height = 0xffff; 636 637 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */ 638 dev->vblank_disable_immediate = true; 639 640 return kms; 641 fail: 642 if (kms) 643 mdp5_kms_destroy(kms); 644 return ERR_PTR(ret); 645 } 646 647 static void mdp5_destroy(struct platform_device *pdev) 648 { 649 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 650 int i; 651 652 if (mdp5_kms->ctlm) 653 mdp5_ctlm_destroy(mdp5_kms->ctlm); 654 if (mdp5_kms->smp) 655 mdp5_smp_destroy(mdp5_kms->smp); 656 if (mdp5_kms->cfg) 657 mdp5_cfg_destroy(mdp5_kms->cfg); 658 659 for (i = 0; i < mdp5_kms->num_intfs; i++) 660 kfree(mdp5_kms->intfs[i]); 661 662 if (mdp5_kms->rpm_enabled) 663 pm_runtime_disable(&pdev->dev); 664 665 drm_atomic_private_obj_fini(&mdp5_kms->glob_state); 666 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); 667 } 668 669 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, 670 const enum mdp5_pipe *pipes, const uint32_t *offsets, 671 uint32_t caps) 672 { 673 struct drm_device *dev = mdp5_kms->dev; 674 int i, ret; 675 676 for (i = 0; i < cnt; i++) { 677 struct mdp5_hw_pipe *hwpipe; 678 679 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); 680 if (IS_ERR(hwpipe)) { 681 ret = PTR_ERR(hwpipe); 682 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n", 683 pipe2name(pipes[i]), ret); 684 return ret; 685 } 686 hwpipe->idx = mdp5_kms->num_hwpipes; 687 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; 688 } 689 690 return 0; 691 } 692 693 static int hwpipe_init(struct mdp5_kms *mdp5_kms) 694 { 695 static const enum mdp5_pipe rgb_planes[] = { 696 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, 697 }; 698 static const enum mdp5_pipe vig_planes[] = { 699 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, 700 }; 701 static const enum mdp5_pipe dma_planes[] = { 702 SSPP_DMA0, SSPP_DMA1, 703 }; 704 static const enum mdp5_pipe cursor_planes[] = { 705 SSPP_CURSOR0, SSPP_CURSOR1, 706 }; 707 const struct mdp5_cfg_hw *hw_cfg; 708 int ret; 709 710 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 711 712 /* Construct RGB pipes: */ 713 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, 714 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); 715 if (ret) 716 return ret; 717 718 /* Construct video (VIG) pipes: */ 719 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, 720 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); 721 if (ret) 722 return ret; 723 724 /* Construct DMA pipes: */ 725 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, 726 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); 727 if (ret) 728 return ret; 729 730 /* Construct cursor pipes: */ 731 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, 732 cursor_planes, hw_cfg->pipe_cursor.base, 733 hw_cfg->pipe_cursor.caps); 734 if (ret) 735 return ret; 736 737 return 0; 738 } 739 740 static int hwmixer_init(struct mdp5_kms *mdp5_kms) 741 { 742 struct drm_device *dev = mdp5_kms->dev; 743 const struct mdp5_cfg_hw *hw_cfg; 744 int i, ret; 745 746 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 747 748 for (i = 0; i < hw_cfg->lm.count; i++) { 749 struct mdp5_hw_mixer *mixer; 750 751 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]); 752 if (IS_ERR(mixer)) { 753 ret = PTR_ERR(mixer); 754 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n", 755 i, ret); 756 return ret; 757 } 758 759 mixer->idx = mdp5_kms->num_hwmixers; 760 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; 761 } 762 763 return 0; 764 } 765 766 static int interface_init(struct mdp5_kms *mdp5_kms) 767 { 768 struct drm_device *dev = mdp5_kms->dev; 769 const struct mdp5_cfg_hw *hw_cfg; 770 const enum mdp5_intf_type *intf_types; 771 int i; 772 773 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 774 intf_types = hw_cfg->intf.connect; 775 776 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 777 struct mdp5_interface *intf; 778 779 if (intf_types[i] == INTF_DISABLED) 780 continue; 781 782 intf = kzalloc(sizeof(*intf), GFP_KERNEL); 783 if (!intf) { 784 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i); 785 return -ENOMEM; 786 } 787 788 intf->num = i; 789 intf->type = intf_types[i]; 790 intf->mode = MDP5_INTF_MODE_NONE; 791 intf->idx = mdp5_kms->num_intfs; 792 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; 793 } 794 795 return 0; 796 } 797 798 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) 799 { 800 struct msm_drm_private *priv = dev->dev_private; 801 struct mdp5_kms *mdp5_kms; 802 struct mdp5_cfg *config; 803 u32 major, minor; 804 int ret; 805 806 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); 807 if (!mdp5_kms) { 808 ret = -ENOMEM; 809 goto fail; 810 } 811 812 platform_set_drvdata(pdev, mdp5_kms); 813 814 spin_lock_init(&mdp5_kms->resource_lock); 815 816 mdp5_kms->dev = dev; 817 mdp5_kms->pdev = pdev; 818 819 ret = mdp5_global_obj_init(mdp5_kms); 820 if (ret) 821 goto fail; 822 823 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys"); 824 if (IS_ERR(mdp5_kms->mmio)) { 825 ret = PTR_ERR(mdp5_kms->mmio); 826 goto fail; 827 } 828 829 /* mandatory clocks: */ 830 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true); 831 if (ret) 832 goto fail; 833 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true); 834 if (ret) 835 goto fail; 836 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true); 837 if (ret) 838 goto fail; 839 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true); 840 if (ret) 841 goto fail; 842 843 /* optional clocks: */ 844 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); 845 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); 846 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); 847 848 /* we need to set a default rate before enabling. Set a safe 849 * rate first, then figure out hw revision, and then set a 850 * more optimal rate: 851 */ 852 clk_set_rate(mdp5_kms->core_clk, 200000000); 853 854 pm_runtime_enable(&pdev->dev); 855 mdp5_kms->rpm_enabled = true; 856 857 read_mdp_hw_revision(mdp5_kms, &major, &minor); 858 859 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); 860 if (IS_ERR(mdp5_kms->cfg)) { 861 ret = PTR_ERR(mdp5_kms->cfg); 862 mdp5_kms->cfg = NULL; 863 goto fail; 864 } 865 866 config = mdp5_cfg_get_config(mdp5_kms->cfg); 867 mdp5_kms->caps = config->hw->mdp.caps; 868 869 /* TODO: compute core clock rate at runtime */ 870 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); 871 872 /* 873 * Some chipsets have a Shared Memory Pool (SMP), while others 874 * have dedicated latency buffering per source pipe instead; 875 * this section initializes the SMP: 876 */ 877 if (mdp5_kms->caps & MDP_CAP_SMP) { 878 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); 879 if (IS_ERR(mdp5_kms->smp)) { 880 ret = PTR_ERR(mdp5_kms->smp); 881 mdp5_kms->smp = NULL; 882 goto fail; 883 } 884 } 885 886 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); 887 if (IS_ERR(mdp5_kms->ctlm)) { 888 ret = PTR_ERR(mdp5_kms->ctlm); 889 mdp5_kms->ctlm = NULL; 890 goto fail; 891 } 892 893 ret = hwpipe_init(mdp5_kms); 894 if (ret) 895 goto fail; 896 897 ret = hwmixer_init(mdp5_kms); 898 if (ret) 899 goto fail; 900 901 ret = interface_init(mdp5_kms); 902 if (ret) 903 goto fail; 904 905 /* set uninit-ed kms */ 906 priv->kms = &mdp5_kms->base.base; 907 908 return 0; 909 fail: 910 if (mdp5_kms) 911 mdp5_destroy(pdev); 912 return ret; 913 } 914 915 static int mdp5_bind(struct device *dev, struct device *master, void *data) 916 { 917 struct msm_drm_private *priv = dev_get_drvdata(master); 918 struct drm_device *ddev = priv->dev; 919 struct platform_device *pdev = to_platform_device(dev); 920 921 DBG(""); 922 923 return mdp5_init(pdev, ddev); 924 } 925 926 static void mdp5_unbind(struct device *dev, struct device *master, 927 void *data) 928 { 929 struct platform_device *pdev = to_platform_device(dev); 930 931 mdp5_destroy(pdev); 932 } 933 934 static const struct component_ops mdp5_ops = { 935 .bind = mdp5_bind, 936 .unbind = mdp5_unbind, 937 }; 938 939 static int mdp5_setup_interconnect(struct platform_device *pdev) 940 { 941 struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem"); 942 struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem"); 943 struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem"); 944 945 if (IS_ERR(path0)) 946 return PTR_ERR(path0); 947 948 if (!path0) { 949 /* no interconnect support is not necessarily a fatal 950 * condition, the platform may simply not have an 951 * interconnect driver yet. But warn about it in case 952 * bootloader didn't setup bus clocks high enough for 953 * scanout. 954 */ 955 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n"); 956 return 0; 957 } 958 959 icc_set_bw(path0, 0, MBps_to_icc(6400)); 960 961 if (!IS_ERR_OR_NULL(path1)) 962 icc_set_bw(path1, 0, MBps_to_icc(6400)); 963 if (!IS_ERR_OR_NULL(path_rot)) 964 icc_set_bw(path_rot, 0, MBps_to_icc(6400)); 965 966 return 0; 967 } 968 969 static int mdp5_dev_probe(struct platform_device *pdev) 970 { 971 int ret; 972 973 DBG(""); 974 975 ret = mdp5_setup_interconnect(pdev); 976 if (ret) 977 return ret; 978 979 return component_add(&pdev->dev, &mdp5_ops); 980 } 981 982 static int mdp5_dev_remove(struct platform_device *pdev) 983 { 984 DBG(""); 985 component_del(&pdev->dev, &mdp5_ops); 986 return 0; 987 } 988 989 static __maybe_unused int mdp5_runtime_suspend(struct device *dev) 990 { 991 struct platform_device *pdev = to_platform_device(dev); 992 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 993 994 DBG(""); 995 996 return mdp5_disable(mdp5_kms); 997 } 998 999 static __maybe_unused int mdp5_runtime_resume(struct device *dev) 1000 { 1001 struct platform_device *pdev = to_platform_device(dev); 1002 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 1003 1004 DBG(""); 1005 1006 return mdp5_enable(mdp5_kms); 1007 } 1008 1009 static const struct dev_pm_ops mdp5_pm_ops = { 1010 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) 1011 }; 1012 1013 const struct of_device_id mdp5_dt_match[] = { 1014 { .compatible = "qcom,mdp5", }, 1015 /* to support downstream DT files */ 1016 { .compatible = "qcom,mdss_mdp", }, 1017 {} 1018 }; 1019 MODULE_DEVICE_TABLE(of, mdp5_dt_match); 1020 1021 static struct platform_driver mdp5_driver = { 1022 .probe = mdp5_dev_probe, 1023 .remove = mdp5_dev_remove, 1024 .driver = { 1025 .name = "msm_mdp", 1026 .of_match_table = mdp5_dt_match, 1027 .pm = &mdp5_pm_ops, 1028 }, 1029 }; 1030 1031 void __init msm_mdp_register(void) 1032 { 1033 DBG(""); 1034 platform_driver_register(&mdp5_driver); 1035 } 1036 1037 void __exit msm_mdp_unregister(void) 1038 { 1039 DBG(""); 1040 platform_driver_unregister(&mdp5_driver); 1041 } 1042