1 /* 2 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <drm/drm_crtc.h> 20 #include <drm/drm_probe_helper.h> 21 22 #include "mdp5_kms.h" 23 24 static struct mdp5_kms *get_kms(struct drm_encoder *encoder) 25 { 26 struct msm_drm_private *priv = encoder->dev->dev_private; 27 return to_mdp5_kms(to_mdp_kms(priv->kms)); 28 } 29 30 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING 31 #include <mach/board.h> 32 #include <mach/msm_bus.h> 33 #include <mach/msm_bus_board.h> 34 #define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val) \ 35 { \ 36 .src = MSM_BUS_MASTER_MDP_PORT0, \ 37 .dst = MSM_BUS_SLAVE_EBI_CH0, \ 38 .ab = (ab_val), \ 39 .ib = (ib_val), \ 40 } 41 42 static struct msm_bus_vectors mdp_bus_vectors[] = { 43 MDP_BUS_VECTOR_ENTRY(0, 0), 44 MDP_BUS_VECTOR_ENTRY(2000000000, 2000000000), 45 }; 46 static struct msm_bus_paths mdp_bus_usecases[] = { { 47 .num_paths = 1, 48 .vectors = &mdp_bus_vectors[0], 49 }, { 50 .num_paths = 1, 51 .vectors = &mdp_bus_vectors[1], 52 } }; 53 static struct msm_bus_scale_pdata mdp_bus_scale_table = { 54 .usecase = mdp_bus_usecases, 55 .num_usecases = ARRAY_SIZE(mdp_bus_usecases), 56 .name = "mdss_mdp", 57 }; 58 59 static void bs_init(struct mdp5_encoder *mdp5_encoder) 60 { 61 mdp5_encoder->bsc = msm_bus_scale_register_client( 62 &mdp_bus_scale_table); 63 DBG("bus scale client: %08x", mdp5_encoder->bsc); 64 } 65 66 static void bs_fini(struct mdp5_encoder *mdp5_encoder) 67 { 68 if (mdp5_encoder->bsc) { 69 msm_bus_scale_unregister_client(mdp5_encoder->bsc); 70 mdp5_encoder->bsc = 0; 71 } 72 } 73 74 static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx) 75 { 76 if (mdp5_encoder->bsc) { 77 DBG("set bus scaling: %d", idx); 78 /* HACK: scaling down, and then immediately back up 79 * seems to leave things broken (underflow).. so 80 * never disable: 81 */ 82 idx = 1; 83 msm_bus_scale_client_update_request(mdp5_encoder->bsc, idx); 84 } 85 } 86 #else 87 static void bs_init(struct mdp5_encoder *mdp5_encoder) {} 88 static void bs_fini(struct mdp5_encoder *mdp5_encoder) {} 89 static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx) {} 90 #endif 91 92 static void mdp5_encoder_destroy(struct drm_encoder *encoder) 93 { 94 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 95 bs_fini(mdp5_encoder); 96 drm_encoder_cleanup(encoder); 97 kfree(mdp5_encoder); 98 } 99 100 static const struct drm_encoder_funcs mdp5_encoder_funcs = { 101 .destroy = mdp5_encoder_destroy, 102 }; 103 104 static void mdp5_vid_encoder_mode_set(struct drm_encoder *encoder, 105 struct drm_display_mode *mode, 106 struct drm_display_mode *adjusted_mode) 107 { 108 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 109 struct mdp5_kms *mdp5_kms = get_kms(encoder); 110 struct drm_device *dev = encoder->dev; 111 struct drm_connector *connector; 112 int intf = mdp5_encoder->intf->num; 113 uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; 114 uint32_t display_v_start, display_v_end; 115 uint32_t hsync_start_x, hsync_end_x; 116 uint32_t format = 0x2100; 117 unsigned long flags; 118 119 mode = adjusted_mode; 120 121 DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode)); 122 123 ctrl_pol = 0; 124 125 /* DSI controller cannot handle active-low sync signals. */ 126 if (mdp5_encoder->intf->type != INTF_DSI) { 127 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 128 ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW; 129 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 130 ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW; 131 } 132 /* probably need to get DATA_EN polarity from panel.. */ 133 134 dtv_hsync_skew = 0; /* get this from panel? */ 135 136 /* Get color format from panel, default is 8bpc */ 137 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 138 if (connector->encoder == encoder) { 139 switch (connector->display_info.bpc) { 140 case 4: 141 format |= 0; 142 break; 143 case 5: 144 format |= 0x15; 145 break; 146 case 6: 147 format |= 0x2A; 148 break; 149 case 8: 150 default: 151 format |= 0x3F; 152 break; 153 } 154 break; 155 } 156 } 157 158 hsync_start_x = (mode->htotal - mode->hsync_start); 159 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; 160 161 vsync_period = mode->vtotal * mode->htotal; 162 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; 163 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; 164 display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1; 165 166 /* 167 * For edp only: 168 * DISPLAY_V_START = (VBP * HCYCLE) + HBP 169 * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP 170 */ 171 if (mdp5_encoder->intf->type == INTF_eDP) { 172 display_v_start += mode->htotal - mode->hsync_start; 173 display_v_end -= mode->hsync_start - mode->hdisplay; 174 } 175 176 spin_lock_irqsave(&mdp5_encoder->intf_lock, flags); 177 178 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf), 179 MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) | 180 MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal)); 181 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period); 182 mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len); 183 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf), 184 MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) | 185 MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x)); 186 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start); 187 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); 188 mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0); 189 mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff); 190 mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew); 191 mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol); 192 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf), 193 MDP5_INTF_ACTIVE_HCTL_START(0) | 194 MDP5_INTF_ACTIVE_HCTL_END(0)); 195 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0); 196 mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0); 197 mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format); 198 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */ 199 200 spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags); 201 202 mdp5_crtc_set_pipeline(encoder->crtc); 203 } 204 205 static void mdp5_vid_encoder_disable(struct drm_encoder *encoder) 206 { 207 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 208 struct mdp5_kms *mdp5_kms = get_kms(encoder); 209 struct mdp5_ctl *ctl = mdp5_encoder->ctl; 210 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); 211 struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc); 212 struct mdp5_interface *intf = mdp5_encoder->intf; 213 int intfn = mdp5_encoder->intf->num; 214 unsigned long flags; 215 216 if (WARN_ON(!mdp5_encoder->enabled)) 217 return; 218 219 mdp5_ctl_set_encoder_state(ctl, pipeline, false); 220 221 spin_lock_irqsave(&mdp5_encoder->intf_lock, flags); 222 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0); 223 spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags); 224 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); 225 226 /* 227 * Wait for a vsync so we know the ENABLE=0 latched before 228 * the (connector) source of the vsync's gets disabled, 229 * otherwise we end up in a funny state if we re-enable 230 * before the disable latches, which results that some of 231 * the settings changes for the new modeset (like new 232 * scanout buffer) don't latch properly.. 233 */ 234 mdp_irq_wait(&mdp5_kms->base, intf2vblank(mixer, intf)); 235 236 bs_set(mdp5_encoder, 0); 237 238 mdp5_encoder->enabled = false; 239 } 240 241 static void mdp5_vid_encoder_enable(struct drm_encoder *encoder) 242 { 243 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 244 struct mdp5_kms *mdp5_kms = get_kms(encoder); 245 struct mdp5_ctl *ctl = mdp5_encoder->ctl; 246 struct mdp5_interface *intf = mdp5_encoder->intf; 247 struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); 248 int intfn = intf->num; 249 unsigned long flags; 250 251 if (WARN_ON(mdp5_encoder->enabled)) 252 return; 253 254 bs_set(mdp5_encoder, 1); 255 spin_lock_irqsave(&mdp5_encoder->intf_lock, flags); 256 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1); 257 spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags); 258 mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); 259 260 mdp5_ctl_set_encoder_state(ctl, pipeline, true); 261 262 mdp5_encoder->enabled = true; 263 } 264 265 static void mdp5_encoder_mode_set(struct drm_encoder *encoder, 266 struct drm_display_mode *mode, 267 struct drm_display_mode *adjusted_mode) 268 { 269 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 270 struct mdp5_interface *intf = mdp5_encoder->intf; 271 272 if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND) 273 mdp5_cmd_encoder_mode_set(encoder, mode, adjusted_mode); 274 else 275 mdp5_vid_encoder_mode_set(encoder, mode, adjusted_mode); 276 } 277 278 static void mdp5_encoder_disable(struct drm_encoder *encoder) 279 { 280 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 281 struct mdp5_interface *intf = mdp5_encoder->intf; 282 283 if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND) 284 mdp5_cmd_encoder_disable(encoder); 285 else 286 mdp5_vid_encoder_disable(encoder); 287 } 288 289 static void mdp5_encoder_enable(struct drm_encoder *encoder) 290 { 291 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 292 struct mdp5_interface *intf = mdp5_encoder->intf; 293 /* this isn't right I think */ 294 struct drm_crtc_state *cstate = encoder->crtc->state; 295 296 mdp5_encoder_mode_set(encoder, &cstate->mode, &cstate->adjusted_mode); 297 298 if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND) 299 mdp5_cmd_encoder_enable(encoder); 300 else 301 mdp5_vid_encoder_enable(encoder); 302 } 303 304 static int mdp5_encoder_atomic_check(struct drm_encoder *encoder, 305 struct drm_crtc_state *crtc_state, 306 struct drm_connector_state *conn_state) 307 { 308 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 309 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state); 310 struct mdp5_interface *intf = mdp5_encoder->intf; 311 struct mdp5_ctl *ctl = mdp5_encoder->ctl; 312 313 mdp5_cstate->ctl = ctl; 314 mdp5_cstate->pipeline.intf = intf; 315 316 /* 317 * This is a bit awkward, but we want to flush the CTL and hit the 318 * START bit at most once for an atomic update. In the non-full- 319 * modeset case, this is done from crtc->atomic_flush(), but that 320 * is too early in the case of full modeset, in which case we 321 * defer to encoder->enable(). But we need to *know* whether 322 * encoder->enable() will be called to do this: 323 */ 324 if (drm_atomic_crtc_needs_modeset(crtc_state)) 325 mdp5_cstate->defer_start = true; 326 327 return 0; 328 } 329 330 static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = { 331 .disable = mdp5_encoder_disable, 332 .enable = mdp5_encoder_enable, 333 .atomic_check = mdp5_encoder_atomic_check, 334 }; 335 336 int mdp5_encoder_get_linecount(struct drm_encoder *encoder) 337 { 338 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 339 struct mdp5_kms *mdp5_kms = get_kms(encoder); 340 int intf = mdp5_encoder->intf->num; 341 342 return mdp5_read(mdp5_kms, REG_MDP5_INTF_LINE_COUNT(intf)); 343 } 344 345 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder) 346 { 347 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 348 struct mdp5_kms *mdp5_kms = get_kms(encoder); 349 int intf = mdp5_encoder->intf->num; 350 351 return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf)); 352 } 353 354 int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, 355 struct drm_encoder *slave_encoder) 356 { 357 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 358 struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder); 359 struct mdp5_kms *mdp5_kms; 360 struct device *dev; 361 int intf_num; 362 u32 data = 0; 363 364 if (!encoder || !slave_encoder) 365 return -EINVAL; 366 367 mdp5_kms = get_kms(encoder); 368 intf_num = mdp5_encoder->intf->num; 369 370 /* Switch slave encoder's TimingGen Sync mode, 371 * to use the master's enable signal for the slave encoder. 372 */ 373 if (intf_num == 1) 374 data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC; 375 else if (intf_num == 2) 376 data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC; 377 else 378 return -EINVAL; 379 380 dev = &mdp5_kms->pdev->dev; 381 /* Make sure clocks are on when connectors calling this function. */ 382 pm_runtime_get_sync(dev); 383 384 /* Dumb Panel, Sync mode */ 385 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); 386 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); 387 mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); 388 389 mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true); 390 391 pm_runtime_put_sync(dev); 392 393 return 0; 394 } 395 396 void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode) 397 { 398 struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); 399 struct mdp5_interface *intf = mdp5_encoder->intf; 400 401 /* TODO: Expand this to set writeback modes too */ 402 if (cmd_mode) { 403 WARN_ON(intf->type != INTF_DSI); 404 intf->mode = MDP5_INTF_DSI_MODE_COMMAND; 405 } else { 406 if (intf->type == INTF_DSI) 407 intf->mode = MDP5_INTF_DSI_MODE_VIDEO; 408 else 409 intf->mode = MDP5_INTF_MODE_NONE; 410 } 411 } 412 413 /* initialize encoder */ 414 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, 415 struct mdp5_interface *intf, 416 struct mdp5_ctl *ctl) 417 { 418 struct drm_encoder *encoder = NULL; 419 struct mdp5_encoder *mdp5_encoder; 420 int enc_type = (intf->type == INTF_DSI) ? 421 DRM_MODE_ENCODER_DSI : DRM_MODE_ENCODER_TMDS; 422 int ret; 423 424 mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL); 425 if (!mdp5_encoder) { 426 ret = -ENOMEM; 427 goto fail; 428 } 429 430 encoder = &mdp5_encoder->base; 431 mdp5_encoder->ctl = ctl; 432 mdp5_encoder->intf = intf; 433 434 spin_lock_init(&mdp5_encoder->intf_lock); 435 436 drm_encoder_init(dev, encoder, &mdp5_encoder_funcs, enc_type, NULL); 437 438 drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs); 439 440 bs_init(mdp5_encoder); 441 442 return encoder; 443 444 fail: 445 if (encoder) 446 mdp5_encoder_destroy(encoder); 447 448 return ERR_PTR(ret); 449 } 450