1 /*
2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 and
6  * only version 2 as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #include "mdp5_kms.h"
15 #include "mdp5_ctl.h"
16 
17 /*
18  * CTL - MDP Control Pool Manager
19  *
20  * Controls are shared between all display interfaces.
21  *
22  * They are intended to be used for data path configuration.
23  * The top level register programming describes the complete data path for
24  * a specific data path ID - REG_MDP5_CTL_*(<id>, ...)
25  *
26  * Hardware capabilities determine the number of concurrent data paths
27  *
28  * In certain use cases (high-resolution dual pipe), one single CTL can be
29  * shared across multiple CRTCs.
30  */
31 
32 #define CTL_STAT_BUSY		0x1
33 #define CTL_STAT_BOOKED	0x2
34 
35 struct mdp5_ctl {
36 	struct mdp5_ctl_manager *ctlm;
37 
38 	u32 id;
39 
40 	/* CTL status bitmask */
41 	u32 status;
42 
43 	bool encoder_enabled;
44 
45 	/* pending flush_mask bits */
46 	u32 flush_mask;
47 
48 	/* REG_MDP5_CTL_*(<id>) registers access info + lock: */
49 	spinlock_t hw_lock;
50 	u32 reg_offset;
51 
52 	/* when do CTL registers need to be flushed? (mask of trigger bits) */
53 	u32 pending_ctl_trigger;
54 
55 	bool cursor_on;
56 
57 	/* True if the current CTL has FLUSH bits pending for single FLUSH. */
58 	bool flush_pending;
59 
60 	struct mdp5_ctl *pair; /* Paired CTL to be flushed together */
61 };
62 
63 struct mdp5_ctl_manager {
64 	struct drm_device *dev;
65 
66 	/* number of CTL / Layer Mixers in this hw config: */
67 	u32 nlm;
68 	u32 nctl;
69 
70 	/* to filter out non-present bits in the current hardware config */
71 	u32 flush_hw_mask;
72 
73 	/* status for single FLUSH */
74 	bool single_flush_supported;
75 	u32 single_flush_pending_mask;
76 
77 	/* pool of CTLs + lock to protect resource allocation (ctls[i].busy) */
78 	spinlock_t pool_lock;
79 	struct mdp5_ctl ctls[MAX_CTL];
80 };
81 
82 static inline
83 struct mdp5_kms *get_kms(struct mdp5_ctl_manager *ctl_mgr)
84 {
85 	struct msm_drm_private *priv = ctl_mgr->dev->dev_private;
86 
87 	return to_mdp5_kms(to_mdp_kms(priv->kms));
88 }
89 
90 static inline
91 void ctl_write(struct mdp5_ctl *ctl, u32 reg, u32 data)
92 {
93 	struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm);
94 
95 	(void)ctl->reg_offset; /* TODO use this instead of mdp5_write */
96 	mdp5_write(mdp5_kms, reg, data);
97 }
98 
99 static inline
100 u32 ctl_read(struct mdp5_ctl *ctl, u32 reg)
101 {
102 	struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm);
103 
104 	(void)ctl->reg_offset; /* TODO use this instead of mdp5_write */
105 	return mdp5_read(mdp5_kms, reg);
106 }
107 
108 static void set_display_intf(struct mdp5_kms *mdp5_kms,
109 		struct mdp5_interface *intf)
110 {
111 	unsigned long flags;
112 	u32 intf_sel;
113 
114 	spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
115 	intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
116 
117 	switch (intf->num) {
118 	case 0:
119 		intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
120 		intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf->type);
121 		break;
122 	case 1:
123 		intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
124 		intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf->type);
125 		break;
126 	case 2:
127 		intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
128 		intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf->type);
129 		break;
130 	case 3:
131 		intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
132 		intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf->type);
133 		break;
134 	default:
135 		BUG();
136 		break;
137 	}
138 
139 	mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
140 	spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
141 }
142 
143 static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
144 {
145 	unsigned long flags;
146 	struct mdp5_interface *intf = pipeline->intf;
147 	u32 ctl_op = 0;
148 
149 	if (!mdp5_cfg_intf_is_virtual(intf->type))
150 		ctl_op |= MDP5_CTL_OP_INTF_NUM(INTF0 + intf->num);
151 
152 	switch (intf->type) {
153 	case INTF_DSI:
154 		if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
155 			ctl_op |= MDP5_CTL_OP_CMD_MODE;
156 		break;
157 
158 	case INTF_WB:
159 		if (intf->mode == MDP5_INTF_WB_MODE_LINE)
160 			ctl_op |= MDP5_CTL_OP_MODE(MODE_WB_2_LINE);
161 		break;
162 
163 	default:
164 		break;
165 	}
166 
167 	if (pipeline->r_mixer)
168 		ctl_op |= MDP5_CTL_OP_PACK_3D_ENABLE |
169 			  MDP5_CTL_OP_PACK_3D(1);
170 
171 	spin_lock_irqsave(&ctl->hw_lock, flags);
172 	ctl_write(ctl, REG_MDP5_CTL_OP(ctl->id), ctl_op);
173 	spin_unlock_irqrestore(&ctl->hw_lock, flags);
174 }
175 
176 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)
177 {
178 	struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm);
179 	struct mdp5_interface *intf = pipeline->intf;
180 
181 	/* Virtual interfaces need not set a display intf (e.g.: Writeback) */
182 	if (!mdp5_cfg_intf_is_virtual(intf->type))
183 		set_display_intf(mdp5_kms, intf);
184 
185 	set_ctl_op(ctl, pipeline);
186 
187 	return 0;
188 }
189 
190 static bool start_signal_needed(struct mdp5_ctl *ctl,
191 				struct mdp5_pipeline *pipeline)
192 {
193 	struct mdp5_interface *intf = pipeline->intf;
194 
195 	if (!ctl->encoder_enabled)
196 		return false;
197 
198 	switch (intf->type) {
199 	case INTF_WB:
200 		return true;
201 	case INTF_DSI:
202 		return intf->mode == MDP5_INTF_DSI_MODE_COMMAND;
203 	default:
204 		return false;
205 	}
206 }
207 
208 /*
209  * send_start_signal() - Overlay Processor Start Signal
210  *
211  * For a given control operation (display pipeline), a START signal needs to be
212  * executed in order to kick off operation and activate all layers.
213  * e.g.: DSI command mode, Writeback
214  */
215 static void send_start_signal(struct mdp5_ctl *ctl)
216 {
217 	unsigned long flags;
218 
219 	spin_lock_irqsave(&ctl->hw_lock, flags);
220 	ctl_write(ctl, REG_MDP5_CTL_START(ctl->id), 1);
221 	spin_unlock_irqrestore(&ctl->hw_lock, flags);
222 }
223 
224 /**
225  * mdp5_ctl_set_encoder_state() - set the encoder state
226  *
227  * @enable: true, when encoder is ready for data streaming; false, otherwise.
228  *
229  * Note:
230  * This encoder state is needed to trigger START signal (data path kickoff).
231  */
232 int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl,
233 			       struct mdp5_pipeline *pipeline,
234 			       bool enabled)
235 {
236 	struct mdp5_interface *intf = pipeline->intf;
237 
238 	if (WARN_ON(!ctl))
239 		return -EINVAL;
240 
241 	ctl->encoder_enabled = enabled;
242 	DBG("intf_%d: %s", intf->num, enabled ? "on" : "off");
243 
244 	if (start_signal_needed(ctl, pipeline)) {
245 		send_start_signal(ctl);
246 	}
247 
248 	return 0;
249 }
250 
251 /*
252  * Note:
253  * CTL registers need to be flushed after calling this function
254  * (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
255  */
256 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
257 			int cursor_id, bool enable)
258 {
259 	struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
260 	unsigned long flags;
261 	u32 blend_cfg;
262 	struct mdp5_hw_mixer *mixer = pipeline->mixer;
263 
264 	if (unlikely(WARN_ON(!mixer))) {
265 		DRM_DEV_ERROR(ctl_mgr->dev->dev, "CTL %d cannot find LM",
266 			ctl->id);
267 		return -EINVAL;
268 	}
269 
270 	if (pipeline->r_mixer) {
271 		DRM_DEV_ERROR(ctl_mgr->dev->dev, "unsupported configuration");
272 		return -EINVAL;
273 	}
274 
275 	spin_lock_irqsave(&ctl->hw_lock, flags);
276 
277 	blend_cfg = ctl_read(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, mixer->lm));
278 
279 	if (enable)
280 		blend_cfg |=  MDP5_CTL_LAYER_REG_CURSOR_OUT;
281 	else
282 		blend_cfg &= ~MDP5_CTL_LAYER_REG_CURSOR_OUT;
283 
284 	ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, mixer->lm), blend_cfg);
285 	ctl->cursor_on = enable;
286 
287 	spin_unlock_irqrestore(&ctl->hw_lock, flags);
288 
289 	ctl->pending_ctl_trigger = mdp_ctl_flush_mask_cursor(cursor_id);
290 
291 	return 0;
292 }
293 
294 static u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
295 		enum mdp_mixer_stage_id stage)
296 {
297 	switch (pipe) {
298 	case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage);
299 	case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage);
300 	case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage);
301 	case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage);
302 	case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage);
303 	case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage);
304 	case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage);
305 	case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage);
306 	case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage);
307 	case SSPP_RGB3: return MDP5_CTL_LAYER_REG_RGB3(stage);
308 	case SSPP_CURSOR0:
309 	case SSPP_CURSOR1:
310 	default:	return 0;
311 	}
312 }
313 
314 static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe,
315 		enum mdp_mixer_stage_id stage)
316 {
317 	if (stage < STAGE6 && (pipe != SSPP_CURSOR0 && pipe != SSPP_CURSOR1))
318 		return 0;
319 
320 	switch (pipe) {
321 	case SSPP_VIG0: return MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3;
322 	case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3;
323 	case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3;
324 	case SSPP_RGB0: return MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3;
325 	case SSPP_RGB1: return MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3;
326 	case SSPP_RGB2: return MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3;
327 	case SSPP_DMA0: return MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3;
328 	case SSPP_DMA1: return MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3;
329 	case SSPP_VIG3: return MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3;
330 	case SSPP_RGB3: return MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3;
331 	case SSPP_CURSOR0: return MDP5_CTL_LAYER_EXT_REG_CURSOR0(stage);
332 	case SSPP_CURSOR1: return MDP5_CTL_LAYER_EXT_REG_CURSOR1(stage);
333 	default:	return 0;
334 	}
335 }
336 
337 static void mdp5_ctl_reset_blend_regs(struct mdp5_ctl *ctl)
338 {
339 	unsigned long flags;
340 	struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
341 	int i;
342 
343 	spin_lock_irqsave(&ctl->hw_lock, flags);
344 
345 	for (i = 0; i < ctl_mgr->nlm; i++) {
346 		ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, i), 0x0);
347 		ctl_write(ctl, REG_MDP5_CTL_LAYER_EXT_REG(ctl->id, i), 0x0);
348 	}
349 
350 	spin_unlock_irqrestore(&ctl->hw_lock, flags);
351 }
352 
353 #define PIPE_LEFT	0
354 #define PIPE_RIGHT	1
355 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
356 		   enum mdp5_pipe stage[][MAX_PIPE_STAGE],
357 		   enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],
358 		   u32 stage_cnt, u32 ctl_blend_op_flags)
359 {
360 	struct mdp5_hw_mixer *mixer = pipeline->mixer;
361 	struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
362 	unsigned long flags;
363 	u32 blend_cfg = 0, blend_ext_cfg = 0;
364 	u32 r_blend_cfg = 0, r_blend_ext_cfg = 0;
365 	int i, start_stage;
366 
367 	mdp5_ctl_reset_blend_regs(ctl);
368 
369 	if (ctl_blend_op_flags & MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT) {
370 		start_stage = STAGE0;
371 		blend_cfg |= MDP5_CTL_LAYER_REG_BORDER_COLOR;
372 		if (r_mixer)
373 			r_blend_cfg |= MDP5_CTL_LAYER_REG_BORDER_COLOR;
374 	} else {
375 		start_stage = STAGE_BASE;
376 	}
377 
378 	for (i = start_stage; stage_cnt && i <= STAGE_MAX; i++) {
379 		blend_cfg |=
380 			mdp_ctl_blend_mask(stage[i][PIPE_LEFT], i) |
381 			mdp_ctl_blend_mask(stage[i][PIPE_RIGHT], i);
382 		blend_ext_cfg |=
383 			mdp_ctl_blend_ext_mask(stage[i][PIPE_LEFT], i) |
384 			mdp_ctl_blend_ext_mask(stage[i][PIPE_RIGHT], i);
385 		if (r_mixer) {
386 			r_blend_cfg |=
387 				mdp_ctl_blend_mask(r_stage[i][PIPE_LEFT], i) |
388 				mdp_ctl_blend_mask(r_stage[i][PIPE_RIGHT], i);
389 			r_blend_ext_cfg |=
390 			     mdp_ctl_blend_ext_mask(r_stage[i][PIPE_LEFT], i) |
391 			     mdp_ctl_blend_ext_mask(r_stage[i][PIPE_RIGHT], i);
392 		}
393 	}
394 
395 	spin_lock_irqsave(&ctl->hw_lock, flags);
396 	if (ctl->cursor_on)
397 		blend_cfg |=  MDP5_CTL_LAYER_REG_CURSOR_OUT;
398 
399 	ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, mixer->lm), blend_cfg);
400 	ctl_write(ctl, REG_MDP5_CTL_LAYER_EXT_REG(ctl->id, mixer->lm),
401 		  blend_ext_cfg);
402 	if (r_mixer) {
403 		ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, r_mixer->lm),
404 			  r_blend_cfg);
405 		ctl_write(ctl, REG_MDP5_CTL_LAYER_EXT_REG(ctl->id, r_mixer->lm),
406 			  r_blend_ext_cfg);
407 	}
408 	spin_unlock_irqrestore(&ctl->hw_lock, flags);
409 
410 	ctl->pending_ctl_trigger = mdp_ctl_flush_mask_lm(mixer->lm);
411 	if (r_mixer)
412 		ctl->pending_ctl_trigger |= mdp_ctl_flush_mask_lm(r_mixer->lm);
413 
414 	DBG("lm%d: blend config = 0x%08x. ext_cfg = 0x%08x", mixer->lm,
415 		blend_cfg, blend_ext_cfg);
416 	if (r_mixer)
417 		DBG("lm%d: blend config = 0x%08x. ext_cfg = 0x%08x",
418 		    r_mixer->lm, r_blend_cfg, r_blend_ext_cfg);
419 
420 	return 0;
421 }
422 
423 u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf)
424 {
425 	if (intf->type == INTF_WB)
426 		return MDP5_CTL_FLUSH_WB;
427 
428 	switch (intf->num) {
429 	case 0: return MDP5_CTL_FLUSH_TIMING_0;
430 	case 1: return MDP5_CTL_FLUSH_TIMING_1;
431 	case 2: return MDP5_CTL_FLUSH_TIMING_2;
432 	case 3: return MDP5_CTL_FLUSH_TIMING_3;
433 	default: return 0;
434 	}
435 }
436 
437 u32 mdp_ctl_flush_mask_cursor(int cursor_id)
438 {
439 	switch (cursor_id) {
440 	case 0: return MDP5_CTL_FLUSH_CURSOR_0;
441 	case 1: return MDP5_CTL_FLUSH_CURSOR_1;
442 	default: return 0;
443 	}
444 }
445 
446 u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe)
447 {
448 	switch (pipe) {
449 	case SSPP_VIG0: return MDP5_CTL_FLUSH_VIG0;
450 	case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1;
451 	case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2;
452 	case SSPP_RGB0: return MDP5_CTL_FLUSH_RGB0;
453 	case SSPP_RGB1: return MDP5_CTL_FLUSH_RGB1;
454 	case SSPP_RGB2: return MDP5_CTL_FLUSH_RGB2;
455 	case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0;
456 	case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1;
457 	case SSPP_VIG3: return MDP5_CTL_FLUSH_VIG3;
458 	case SSPP_RGB3: return MDP5_CTL_FLUSH_RGB3;
459 	case SSPP_CURSOR0: return MDP5_CTL_FLUSH_CURSOR_0;
460 	case SSPP_CURSOR1: return MDP5_CTL_FLUSH_CURSOR_1;
461 	default:        return 0;
462 	}
463 }
464 
465 u32 mdp_ctl_flush_mask_lm(int lm)
466 {
467 	switch (lm) {
468 	case 0:  return MDP5_CTL_FLUSH_LM0;
469 	case 1:  return MDP5_CTL_FLUSH_LM1;
470 	case 2:  return MDP5_CTL_FLUSH_LM2;
471 	case 3:  return MDP5_CTL_FLUSH_LM3;
472 	case 4:  return MDP5_CTL_FLUSH_LM4;
473 	case 5:  return MDP5_CTL_FLUSH_LM5;
474 	default: return 0;
475 	}
476 }
477 
478 static u32 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
479 			u32 flush_mask)
480 {
481 	struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
482 	u32 sw_mask = 0;
483 #define BIT_NEEDS_SW_FIX(bit) \
484 	(!(ctl_mgr->flush_hw_mask & bit) && (flush_mask & bit))
485 
486 	/* for some targets, cursor bit is the same as LM bit */
487 	if (BIT_NEEDS_SW_FIX(MDP5_CTL_FLUSH_CURSOR_0))
488 		sw_mask |= mdp_ctl_flush_mask_lm(pipeline->mixer->lm);
489 
490 	return sw_mask;
491 }
492 
493 static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask,
494 		u32 *flush_id)
495 {
496 	struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
497 
498 	if (ctl->pair) {
499 		DBG("CTL %d FLUSH pending mask %x", ctl->id, *flush_mask);
500 		ctl->flush_pending = true;
501 		ctl_mgr->single_flush_pending_mask |= (*flush_mask);
502 		*flush_mask = 0;
503 
504 		if (ctl->pair->flush_pending) {
505 			*flush_id = min_t(u32, ctl->id, ctl->pair->id);
506 			*flush_mask = ctl_mgr->single_flush_pending_mask;
507 
508 			ctl->flush_pending = false;
509 			ctl->pair->flush_pending = false;
510 			ctl_mgr->single_flush_pending_mask = 0;
511 
512 			DBG("Single FLUSH mask %x,ID %d", *flush_mask,
513 				*flush_id);
514 		}
515 	}
516 }
517 
518 /**
519  * mdp5_ctl_commit() - Register Flush
520  *
521  * The flush register is used to indicate several registers are all
522  * programmed, and are safe to update to the back copy of the double
523  * buffered registers.
524  *
525  * Some registers FLUSH bits are shared when the hardware does not have
526  * dedicated bits for them; handling these is the job of fix_sw_flush().
527  *
528  * CTL registers need to be flushed in some circumstances; if that is the
529  * case, some trigger bits will be present in both flush mask and
530  * ctl->pending_ctl_trigger.
531  *
532  * Return H/W flushed bit mask.
533  */
534 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl,
535 		    struct mdp5_pipeline *pipeline,
536 		    u32 flush_mask, bool start)
537 {
538 	struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
539 	unsigned long flags;
540 	u32 flush_id = ctl->id;
541 	u32 curr_ctl_flush_mask;
542 
543 	VERB("flush_mask=%x, trigger=%x", flush_mask, ctl->pending_ctl_trigger);
544 
545 	if (ctl->pending_ctl_trigger & flush_mask) {
546 		flush_mask |= MDP5_CTL_FLUSH_CTL;
547 		ctl->pending_ctl_trigger = 0;
548 	}
549 
550 	flush_mask |= fix_sw_flush(ctl, pipeline, flush_mask);
551 
552 	flush_mask &= ctl_mgr->flush_hw_mask;
553 
554 	curr_ctl_flush_mask = flush_mask;
555 
556 	fix_for_single_flush(ctl, &flush_mask, &flush_id);
557 
558 	if (!start) {
559 		ctl->flush_mask |= flush_mask;
560 		return curr_ctl_flush_mask;
561 	} else {
562 		flush_mask |= ctl->flush_mask;
563 		ctl->flush_mask = 0;
564 	}
565 
566 	if (flush_mask) {
567 		spin_lock_irqsave(&ctl->hw_lock, flags);
568 		ctl_write(ctl, REG_MDP5_CTL_FLUSH(flush_id), flush_mask);
569 		spin_unlock_irqrestore(&ctl->hw_lock, flags);
570 	}
571 
572 	if (start_signal_needed(ctl, pipeline)) {
573 		send_start_signal(ctl);
574 	}
575 
576 	return curr_ctl_flush_mask;
577 }
578 
579 u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl)
580 {
581 	return ctl_read(ctl, REG_MDP5_CTL_FLUSH(ctl->id));
582 }
583 
584 int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl)
585 {
586 	return WARN_ON(!ctl) ? -EINVAL : ctl->id;
587 }
588 
589 /*
590  * mdp5_ctl_pair() - Associate 2 booked CTLs for single FLUSH
591  */
592 int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable)
593 {
594 	struct mdp5_ctl_manager *ctl_mgr = ctlx->ctlm;
595 	struct mdp5_kms *mdp5_kms = get_kms(ctl_mgr);
596 
597 	/* do nothing silently if hw doesn't support */
598 	if (!ctl_mgr->single_flush_supported)
599 		return 0;
600 
601 	if (!enable) {
602 		ctlx->pair = NULL;
603 		ctly->pair = NULL;
604 		mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, 0);
605 		return 0;
606 	} else if ((ctlx->pair != NULL) || (ctly->pair != NULL)) {
607 		DRM_DEV_ERROR(ctl_mgr->dev->dev, "CTLs already paired\n");
608 		return -EINVAL;
609 	} else if (!(ctlx->status & ctly->status & CTL_STAT_BOOKED)) {
610 		DRM_DEV_ERROR(ctl_mgr->dev->dev, "Only pair booked CTLs\n");
611 		return -EINVAL;
612 	}
613 
614 	ctlx->pair = ctly;
615 	ctly->pair = ctlx;
616 
617 	mdp5_write(mdp5_kms, REG_MDP5_SPARE_0,
618 		   MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN);
619 
620 	return 0;
621 }
622 
623 /*
624  * mdp5_ctl_request() - CTL allocation
625  *
626  * Try to return booked CTL for @intf_num is 1 or 2, unbooked for other INTFs.
627  * If no CTL is available in preferred category, allocate from the other one.
628  *
629  * @return fail if no CTL is available.
630  */
631 struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr,
632 		int intf_num)
633 {
634 	struct mdp5_ctl *ctl = NULL;
635 	const u32 checkm = CTL_STAT_BUSY | CTL_STAT_BOOKED;
636 	u32 match = ((intf_num == 1) || (intf_num == 2)) ? CTL_STAT_BOOKED : 0;
637 	unsigned long flags;
638 	int c;
639 
640 	spin_lock_irqsave(&ctl_mgr->pool_lock, flags);
641 
642 	/* search the preferred */
643 	for (c = 0; c < ctl_mgr->nctl; c++)
644 		if ((ctl_mgr->ctls[c].status & checkm) == match)
645 			goto found;
646 
647 	dev_warn(ctl_mgr->dev->dev,
648 		"fall back to the other CTL category for INTF %d!\n", intf_num);
649 
650 	match ^= CTL_STAT_BOOKED;
651 	for (c = 0; c < ctl_mgr->nctl; c++)
652 		if ((ctl_mgr->ctls[c].status & checkm) == match)
653 			goto found;
654 
655 	DRM_DEV_ERROR(ctl_mgr->dev->dev, "No more CTL available!");
656 	goto unlock;
657 
658 found:
659 	ctl = &ctl_mgr->ctls[c];
660 	ctl->status |= CTL_STAT_BUSY;
661 	ctl->pending_ctl_trigger = 0;
662 	DBG("CTL %d allocated", ctl->id);
663 
664 unlock:
665 	spin_unlock_irqrestore(&ctl_mgr->pool_lock, flags);
666 	return ctl;
667 }
668 
669 void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctl_mgr)
670 {
671 	unsigned long flags;
672 	int c;
673 
674 	for (c = 0; c < ctl_mgr->nctl; c++) {
675 		struct mdp5_ctl *ctl = &ctl_mgr->ctls[c];
676 
677 		spin_lock_irqsave(&ctl->hw_lock, flags);
678 		ctl_write(ctl, REG_MDP5_CTL_OP(ctl->id), 0);
679 		spin_unlock_irqrestore(&ctl->hw_lock, flags);
680 	}
681 }
682 
683 void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctl_mgr)
684 {
685 	kfree(ctl_mgr);
686 }
687 
688 struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
689 		void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd)
690 {
691 	struct mdp5_ctl_manager *ctl_mgr;
692 	const struct mdp5_cfg_hw *hw_cfg = mdp5_cfg_get_hw_config(cfg_hnd);
693 	int rev = mdp5_cfg_get_hw_rev(cfg_hnd);
694 	unsigned dsi_cnt = 0;
695 	const struct mdp5_ctl_block *ctl_cfg = &hw_cfg->ctl;
696 	unsigned long flags;
697 	int c, ret;
698 
699 	ctl_mgr = kzalloc(sizeof(*ctl_mgr), GFP_KERNEL);
700 	if (!ctl_mgr) {
701 		DRM_DEV_ERROR(dev->dev, "failed to allocate CTL manager\n");
702 		ret = -ENOMEM;
703 		goto fail;
704 	}
705 
706 	if (unlikely(WARN_ON(ctl_cfg->count > MAX_CTL))) {
707 		DRM_DEV_ERROR(dev->dev, "Increase static pool size to at least %d\n",
708 				ctl_cfg->count);
709 		ret = -ENOSPC;
710 		goto fail;
711 	}
712 
713 	/* initialize the CTL manager: */
714 	ctl_mgr->dev = dev;
715 	ctl_mgr->nlm = hw_cfg->lm.count;
716 	ctl_mgr->nctl = ctl_cfg->count;
717 	ctl_mgr->flush_hw_mask = ctl_cfg->flush_hw_mask;
718 	spin_lock_init(&ctl_mgr->pool_lock);
719 
720 	/* initialize each CTL of the pool: */
721 	spin_lock_irqsave(&ctl_mgr->pool_lock, flags);
722 	for (c = 0; c < ctl_mgr->nctl; c++) {
723 		struct mdp5_ctl *ctl = &ctl_mgr->ctls[c];
724 
725 		if (WARN_ON(!ctl_cfg->base[c])) {
726 			DRM_DEV_ERROR(dev->dev, "CTL_%d: base is null!\n", c);
727 			ret = -EINVAL;
728 			spin_unlock_irqrestore(&ctl_mgr->pool_lock, flags);
729 			goto fail;
730 		}
731 		ctl->ctlm = ctl_mgr;
732 		ctl->id = c;
733 		ctl->reg_offset = ctl_cfg->base[c];
734 		ctl->status = 0;
735 		spin_lock_init(&ctl->hw_lock);
736 	}
737 
738 	/*
739 	 * In Dual DSI case, CTL0 and CTL1 are always assigned to two DSI
740 	 * interfaces to support single FLUSH feature (Flush CTL0 and CTL1 when
741 	 * only write into CTL0's FLUSH register) to keep two DSI pipes in sync.
742 	 * Single FLUSH is supported from hw rev v3.0.
743 	 */
744 	for (c = 0; c < ARRAY_SIZE(hw_cfg->intf.connect); c++)
745 		if (hw_cfg->intf.connect[c] == INTF_DSI)
746 			dsi_cnt++;
747 	if ((rev >= 3) && (dsi_cnt > 1)) {
748 		ctl_mgr->single_flush_supported = true;
749 		/* Reserve CTL0/1 for INTF1/2 */
750 		ctl_mgr->ctls[0].status |= CTL_STAT_BOOKED;
751 		ctl_mgr->ctls[1].status |= CTL_STAT_BOOKED;
752 	}
753 	spin_unlock_irqrestore(&ctl_mgr->pool_lock, flags);
754 	DBG("Pool of %d CTLs created.", ctl_mgr->nctl);
755 
756 	return ctl_mgr;
757 
758 fail:
759 	if (ctl_mgr)
760 		mdp5_ctlm_destroy(ctl_mgr);
761 
762 	return ERR_PTR(ret);
763 }
764