1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #include <linux/sort.h>
9 
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_mode.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_flip_work.h>
14 #include <drm/drm_fourcc.h>
15 #include <drm/drm_probe_helper.h>
16 #include <drm/drm_vblank.h>
17 
18 #include "mdp5_kms.h"
19 #include "msm_gem.h"
20 
21 #define CURSOR_WIDTH	64
22 #define CURSOR_HEIGHT	64
23 
24 struct mdp5_crtc {
25 	struct drm_crtc base;
26 	int id;
27 	bool enabled;
28 
29 	spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
30 
31 	/* if there is a pending flip, these will be non-null: */
32 	struct drm_pending_vblank_event *event;
33 
34 	/* Bits have been flushed at the last commit,
35 	 * used to decide if a vsync has happened since last commit.
36 	 */
37 	u32 flushed_mask;
38 
39 #define PENDING_CURSOR 0x1
40 #define PENDING_FLIP   0x2
41 	atomic_t pending;
42 
43 	/* for unref'ing cursor bo's after scanout completes: */
44 	struct drm_flip_work unref_cursor_work;
45 
46 	struct mdp_irq vblank;
47 	struct mdp_irq err;
48 	struct mdp_irq pp_done;
49 
50 	struct completion pp_completion;
51 
52 	bool lm_cursor_enabled;
53 
54 	struct {
55 		/* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
56 		spinlock_t lock;
57 
58 		/* current cursor being scanned out: */
59 		struct drm_gem_object *scanout_bo;
60 		uint64_t iova;
61 		uint32_t width, height;
62 		int x, y;
63 	} cursor;
64 };
65 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
66 
67 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc);
68 
69 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
70 {
71 	struct msm_drm_private *priv = crtc->dev->dev_private;
72 	return to_mdp5_kms(to_mdp_kms(priv->kms));
73 }
74 
75 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
76 {
77 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
78 
79 	atomic_or(pending, &mdp5_crtc->pending);
80 	mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
81 }
82 
83 static void request_pp_done_pending(struct drm_crtc *crtc)
84 {
85 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
86 	reinit_completion(&mdp5_crtc->pp_completion);
87 }
88 
89 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
90 {
91 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
92 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
93 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
94 	bool start = !mdp5_cstate->defer_start;
95 
96 	mdp5_cstate->defer_start = false;
97 
98 	DBG("%s: flush=%08x", crtc->name, flush_mask);
99 
100 	return mdp5_ctl_commit(ctl, pipeline, flush_mask, start);
101 }
102 
103 /*
104  * flush updates, to make sure hw is updated to new scanout fb,
105  * so that we can safely queue unref to current fb (ie. next
106  * vblank we know hw is done w/ previous scanout_fb).
107  */
108 static u32 crtc_flush_all(struct drm_crtc *crtc)
109 {
110 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
111 	struct mdp5_hw_mixer *mixer, *r_mixer;
112 	struct drm_plane *plane;
113 	uint32_t flush_mask = 0;
114 
115 	/* this should not happen: */
116 	if (WARN_ON(!mdp5_cstate->ctl))
117 		return 0;
118 
119 	drm_atomic_crtc_for_each_plane(plane, crtc) {
120 		if (!plane->state->visible)
121 			continue;
122 		flush_mask |= mdp5_plane_get_flush(plane);
123 	}
124 
125 	mixer = mdp5_cstate->pipeline.mixer;
126 	flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm);
127 
128 	r_mixer = mdp5_cstate->pipeline.r_mixer;
129 	if (r_mixer)
130 		flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm);
131 
132 	return crtc_flush(crtc, flush_mask);
133 }
134 
135 /* if file!=NULL, this is preclose potential cancel-flip path */
136 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
137 {
138 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
139 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
140 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
141 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
142 	struct drm_device *dev = crtc->dev;
143 	struct drm_pending_vblank_event *event;
144 	unsigned long flags;
145 
146 	spin_lock_irqsave(&dev->event_lock, flags);
147 	event = mdp5_crtc->event;
148 	if (event) {
149 		mdp5_crtc->event = NULL;
150 		DBG("%s: send event: %p", crtc->name, event);
151 		drm_crtc_send_vblank_event(crtc, event);
152 	}
153 	spin_unlock_irqrestore(&dev->event_lock, flags);
154 
155 	if (ctl && !crtc->state->enable) {
156 		/* set STAGE_UNUSED for all layers */
157 		mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0);
158 		/* XXX: What to do here? */
159 		/* mdp5_crtc->ctl = NULL; */
160 	}
161 }
162 
163 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
164 {
165 	struct mdp5_crtc *mdp5_crtc =
166 		container_of(work, struct mdp5_crtc, unref_cursor_work);
167 	struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
168 	struct msm_kms *kms = &mdp5_kms->base.base;
169 
170 	msm_gem_unpin_iova(val, kms->aspace);
171 	drm_gem_object_put(val);
172 }
173 
174 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
175 {
176 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
177 
178 	drm_crtc_cleanup(crtc);
179 	drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
180 
181 	kfree(mdp5_crtc);
182 }
183 
184 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage)
185 {
186 	switch (stage) {
187 	case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA;
188 	case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA;
189 	case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA;
190 	case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA;
191 	case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA;
192 	case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA;
193 	case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA;
194 	default:
195 		return 0;
196 	}
197 }
198 
199 /*
200  * left/right pipe offsets for the stage array used in blend_setup()
201  */
202 #define PIPE_LEFT	0
203 #define PIPE_RIGHT	1
204 
205 /*
206  * blend_setup() - blend all the planes of a CRTC
207  *
208  * If no base layer is available, border will be enabled as the base layer.
209  * Otherwise all layers will be blended based on their stage calculated
210  * in mdp5_crtc_atomic_check.
211  */
212 static void blend_setup(struct drm_crtc *crtc)
213 {
214 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
215 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
216 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
217 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
218 	struct drm_plane *plane;
219 	struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
220 	const struct mdp_format *format;
221 	struct mdp5_hw_mixer *mixer = pipeline->mixer;
222 	uint32_t lm = mixer->lm;
223 	struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
224 	uint32_t r_lm = r_mixer ? r_mixer->lm : 0;
225 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
226 	uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
227 	unsigned long flags;
228 	enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
229 	enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
230 	int i, plane_cnt = 0;
231 	bool bg_alpha_enabled = false;
232 	u32 mixer_op_mode = 0;
233 	u32 val;
234 #define blender(stage)	((stage) - STAGE0)
235 
236 	spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
237 
238 	/* ctl could be released already when we are shutting down: */
239 	/* XXX: Can this happen now? */
240 	if (!ctl)
241 		goto out;
242 
243 	/* Collect all plane information */
244 	drm_atomic_crtc_for_each_plane(plane, crtc) {
245 		enum mdp5_pipe right_pipe;
246 
247 		if (!plane->state->visible)
248 			continue;
249 
250 		pstate = to_mdp5_plane_state(plane->state);
251 		pstates[pstate->stage] = pstate;
252 		stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
253 		/*
254 		 * if we have a right mixer, stage the same pipe as we
255 		 * have on the left mixer
256 		 */
257 		if (r_mixer)
258 			r_stage[pstate->stage][PIPE_LEFT] =
259 						mdp5_plane_pipe(plane);
260 		/*
261 		 * if we have a right pipe (i.e, the plane comprises of 2
262 		 * hwpipes, then stage the right pipe on the right side of both
263 		 * the layer mixers
264 		 */
265 		right_pipe = mdp5_plane_right_pipe(plane);
266 		if (right_pipe) {
267 			stage[pstate->stage][PIPE_RIGHT] = right_pipe;
268 			r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
269 		}
270 
271 		plane_cnt++;
272 	}
273 
274 	if (!pstates[STAGE_BASE]) {
275 		ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
276 		DBG("Border Color is enabled");
277 	} else if (plane_cnt) {
278 		format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
279 
280 		if (format->alpha_enable)
281 			bg_alpha_enabled = true;
282 	}
283 
284 	/* The reset for blending */
285 	for (i = STAGE0; i <= STAGE_MAX; i++) {
286 		if (!pstates[i])
287 			continue;
288 
289 		format = to_mdp_format(
290 			msm_framebuffer_format(pstates[i]->base.fb));
291 		plane = pstates[i]->base.plane;
292 		blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
293 			MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
294 		fg_alpha = pstates[i]->base.alpha >> 8;
295 		bg_alpha = 0xFF - fg_alpha;
296 
297 		if (!format->alpha_enable && bg_alpha_enabled)
298 			mixer_op_mode = 0;
299 		else
300 			mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
301 
302 		DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
303 
304 		if (format->alpha_enable &&
305 		    pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
306 			blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
307 				MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
308 			if (fg_alpha != 0xff) {
309 				bg_alpha = fg_alpha;
310 				blend_op |=
311 					MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
312 					MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
313 			} else {
314 				blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
315 			}
316 		} else if (format->alpha_enable &&
317 			   pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
318 			blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
319 				MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
320 			if (fg_alpha != 0xff) {
321 				bg_alpha = fg_alpha;
322 				blend_op |=
323 				       MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
324 				       MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
325 				       MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
326 				       MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
327 			} else {
328 				blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
329 			}
330 		}
331 
332 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
333 				blender(i)), blend_op);
334 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
335 				blender(i)), fg_alpha);
336 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
337 				blender(i)), bg_alpha);
338 		if (r_mixer) {
339 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,
340 					blender(i)), blend_op);
341 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,
342 					blender(i)), fg_alpha);
343 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,
344 					blender(i)), bg_alpha);
345 		}
346 	}
347 
348 	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
349 	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
350 		   val | mixer_op_mode);
351 	if (r_mixer) {
352 		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
353 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),
354 			   val | mixer_op_mode);
355 	}
356 
357 	mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,
358 		       ctl_blend_flags);
359 out:
360 	spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
361 }
362 
363 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
364 {
365 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
366 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
367 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
368 	struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
369 	struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;
370 	uint32_t lm = mixer->lm;
371 	u32 mixer_width, val;
372 	unsigned long flags;
373 	struct drm_display_mode *mode;
374 
375 	if (WARN_ON(!crtc->state))
376 		return;
377 
378 	mode = &crtc->state->adjusted_mode;
379 
380 	DBG("%s: set mode: " DRM_MODE_FMT, crtc->name, DRM_MODE_ARG(mode));
381 
382 	mixer_width = mode->hdisplay;
383 	if (r_mixer)
384 		mixer_width /= 2;
385 
386 	spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
387 	mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
388 			MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
389 			MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
390 
391 	/* Assign mixer to LEFT side in source split mode */
392 	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
393 	val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
394 	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
395 
396 	if (r_mixer) {
397 		u32 r_lm = r_mixer->lm;
398 
399 		mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),
400 			   MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
401 			   MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
402 
403 		/* Assign mixer to RIGHT side in source split mode */
404 		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
405 		val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
406 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);
407 	}
408 
409 	spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
410 }
411 
412 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
413 {
414 	struct drm_device *dev = crtc->dev;
415 	struct drm_encoder *encoder;
416 
417 	drm_for_each_encoder(encoder, dev)
418 		if (encoder->crtc == crtc)
419 			return encoder;
420 
421 	return NULL;
422 }
423 
424 static bool mdp5_crtc_get_scanout_position(struct drm_crtc *crtc,
425 					   bool in_vblank_irq,
426 					   int *vpos, int *hpos,
427 					   ktime_t *stime, ktime_t *etime,
428 					   const struct drm_display_mode *mode)
429 {
430 	unsigned int pipe = crtc->index;
431 	struct drm_encoder *encoder;
432 	int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
433 
434 
435 	encoder = get_encoder_from_crtc(crtc);
436 	if (!encoder) {
437 		DRM_ERROR("no encoder found for crtc %d\n", pipe);
438 		return false;
439 	}
440 
441 	vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
442 	vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
443 
444 	/*
445 	 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
446 	 * the end of VFP. Translate the porch values relative to the line
447 	 * counter positions.
448 	 */
449 
450 	vactive_start = vsw + vbp + 1;
451 
452 	vactive_end = vactive_start + mode->crtc_vdisplay;
453 
454 	/* last scan line before VSYNC */
455 	vfp_end = mode->crtc_vtotal;
456 
457 	if (stime)
458 		*stime = ktime_get();
459 
460 	line = mdp5_encoder_get_linecount(encoder);
461 
462 	if (line < vactive_start)
463 		line -= vactive_start;
464 	else if (line > vactive_end)
465 		line = line - vfp_end - vactive_start;
466 	else
467 		line -= vactive_start;
468 
469 	*vpos = line;
470 	*hpos = 0;
471 
472 	if (etime)
473 		*etime = ktime_get();
474 
475 	return true;
476 }
477 
478 static u32 mdp5_crtc_get_vblank_counter(struct drm_crtc *crtc)
479 {
480 	struct drm_encoder *encoder;
481 
482 	encoder = get_encoder_from_crtc(crtc);
483 	if (!encoder)
484 		return 0;
485 
486 	return mdp5_encoder_get_framecount(encoder);
487 }
488 
489 static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
490 				     struct drm_atomic_state *state)
491 {
492 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
493 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
494 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
495 	struct device *dev = &mdp5_kms->pdev->dev;
496 	unsigned long flags;
497 
498 	DBG("%s", crtc->name);
499 
500 	if (WARN_ON(!mdp5_crtc->enabled))
501 		return;
502 
503 	/* Disable/save vblank irq handling before power is disabled */
504 	drm_crtc_vblank_off(crtc);
505 
506 	if (mdp5_cstate->cmd_mode)
507 		mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
508 
509 	mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
510 	pm_runtime_put_sync(dev);
511 
512 	if (crtc->state->event && !crtc->state->active) {
513 		WARN_ON(mdp5_crtc->event);
514 		spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags);
515 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
516 		crtc->state->event = NULL;
517 		spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags);
518 	}
519 
520 	mdp5_crtc->enabled = false;
521 }
522 
523 static void mdp5_crtc_vblank_on(struct drm_crtc *crtc)
524 {
525 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
526 	struct mdp5_interface *intf = mdp5_cstate->pipeline.intf;
527 	u32 count;
528 
529 	count = intf->mode == MDP5_INTF_DSI_MODE_COMMAND ? 0 : 0xffffffff;
530 	drm_crtc_set_max_vblank_count(crtc, count);
531 
532 	drm_crtc_vblank_on(crtc);
533 }
534 
535 static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,
536 				    struct drm_atomic_state *state)
537 {
538 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
539 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
540 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
541 	struct device *dev = &mdp5_kms->pdev->dev;
542 
543 	DBG("%s", crtc->name);
544 
545 	if (WARN_ON(mdp5_crtc->enabled))
546 		return;
547 
548 	pm_runtime_get_sync(dev);
549 
550 	if (mdp5_crtc->lm_cursor_enabled) {
551 		/*
552 		 * Restore LM cursor state, as it might have been lost
553 		 * with suspend:
554 		 */
555 		if (mdp5_crtc->cursor.iova) {
556 			unsigned long flags;
557 
558 			spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
559 			mdp5_crtc_restore_cursor(crtc);
560 			spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
561 
562 			mdp5_ctl_set_cursor(mdp5_cstate->ctl,
563 					    &mdp5_cstate->pipeline, 0, true);
564 		} else {
565 			mdp5_ctl_set_cursor(mdp5_cstate->ctl,
566 					    &mdp5_cstate->pipeline, 0, false);
567 		}
568 	}
569 
570 	/* Restore vblank irq handling after power is enabled */
571 	mdp5_crtc_vblank_on(crtc);
572 
573 	mdp5_crtc_mode_set_nofb(crtc);
574 
575 	mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
576 
577 	if (mdp5_cstate->cmd_mode)
578 		mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
579 
580 	mdp5_crtc->enabled = true;
581 }
582 
583 static int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc,
584 				    struct drm_crtc_state *new_crtc_state,
585 				    bool need_right_mixer)
586 {
587 	struct mdp5_crtc_state *mdp5_cstate =
588 			to_mdp5_crtc_state(new_crtc_state);
589 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
590 	struct mdp5_interface *intf;
591 	bool new_mixer = false;
592 
593 	new_mixer = !pipeline->mixer;
594 
595 	if ((need_right_mixer && !pipeline->r_mixer) ||
596 	    (!need_right_mixer && pipeline->r_mixer))
597 		new_mixer = true;
598 
599 	if (new_mixer) {
600 		struct mdp5_hw_mixer *old_mixer = pipeline->mixer;
601 		struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer;
602 		u32 caps;
603 		int ret;
604 
605 		caps = MDP_LM_CAP_DISPLAY;
606 		if (need_right_mixer)
607 			caps |= MDP_LM_CAP_PAIR;
608 
609 		ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps,
610 					&pipeline->mixer, need_right_mixer ?
611 					&pipeline->r_mixer : NULL);
612 		if (ret)
613 			return ret;
614 
615 		mdp5_mixer_release(new_crtc_state->state, old_mixer);
616 		if (old_r_mixer) {
617 			mdp5_mixer_release(new_crtc_state->state, old_r_mixer);
618 			if (!need_right_mixer)
619 				pipeline->r_mixer = NULL;
620 		}
621 	}
622 
623 	/*
624 	 * these should have been already set up in the encoder's atomic
625 	 * check (called by drm_atomic_helper_check_modeset)
626 	 */
627 	intf = pipeline->intf;
628 
629 	mdp5_cstate->err_irqmask = intf2err(intf->num);
630 	mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf);
631 
632 	if ((intf->type == INTF_DSI) &&
633 	    (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
634 		mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer);
635 		mdp5_cstate->cmd_mode = true;
636 	} else {
637 		mdp5_cstate->pp_done_irqmask = 0;
638 		mdp5_cstate->cmd_mode = false;
639 	}
640 
641 	return 0;
642 }
643 
644 struct plane_state {
645 	struct drm_plane *plane;
646 	struct mdp5_plane_state *state;
647 };
648 
649 static int pstate_cmp(const void *a, const void *b)
650 {
651 	struct plane_state *pa = (struct plane_state *)a;
652 	struct plane_state *pb = (struct plane_state *)b;
653 	return pa->state->base.normalized_zpos - pb->state->base.normalized_zpos;
654 }
655 
656 /* is there a helper for this? */
657 static bool is_fullscreen(struct drm_crtc_state *cstate,
658 		struct drm_plane_state *pstate)
659 {
660 	return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
661 		((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
662 		((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
663 }
664 
665 static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc,
666 					struct drm_crtc_state *new_crtc_state,
667 					struct drm_plane_state *bpstate)
668 {
669 	struct mdp5_crtc_state *mdp5_cstate =
670 			to_mdp5_crtc_state(new_crtc_state);
671 
672 	/*
673 	 * if we're in source split mode, it's mandatory to have
674 	 * border out on the base stage
675 	 */
676 	if (mdp5_cstate->pipeline.r_mixer)
677 		return STAGE0;
678 
679 	/* if the bottom-most layer is not fullscreen, we need to use
680 	 * it for solid-color:
681 	 */
682 	if (!is_fullscreen(new_crtc_state, bpstate))
683 		return STAGE0;
684 
685 	return STAGE_BASE;
686 }
687 
688 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
689 		struct drm_atomic_state *state)
690 {
691 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
692 									  crtc);
693 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);
694 	struct mdp5_interface *intf = mdp5_cstate->pipeline.intf;
695 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
696 	struct drm_plane *plane;
697 	struct drm_device *dev = crtc->dev;
698 	struct plane_state pstates[STAGE_MAX + 1];
699 	const struct mdp5_cfg_hw *hw_cfg;
700 	const struct drm_plane_state *pstate;
701 	const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
702 	bool cursor_plane = false;
703 	bool need_right_mixer = false;
704 	int cnt = 0, i;
705 	int ret;
706 	enum mdp_mixer_stage_id start;
707 
708 	DBG("%s: check", crtc->name);
709 
710 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
711 		struct mdp5_plane_state *mdp5_pstate =
712 				to_mdp5_plane_state(pstate);
713 
714 		if (!pstate->visible)
715 			continue;
716 
717 		pstates[cnt].plane = plane;
718 		pstates[cnt].state = to_mdp5_plane_state(pstate);
719 
720 		mdp5_pstate->needs_dirtyfb =
721 			intf->mode == MDP5_INTF_DSI_MODE_COMMAND;
722 
723 		/*
724 		 * if any plane on this crtc uses 2 hwpipes, then we need
725 		 * the crtc to have a right hwmixer.
726 		 */
727 		if (pstates[cnt].state->r_hwpipe)
728 			need_right_mixer = true;
729 		cnt++;
730 
731 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
732 			cursor_plane = true;
733 	}
734 
735 	/* bail out early if there aren't any planes */
736 	if (!cnt)
737 		return 0;
738 
739 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
740 
741 	/*
742 	 * we need a right hwmixer if the mode's width is greater than a single
743 	 * LM's max width
744 	 */
745 	if (mode->hdisplay > hw_cfg->lm.max_width)
746 		need_right_mixer = true;
747 
748 	ret = mdp5_crtc_setup_pipeline(crtc, crtc_state, need_right_mixer);
749 	if (ret) {
750 		DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret);
751 		return ret;
752 	}
753 
754 	/* assign a stage based on sorted zpos property */
755 	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
756 
757 	/* trigger a warning if cursor isn't the highest zorder */
758 	WARN_ON(cursor_plane &&
759 		(pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));
760 
761 	start = get_start_stage(crtc, crtc_state, &pstates[0].state->base);
762 
763 	/* verify that there are not too many planes attached to crtc
764 	 * and that we don't have conflicting mixer stages:
765 	 */
766 	if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
767 		DRM_DEV_ERROR(dev->dev, "too many planes! cnt=%d, start stage=%d\n",
768 			cnt, start);
769 		return -EINVAL;
770 	}
771 
772 	for (i = 0; i < cnt; i++) {
773 		if (cursor_plane && (i == (cnt - 1)))
774 			pstates[i].state->stage = hw_cfg->lm.nb_stages;
775 		else
776 			pstates[i].state->stage = start + i;
777 		DBG("%s: assign pipe %s on stage=%d", crtc->name,
778 				pstates[i].plane->name,
779 				pstates[i].state->stage);
780 	}
781 
782 	return 0;
783 }
784 
785 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
786 				   struct drm_atomic_state *state)
787 {
788 	DBG("%s: begin", crtc->name);
789 }
790 
791 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
792 				   struct drm_atomic_state *state)
793 {
794 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
795 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
796 	struct drm_device *dev = crtc->dev;
797 	unsigned long flags;
798 
799 	DBG("%s: event: %p", crtc->name, crtc->state->event);
800 
801 	WARN_ON(mdp5_crtc->event);
802 
803 	spin_lock_irqsave(&dev->event_lock, flags);
804 	mdp5_crtc->event = crtc->state->event;
805 	crtc->state->event = NULL;
806 	spin_unlock_irqrestore(&dev->event_lock, flags);
807 
808 	/*
809 	 * If no CTL has been allocated in mdp5_crtc_atomic_check(),
810 	 * it means we are trying to flush a CRTC whose state is disabled:
811 	 * nothing else needs to be done.
812 	 */
813 	/* XXX: Can this happen now ? */
814 	if (unlikely(!mdp5_cstate->ctl))
815 		return;
816 
817 	blend_setup(crtc);
818 
819 	/* PP_DONE irq is only used by command mode for now.
820 	 * It is better to request pending before FLUSH and START trigger
821 	 * to make sure no pp_done irq missed.
822 	 * This is safe because no pp_done will happen before SW trigger
823 	 * in command mode.
824 	 */
825 	if (mdp5_cstate->cmd_mode)
826 		request_pp_done_pending(crtc);
827 
828 	mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
829 
830 	/* XXX are we leaking out state here? */
831 	mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask;
832 	mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask;
833 	mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask;
834 
835 	request_pending(crtc, PENDING_FLIP);
836 }
837 
838 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
839 {
840 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
841 	uint32_t xres = crtc->mode.hdisplay;
842 	uint32_t yres = crtc->mode.vdisplay;
843 
844 	/*
845 	 * Cursor Region Of Interest (ROI) is a plane read from cursor
846 	 * buffer to render. The ROI region is determined by the visibility of
847 	 * the cursor point. In the default Cursor image the cursor point will
848 	 * be at the top left of the cursor image.
849 	 *
850 	 * Without rotation:
851 	 * If the cursor point reaches the right (xres - x < cursor.width) or
852 	 * bottom (yres - y < cursor.height) boundary of the screen, then ROI
853 	 * width and ROI height need to be evaluated to crop the cursor image
854 	 * accordingly.
855 	 * (xres-x) will be new cursor width when x > (xres - cursor.width)
856 	 * (yres-y) will be new cursor height when y > (yres - cursor.height)
857 	 *
858 	 * With rotation:
859 	 * We get negative x and/or y coordinates.
860 	 * (cursor.width - abs(x)) will be new cursor width when x < 0
861 	 * (cursor.height - abs(y)) will be new cursor width when y < 0
862 	 */
863 	if (mdp5_crtc->cursor.x >= 0)
864 		*roi_w = min(mdp5_crtc->cursor.width, xres -
865 			mdp5_crtc->cursor.x);
866 	else
867 		*roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x);
868 	if (mdp5_crtc->cursor.y >= 0)
869 		*roi_h = min(mdp5_crtc->cursor.height, yres -
870 			mdp5_crtc->cursor.y);
871 	else
872 		*roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y);
873 }
874 
875 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
876 {
877 	const struct drm_format_info *info = drm_format_info(DRM_FORMAT_ARGB8888);
878 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
879 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
880 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
881 	const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
882 	uint32_t blendcfg, stride;
883 	uint32_t x, y, src_x, src_y, width, height;
884 	uint32_t roi_w, roi_h;
885 	int lm;
886 
887 	assert_spin_locked(&mdp5_crtc->cursor.lock);
888 
889 	lm = mdp5_cstate->pipeline.mixer->lm;
890 
891 	x = mdp5_crtc->cursor.x;
892 	y = mdp5_crtc->cursor.y;
893 	width = mdp5_crtc->cursor.width;
894 	height = mdp5_crtc->cursor.height;
895 
896 	stride = width * info->cpp[0];
897 
898 	get_roi(crtc, &roi_w, &roi_h);
899 
900 	/* If cusror buffer overlaps due to rotation on the
901 	 * upper or left screen border the pixel offset inside
902 	 * the cursor buffer of the ROI is the positive overlap
903 	 * distance.
904 	 */
905 	if (mdp5_crtc->cursor.x < 0) {
906 		src_x = abs(mdp5_crtc->cursor.x);
907 		x = 0;
908 	} else {
909 		src_x = 0;
910 	}
911 	if (mdp5_crtc->cursor.y < 0) {
912 		src_y = abs(mdp5_crtc->cursor.y);
913 		y = 0;
914 	} else {
915 		src_y = 0;
916 	}
917 	DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d",
918 		crtc->name, x, y, roi_w, roi_h, src_x, src_y);
919 
920 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
921 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
922 			MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
923 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
924 			MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
925 			MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
926 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
927 			MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
928 			MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
929 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
930 			MDP5_LM_CURSOR_START_XY_Y_START(y) |
931 			MDP5_LM_CURSOR_START_XY_X_START(x));
932 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),
933 			MDP5_LM_CURSOR_XY_SRC_Y(src_y) |
934 			MDP5_LM_CURSOR_XY_SRC_X(src_x));
935 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
936 			mdp5_crtc->cursor.iova);
937 
938 	blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
939 	blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
940 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
941 }
942 
943 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
944 		struct drm_file *file, uint32_t handle,
945 		uint32_t width, uint32_t height)
946 {
947 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
948 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
949 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
950 	struct drm_device *dev = crtc->dev;
951 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
952 	struct platform_device *pdev = mdp5_kms->pdev;
953 	struct msm_kms *kms = &mdp5_kms->base.base;
954 	struct drm_gem_object *cursor_bo, *old_bo = NULL;
955 	struct mdp5_ctl *ctl;
956 	int ret;
957 	uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
958 	bool cursor_enable = true;
959 	unsigned long flags;
960 
961 	if (!mdp5_crtc->lm_cursor_enabled) {
962 		dev_warn(dev->dev,
963 			 "cursor_set is deprecated with cursor planes\n");
964 		return -EINVAL;
965 	}
966 
967 	if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
968 		DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height);
969 		return -EINVAL;
970 	}
971 
972 	ctl = mdp5_cstate->ctl;
973 	if (!ctl)
974 		return -EINVAL;
975 
976 	/* don't support LM cursors when we have source split enabled */
977 	if (mdp5_cstate->pipeline.r_mixer)
978 		return -EINVAL;
979 
980 	if (!handle) {
981 		DBG("Cursor off");
982 		cursor_enable = false;
983 		mdp5_crtc->cursor.iova = 0;
984 		pm_runtime_get_sync(&pdev->dev);
985 		goto set_cursor;
986 	}
987 
988 	cursor_bo = drm_gem_object_lookup(file, handle);
989 	if (!cursor_bo)
990 		return -ENOENT;
991 
992 	ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace,
993 			&mdp5_crtc->cursor.iova);
994 	if (ret)
995 		return -EINVAL;
996 
997 	pm_runtime_get_sync(&pdev->dev);
998 
999 	spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
1000 	old_bo = mdp5_crtc->cursor.scanout_bo;
1001 
1002 	mdp5_crtc->cursor.scanout_bo = cursor_bo;
1003 	mdp5_crtc->cursor.width = width;
1004 	mdp5_crtc->cursor.height = height;
1005 
1006 	mdp5_crtc_restore_cursor(crtc);
1007 
1008 	spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
1009 
1010 set_cursor:
1011 	ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable);
1012 	if (ret) {
1013 		DRM_DEV_ERROR(dev->dev, "failed to %sable cursor: %d\n",
1014 				cursor_enable ? "en" : "dis", ret);
1015 		goto end;
1016 	}
1017 
1018 	crtc_flush(crtc, flush_mask);
1019 
1020 end:
1021 	pm_runtime_put_sync(&pdev->dev);
1022 	if (old_bo) {
1023 		drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
1024 		/* enable vblank to complete cursor work: */
1025 		request_pending(crtc, PENDING_CURSOR);
1026 	}
1027 	return ret;
1028 }
1029 
1030 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1031 {
1032 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
1033 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1034 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1035 	uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
1036 	struct drm_device *dev = crtc->dev;
1037 	uint32_t roi_w;
1038 	uint32_t roi_h;
1039 	unsigned long flags;
1040 
1041 	if (!mdp5_crtc->lm_cursor_enabled) {
1042 		dev_warn(dev->dev,
1043 			 "cursor_move is deprecated with cursor planes\n");
1044 		return -EINVAL;
1045 	}
1046 
1047 	/* don't support LM cursors when we have source split enabled */
1048 	if (mdp5_cstate->pipeline.r_mixer)
1049 		return -EINVAL;
1050 
1051 	/* In case the CRTC is disabled, just drop the cursor update */
1052 	if (unlikely(!crtc->state->enable))
1053 		return 0;
1054 
1055 	/* accept negative x/y coordinates up to maximum cursor overlap */
1056 	mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width);
1057 	mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height);
1058 
1059 	get_roi(crtc, &roi_w, &roi_h);
1060 
1061 	pm_runtime_get_sync(&mdp5_kms->pdev->dev);
1062 
1063 	spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
1064 	mdp5_crtc_restore_cursor(crtc);
1065 	spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
1066 
1067 	crtc_flush(crtc, flush_mask);
1068 
1069 	pm_runtime_put_sync(&mdp5_kms->pdev->dev);
1070 
1071 	return 0;
1072 }
1073 
1074 static void
1075 mdp5_crtc_atomic_print_state(struct drm_printer *p,
1076 			     const struct drm_crtc_state *state)
1077 {
1078 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1079 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
1080 	struct mdp5_kms *mdp5_kms = get_kms(state->crtc);
1081 
1082 	if (WARN_ON(!pipeline))
1083 		return;
1084 
1085 	if (mdp5_cstate->ctl)
1086 		drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl));
1087 
1088 	drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ?
1089 			pipeline->mixer->name : "(null)");
1090 
1091 	if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
1092 		drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ?
1093 			   pipeline->r_mixer->name : "(null)");
1094 
1095 	drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode);
1096 }
1097 
1098 static struct drm_crtc_state *
1099 mdp5_crtc_duplicate_state(struct drm_crtc *crtc)
1100 {
1101 	struct mdp5_crtc_state *mdp5_cstate;
1102 
1103 	if (WARN_ON(!crtc->state))
1104 		return NULL;
1105 
1106 	mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state),
1107 			      sizeof(*mdp5_cstate), GFP_KERNEL);
1108 	if (!mdp5_cstate)
1109 		return NULL;
1110 
1111 	__drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base);
1112 
1113 	return &mdp5_cstate->base;
1114 }
1115 
1116 static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state)
1117 {
1118 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1119 
1120 	__drm_atomic_helper_crtc_destroy_state(state);
1121 
1122 	kfree(mdp5_cstate);
1123 }
1124 
1125 static void mdp5_crtc_reset(struct drm_crtc *crtc)
1126 {
1127 	struct mdp5_crtc_state *mdp5_cstate =
1128 		kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
1129 
1130 	if (crtc->state)
1131 		mdp5_crtc_destroy_state(crtc, crtc->state);
1132 
1133 	__drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base);
1134 }
1135 
1136 static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {
1137 	.set_config = drm_atomic_helper_set_config,
1138 	.destroy = mdp5_crtc_destroy,
1139 	.page_flip = drm_atomic_helper_page_flip,
1140 	.reset = mdp5_crtc_reset,
1141 	.atomic_duplicate_state = mdp5_crtc_duplicate_state,
1142 	.atomic_destroy_state = mdp5_crtc_destroy_state,
1143 	.atomic_print_state = mdp5_crtc_atomic_print_state,
1144 	.get_vblank_counter = mdp5_crtc_get_vblank_counter,
1145 	.enable_vblank  = msm_crtc_enable_vblank,
1146 	.disable_vblank = msm_crtc_disable_vblank,
1147 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1148 };
1149 
1150 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
1151 	.set_config = drm_atomic_helper_set_config,
1152 	.destroy = mdp5_crtc_destroy,
1153 	.page_flip = drm_atomic_helper_page_flip,
1154 	.reset = mdp5_crtc_reset,
1155 	.atomic_duplicate_state = mdp5_crtc_duplicate_state,
1156 	.atomic_destroy_state = mdp5_crtc_destroy_state,
1157 	.cursor_set = mdp5_crtc_cursor_set,
1158 	.cursor_move = mdp5_crtc_cursor_move,
1159 	.atomic_print_state = mdp5_crtc_atomic_print_state,
1160 	.get_vblank_counter = mdp5_crtc_get_vblank_counter,
1161 	.enable_vblank  = msm_crtc_enable_vblank,
1162 	.disable_vblank = msm_crtc_disable_vblank,
1163 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1164 };
1165 
1166 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
1167 	.mode_set_nofb = mdp5_crtc_mode_set_nofb,
1168 	.atomic_check = mdp5_crtc_atomic_check,
1169 	.atomic_begin = mdp5_crtc_atomic_begin,
1170 	.atomic_flush = mdp5_crtc_atomic_flush,
1171 	.atomic_enable = mdp5_crtc_atomic_enable,
1172 	.atomic_disable = mdp5_crtc_atomic_disable,
1173 	.get_scanout_position = mdp5_crtc_get_scanout_position,
1174 };
1175 
1176 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
1177 {
1178 	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
1179 	struct drm_crtc *crtc = &mdp5_crtc->base;
1180 	struct msm_drm_private *priv = crtc->dev->dev_private;
1181 	unsigned pending;
1182 
1183 	mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
1184 
1185 	pending = atomic_xchg(&mdp5_crtc->pending, 0);
1186 
1187 	if (pending & PENDING_FLIP) {
1188 		complete_flip(crtc, NULL);
1189 	}
1190 
1191 	if (pending & PENDING_CURSOR)
1192 		drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
1193 }
1194 
1195 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
1196 {
1197 	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
1198 
1199 	DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus);
1200 }
1201 
1202 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
1203 {
1204 	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
1205 								pp_done);
1206 
1207 	complete_all(&mdp5_crtc->pp_completion);
1208 }
1209 
1210 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
1211 {
1212 	struct drm_device *dev = crtc->dev;
1213 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1214 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1215 	int ret;
1216 
1217 	ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
1218 						msecs_to_jiffies(50));
1219 	if (ret == 0)
1220 		dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
1221 				     mdp5_cstate->pipeline.mixer->lm);
1222 }
1223 
1224 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
1225 {
1226 	struct drm_device *dev = crtc->dev;
1227 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1228 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1229 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
1230 	int ret;
1231 
1232 	/* Should not call this function if crtc is disabled. */
1233 	if (!ctl)
1234 		return;
1235 
1236 	ret = drm_crtc_vblank_get(crtc);
1237 	if (ret)
1238 		return;
1239 
1240 	ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
1241 		((mdp5_ctl_get_commit_status(ctl) &
1242 		mdp5_crtc->flushed_mask) == 0),
1243 		msecs_to_jiffies(50));
1244 	if (ret <= 0)
1245 		dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
1246 
1247 	mdp5_crtc->flushed_mask = 0;
1248 
1249 	drm_crtc_vblank_put(crtc);
1250 }
1251 
1252 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
1253 {
1254 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1255 	return mdp5_crtc->vblank.irqmask;
1256 }
1257 
1258 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc)
1259 {
1260 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1261 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
1262 
1263 	/* should this be done elsewhere ? */
1264 	mdp_irq_update(&mdp5_kms->base);
1265 
1266 	mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
1267 }
1268 
1269 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
1270 {
1271 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1272 
1273 	return mdp5_cstate->ctl;
1274 }
1275 
1276 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc)
1277 {
1278 	struct mdp5_crtc_state *mdp5_cstate;
1279 
1280 	if (WARN_ON(!crtc))
1281 		return ERR_PTR(-EINVAL);
1282 
1283 	mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1284 
1285 	return WARN_ON(!mdp5_cstate->pipeline.mixer) ?
1286 		ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
1287 }
1288 
1289 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)
1290 {
1291 	struct mdp5_crtc_state *mdp5_cstate;
1292 
1293 	if (WARN_ON(!crtc))
1294 		return ERR_PTR(-EINVAL);
1295 
1296 	mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1297 
1298 	return &mdp5_cstate->pipeline;
1299 }
1300 
1301 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
1302 {
1303 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1304 
1305 	if (mdp5_cstate->cmd_mode)
1306 		mdp5_crtc_wait_for_pp_done(crtc);
1307 	else
1308 		mdp5_crtc_wait_for_flush_done(crtc);
1309 }
1310 
1311 /* initialize crtc */
1312 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
1313 				struct drm_plane *plane,
1314 				struct drm_plane *cursor_plane, int id)
1315 {
1316 	struct drm_crtc *crtc = NULL;
1317 	struct mdp5_crtc *mdp5_crtc;
1318 
1319 	mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
1320 	if (!mdp5_crtc)
1321 		return ERR_PTR(-ENOMEM);
1322 
1323 	crtc = &mdp5_crtc->base;
1324 
1325 	mdp5_crtc->id = id;
1326 
1327 	spin_lock_init(&mdp5_crtc->lm_lock);
1328 	spin_lock_init(&mdp5_crtc->cursor.lock);
1329 	init_completion(&mdp5_crtc->pp_completion);
1330 
1331 	mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
1332 	mdp5_crtc->err.irq = mdp5_crtc_err_irq;
1333 	mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
1334 
1335 	mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true;
1336 
1337 	drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane,
1338 				  cursor_plane ?
1339 				  &mdp5_crtc_no_lm_cursor_funcs :
1340 				  &mdp5_crtc_funcs, NULL);
1341 
1342 	drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
1343 			"unref cursor", unref_cursor_worker);
1344 
1345 	drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
1346 
1347 	return crtc;
1348 }
1349