1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #include <linux/sort.h>
9 
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_blend.h>
12 #include <drm/drm_mode.h>
13 #include <drm/drm_crtc.h>
14 #include <drm/drm_flip_work.h>
15 #include <drm/drm_fourcc.h>
16 #include <drm/drm_probe_helper.h>
17 #include <drm/drm_vblank.h>
18 
19 #include "mdp5_kms.h"
20 #include "msm_gem.h"
21 
22 #define CURSOR_WIDTH	64
23 #define CURSOR_HEIGHT	64
24 
25 struct mdp5_crtc {
26 	struct drm_crtc base;
27 	int id;
28 	bool enabled;
29 
30 	spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
31 
32 	/* if there is a pending flip, these will be non-null: */
33 	struct drm_pending_vblank_event *event;
34 
35 	/* Bits have been flushed at the last commit,
36 	 * used to decide if a vsync has happened since last commit.
37 	 */
38 	u32 flushed_mask;
39 
40 #define PENDING_CURSOR 0x1
41 #define PENDING_FLIP   0x2
42 	atomic_t pending;
43 
44 	/* for unref'ing cursor bo's after scanout completes: */
45 	struct drm_flip_work unref_cursor_work;
46 
47 	struct mdp_irq vblank;
48 	struct mdp_irq err;
49 	struct mdp_irq pp_done;
50 
51 	struct completion pp_completion;
52 
53 	bool lm_cursor_enabled;
54 
55 	struct {
56 		/* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
57 		spinlock_t lock;
58 
59 		/* current cursor being scanned out: */
60 		struct drm_gem_object *scanout_bo;
61 		uint64_t iova;
62 		uint32_t width, height;
63 		int x, y;
64 	} cursor;
65 };
66 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
67 
68 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc);
69 
70 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
71 {
72 	struct msm_drm_private *priv = crtc->dev->dev_private;
73 	return to_mdp5_kms(to_mdp_kms(priv->kms));
74 }
75 
76 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
77 {
78 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
79 
80 	atomic_or(pending, &mdp5_crtc->pending);
81 	mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
82 }
83 
84 static void request_pp_done_pending(struct drm_crtc *crtc)
85 {
86 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
87 	reinit_completion(&mdp5_crtc->pp_completion);
88 }
89 
90 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
91 {
92 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
93 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
94 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
95 	bool start = !mdp5_cstate->defer_start;
96 
97 	mdp5_cstate->defer_start = false;
98 
99 	DBG("%s: flush=%08x", crtc->name, flush_mask);
100 
101 	return mdp5_ctl_commit(ctl, pipeline, flush_mask, start);
102 }
103 
104 /*
105  * flush updates, to make sure hw is updated to new scanout fb,
106  * so that we can safely queue unref to current fb (ie. next
107  * vblank we know hw is done w/ previous scanout_fb).
108  */
109 static u32 crtc_flush_all(struct drm_crtc *crtc)
110 {
111 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
112 	struct mdp5_hw_mixer *mixer, *r_mixer;
113 	struct drm_plane *plane;
114 	uint32_t flush_mask = 0;
115 
116 	/* this should not happen: */
117 	if (WARN_ON(!mdp5_cstate->ctl))
118 		return 0;
119 
120 	drm_atomic_crtc_for_each_plane(plane, crtc) {
121 		if (!plane->state->visible)
122 			continue;
123 		flush_mask |= mdp5_plane_get_flush(plane);
124 	}
125 
126 	mixer = mdp5_cstate->pipeline.mixer;
127 	flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm);
128 
129 	r_mixer = mdp5_cstate->pipeline.r_mixer;
130 	if (r_mixer)
131 		flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm);
132 
133 	return crtc_flush(crtc, flush_mask);
134 }
135 
136 /* if file!=NULL, this is preclose potential cancel-flip path */
137 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
138 {
139 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
140 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
141 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
142 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
143 	struct drm_device *dev = crtc->dev;
144 	struct drm_pending_vblank_event *event;
145 	unsigned long flags;
146 
147 	spin_lock_irqsave(&dev->event_lock, flags);
148 	event = mdp5_crtc->event;
149 	if (event) {
150 		mdp5_crtc->event = NULL;
151 		DBG("%s: send event: %p", crtc->name, event);
152 		drm_crtc_send_vblank_event(crtc, event);
153 	}
154 	spin_unlock_irqrestore(&dev->event_lock, flags);
155 
156 	if (ctl && !crtc->state->enable) {
157 		/* set STAGE_UNUSED for all layers */
158 		mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0);
159 		/* XXX: What to do here? */
160 		/* mdp5_crtc->ctl = NULL; */
161 	}
162 }
163 
164 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
165 {
166 	struct mdp5_crtc *mdp5_crtc =
167 		container_of(work, struct mdp5_crtc, unref_cursor_work);
168 	struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
169 	struct msm_kms *kms = &mdp5_kms->base.base;
170 
171 	msm_gem_unpin_iova(val, kms->aspace);
172 	drm_gem_object_put(val);
173 }
174 
175 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
176 {
177 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
178 
179 	drm_crtc_cleanup(crtc);
180 	drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
181 
182 	kfree(mdp5_crtc);
183 }
184 
185 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage)
186 {
187 	switch (stage) {
188 	case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA;
189 	case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA;
190 	case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA;
191 	case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA;
192 	case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA;
193 	case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA;
194 	case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA;
195 	default:
196 		return 0;
197 	}
198 }
199 
200 /*
201  * left/right pipe offsets for the stage array used in blend_setup()
202  */
203 #define PIPE_LEFT	0
204 #define PIPE_RIGHT	1
205 
206 /*
207  * blend_setup() - blend all the planes of a CRTC
208  *
209  * If no base layer is available, border will be enabled as the base layer.
210  * Otherwise all layers will be blended based on their stage calculated
211  * in mdp5_crtc_atomic_check.
212  */
213 static void blend_setup(struct drm_crtc *crtc)
214 {
215 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
216 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
217 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
218 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
219 	struct drm_plane *plane;
220 	struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
221 	const struct mdp_format *format;
222 	struct mdp5_hw_mixer *mixer = pipeline->mixer;
223 	uint32_t lm = mixer->lm;
224 	struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
225 	uint32_t r_lm = r_mixer ? r_mixer->lm : 0;
226 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
227 	uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
228 	unsigned long flags;
229 	enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
230 	enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
231 	int i, plane_cnt = 0;
232 	bool bg_alpha_enabled = false;
233 	u32 mixer_op_mode = 0;
234 	u32 val;
235 #define blender(stage)	((stage) - STAGE0)
236 
237 	spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
238 
239 	/* ctl could be released already when we are shutting down: */
240 	/* XXX: Can this happen now? */
241 	if (!ctl)
242 		goto out;
243 
244 	/* Collect all plane information */
245 	drm_atomic_crtc_for_each_plane(plane, crtc) {
246 		enum mdp5_pipe right_pipe;
247 
248 		if (!plane->state->visible)
249 			continue;
250 
251 		pstate = to_mdp5_plane_state(plane->state);
252 		pstates[pstate->stage] = pstate;
253 		stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
254 		/*
255 		 * if we have a right mixer, stage the same pipe as we
256 		 * have on the left mixer
257 		 */
258 		if (r_mixer)
259 			r_stage[pstate->stage][PIPE_LEFT] =
260 						mdp5_plane_pipe(plane);
261 		/*
262 		 * if we have a right pipe (i.e, the plane comprises of 2
263 		 * hwpipes, then stage the right pipe on the right side of both
264 		 * the layer mixers
265 		 */
266 		right_pipe = mdp5_plane_right_pipe(plane);
267 		if (right_pipe) {
268 			stage[pstate->stage][PIPE_RIGHT] = right_pipe;
269 			r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
270 		}
271 
272 		plane_cnt++;
273 	}
274 
275 	if (!pstates[STAGE_BASE]) {
276 		ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
277 		DBG("Border Color is enabled");
278 	} else if (plane_cnt) {
279 		format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
280 
281 		if (format->alpha_enable)
282 			bg_alpha_enabled = true;
283 	}
284 
285 	/* The reset for blending */
286 	for (i = STAGE0; i <= STAGE_MAX; i++) {
287 		if (!pstates[i])
288 			continue;
289 
290 		format = to_mdp_format(
291 			msm_framebuffer_format(pstates[i]->base.fb));
292 		plane = pstates[i]->base.plane;
293 		blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
294 			MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
295 		fg_alpha = pstates[i]->base.alpha >> 8;
296 		bg_alpha = 0xFF - fg_alpha;
297 
298 		if (!format->alpha_enable && bg_alpha_enabled)
299 			mixer_op_mode = 0;
300 		else
301 			mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
302 
303 		DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
304 
305 		if (format->alpha_enable &&
306 		    pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
307 			blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
308 				MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
309 			if (fg_alpha != 0xff) {
310 				bg_alpha = fg_alpha;
311 				blend_op |=
312 					MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
313 					MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
314 			} else {
315 				blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
316 			}
317 		} else if (format->alpha_enable &&
318 			   pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
319 			blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
320 				MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
321 			if (fg_alpha != 0xff) {
322 				bg_alpha = fg_alpha;
323 				blend_op |=
324 				       MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
325 				       MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
326 				       MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
327 				       MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
328 			} else {
329 				blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
330 			}
331 		}
332 
333 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
334 				blender(i)), blend_op);
335 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
336 				blender(i)), fg_alpha);
337 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
338 				blender(i)), bg_alpha);
339 		if (r_mixer) {
340 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,
341 					blender(i)), blend_op);
342 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,
343 					blender(i)), fg_alpha);
344 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,
345 					blender(i)), bg_alpha);
346 		}
347 	}
348 
349 	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
350 	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
351 		   val | mixer_op_mode);
352 	if (r_mixer) {
353 		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
354 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),
355 			   val | mixer_op_mode);
356 	}
357 
358 	mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,
359 		       ctl_blend_flags);
360 out:
361 	spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
362 }
363 
364 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
365 {
366 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
367 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
368 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
369 	struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
370 	struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;
371 	uint32_t lm = mixer->lm;
372 	u32 mixer_width, val;
373 	unsigned long flags;
374 	struct drm_display_mode *mode;
375 
376 	if (WARN_ON(!crtc->state))
377 		return;
378 
379 	mode = &crtc->state->adjusted_mode;
380 
381 	DBG("%s: set mode: " DRM_MODE_FMT, crtc->name, DRM_MODE_ARG(mode));
382 
383 	mixer_width = mode->hdisplay;
384 	if (r_mixer)
385 		mixer_width /= 2;
386 
387 	spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
388 	mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
389 			MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
390 			MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
391 
392 	/* Assign mixer to LEFT side in source split mode */
393 	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
394 	val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
395 	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
396 
397 	if (r_mixer) {
398 		u32 r_lm = r_mixer->lm;
399 
400 		mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),
401 			   MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
402 			   MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
403 
404 		/* Assign mixer to RIGHT side in source split mode */
405 		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
406 		val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
407 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);
408 	}
409 
410 	spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
411 }
412 
413 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
414 {
415 	struct drm_device *dev = crtc->dev;
416 	struct drm_encoder *encoder;
417 
418 	drm_for_each_encoder(encoder, dev)
419 		if (encoder->crtc == crtc)
420 			return encoder;
421 
422 	return NULL;
423 }
424 
425 static bool mdp5_crtc_get_scanout_position(struct drm_crtc *crtc,
426 					   bool in_vblank_irq,
427 					   int *vpos, int *hpos,
428 					   ktime_t *stime, ktime_t *etime,
429 					   const struct drm_display_mode *mode)
430 {
431 	unsigned int pipe = crtc->index;
432 	struct drm_encoder *encoder;
433 	int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
434 
435 
436 	encoder = get_encoder_from_crtc(crtc);
437 	if (!encoder) {
438 		DRM_ERROR("no encoder found for crtc %d\n", pipe);
439 		return false;
440 	}
441 
442 	vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
443 	vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
444 
445 	/*
446 	 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
447 	 * the end of VFP. Translate the porch values relative to the line
448 	 * counter positions.
449 	 */
450 
451 	vactive_start = vsw + vbp + 1;
452 
453 	vactive_end = vactive_start + mode->crtc_vdisplay;
454 
455 	/* last scan line before VSYNC */
456 	vfp_end = mode->crtc_vtotal;
457 
458 	if (stime)
459 		*stime = ktime_get();
460 
461 	line = mdp5_encoder_get_linecount(encoder);
462 
463 	if (line < vactive_start)
464 		line -= vactive_start;
465 	else if (line > vactive_end)
466 		line = line - vfp_end - vactive_start;
467 	else
468 		line -= vactive_start;
469 
470 	*vpos = line;
471 	*hpos = 0;
472 
473 	if (etime)
474 		*etime = ktime_get();
475 
476 	return true;
477 }
478 
479 static u32 mdp5_crtc_get_vblank_counter(struct drm_crtc *crtc)
480 {
481 	struct drm_encoder *encoder;
482 
483 	encoder = get_encoder_from_crtc(crtc);
484 	if (!encoder)
485 		return 0;
486 
487 	return mdp5_encoder_get_framecount(encoder);
488 }
489 
490 static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
491 				     struct drm_atomic_state *state)
492 {
493 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
494 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
495 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
496 	struct device *dev = &mdp5_kms->pdev->dev;
497 	unsigned long flags;
498 
499 	DBG("%s", crtc->name);
500 
501 	if (WARN_ON(!mdp5_crtc->enabled))
502 		return;
503 
504 	/* Disable/save vblank irq handling before power is disabled */
505 	drm_crtc_vblank_off(crtc);
506 
507 	if (mdp5_cstate->cmd_mode)
508 		mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
509 
510 	mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
511 	pm_runtime_put_sync(dev);
512 
513 	if (crtc->state->event && !crtc->state->active) {
514 		WARN_ON(mdp5_crtc->event);
515 		spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags);
516 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
517 		crtc->state->event = NULL;
518 		spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags);
519 	}
520 
521 	mdp5_crtc->enabled = false;
522 }
523 
524 static void mdp5_crtc_vblank_on(struct drm_crtc *crtc)
525 {
526 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
527 	struct mdp5_interface *intf = mdp5_cstate->pipeline.intf;
528 	u32 count;
529 
530 	count = intf->mode == MDP5_INTF_DSI_MODE_COMMAND ? 0 : 0xffffffff;
531 	drm_crtc_set_max_vblank_count(crtc, count);
532 
533 	drm_crtc_vblank_on(crtc);
534 }
535 
536 static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,
537 				    struct drm_atomic_state *state)
538 {
539 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
540 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
541 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
542 	struct device *dev = &mdp5_kms->pdev->dev;
543 
544 	DBG("%s", crtc->name);
545 
546 	if (WARN_ON(mdp5_crtc->enabled))
547 		return;
548 
549 	pm_runtime_get_sync(dev);
550 
551 	if (mdp5_crtc->lm_cursor_enabled) {
552 		/*
553 		 * Restore LM cursor state, as it might have been lost
554 		 * with suspend:
555 		 */
556 		if (mdp5_crtc->cursor.iova) {
557 			unsigned long flags;
558 
559 			spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
560 			mdp5_crtc_restore_cursor(crtc);
561 			spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
562 
563 			mdp5_ctl_set_cursor(mdp5_cstate->ctl,
564 					    &mdp5_cstate->pipeline, 0, true);
565 		} else {
566 			mdp5_ctl_set_cursor(mdp5_cstate->ctl,
567 					    &mdp5_cstate->pipeline, 0, false);
568 		}
569 	}
570 
571 	/* Restore vblank irq handling after power is enabled */
572 	mdp5_crtc_vblank_on(crtc);
573 
574 	mdp5_crtc_mode_set_nofb(crtc);
575 
576 	mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
577 
578 	if (mdp5_cstate->cmd_mode)
579 		mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
580 
581 	mdp5_crtc->enabled = true;
582 }
583 
584 static int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc,
585 				    struct drm_crtc_state *new_crtc_state,
586 				    bool need_right_mixer)
587 {
588 	struct mdp5_crtc_state *mdp5_cstate =
589 			to_mdp5_crtc_state(new_crtc_state);
590 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
591 	struct mdp5_interface *intf;
592 	bool new_mixer = false;
593 
594 	new_mixer = !pipeline->mixer;
595 
596 	if ((need_right_mixer && !pipeline->r_mixer) ||
597 	    (!need_right_mixer && pipeline->r_mixer))
598 		new_mixer = true;
599 
600 	if (new_mixer) {
601 		struct mdp5_hw_mixer *old_mixer = pipeline->mixer;
602 		struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer;
603 		u32 caps;
604 		int ret;
605 
606 		caps = MDP_LM_CAP_DISPLAY;
607 		if (need_right_mixer)
608 			caps |= MDP_LM_CAP_PAIR;
609 
610 		ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps,
611 					&pipeline->mixer, need_right_mixer ?
612 					&pipeline->r_mixer : NULL);
613 		if (ret)
614 			return ret;
615 
616 		ret = mdp5_mixer_release(new_crtc_state->state, old_mixer);
617 		if (ret)
618 			return ret;
619 
620 		if (old_r_mixer) {
621 			ret = mdp5_mixer_release(new_crtc_state->state, old_r_mixer);
622 			if (ret)
623 				return ret;
624 
625 			if (!need_right_mixer)
626 				pipeline->r_mixer = NULL;
627 		}
628 	}
629 
630 	/*
631 	 * these should have been already set up in the encoder's atomic
632 	 * check (called by drm_atomic_helper_check_modeset)
633 	 */
634 	intf = pipeline->intf;
635 
636 	mdp5_cstate->err_irqmask = intf2err(intf->num);
637 	mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf);
638 
639 	if ((intf->type == INTF_DSI) &&
640 	    (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
641 		mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer);
642 		mdp5_cstate->cmd_mode = true;
643 	} else {
644 		mdp5_cstate->pp_done_irqmask = 0;
645 		mdp5_cstate->cmd_mode = false;
646 	}
647 
648 	return 0;
649 }
650 
651 struct plane_state {
652 	struct drm_plane *plane;
653 	struct mdp5_plane_state *state;
654 };
655 
656 static int pstate_cmp(const void *a, const void *b)
657 {
658 	struct plane_state *pa = (struct plane_state *)a;
659 	struct plane_state *pb = (struct plane_state *)b;
660 	return pa->state->base.normalized_zpos - pb->state->base.normalized_zpos;
661 }
662 
663 /* is there a helper for this? */
664 static bool is_fullscreen(struct drm_crtc_state *cstate,
665 		struct drm_plane_state *pstate)
666 {
667 	return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
668 		((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
669 		((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
670 }
671 
672 static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc,
673 					struct drm_crtc_state *new_crtc_state,
674 					struct drm_plane_state *bpstate)
675 {
676 	struct mdp5_crtc_state *mdp5_cstate =
677 			to_mdp5_crtc_state(new_crtc_state);
678 
679 	/*
680 	 * if we're in source split mode, it's mandatory to have
681 	 * border out on the base stage
682 	 */
683 	if (mdp5_cstate->pipeline.r_mixer)
684 		return STAGE0;
685 
686 	/* if the bottom-most layer is not fullscreen, we need to use
687 	 * it for solid-color:
688 	 */
689 	if (!is_fullscreen(new_crtc_state, bpstate))
690 		return STAGE0;
691 
692 	return STAGE_BASE;
693 }
694 
695 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
696 		struct drm_atomic_state *state)
697 {
698 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
699 									  crtc);
700 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);
701 	struct mdp5_interface *intf = mdp5_cstate->pipeline.intf;
702 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
703 	struct drm_plane *plane;
704 	struct drm_device *dev = crtc->dev;
705 	struct plane_state pstates[STAGE_MAX + 1];
706 	const struct mdp5_cfg_hw *hw_cfg;
707 	const struct drm_plane_state *pstate;
708 	const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
709 	bool cursor_plane = false;
710 	bool need_right_mixer = false;
711 	int cnt = 0, i;
712 	int ret;
713 	enum mdp_mixer_stage_id start;
714 
715 	DBG("%s: check", crtc->name);
716 
717 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
718 		struct mdp5_plane_state *mdp5_pstate =
719 				to_mdp5_plane_state(pstate);
720 
721 		if (!pstate->visible)
722 			continue;
723 
724 		pstates[cnt].plane = plane;
725 		pstates[cnt].state = to_mdp5_plane_state(pstate);
726 
727 		mdp5_pstate->needs_dirtyfb =
728 			intf->mode == MDP5_INTF_DSI_MODE_COMMAND;
729 
730 		/*
731 		 * if any plane on this crtc uses 2 hwpipes, then we need
732 		 * the crtc to have a right hwmixer.
733 		 */
734 		if (pstates[cnt].state->r_hwpipe)
735 			need_right_mixer = true;
736 		cnt++;
737 
738 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
739 			cursor_plane = true;
740 	}
741 
742 	/* bail out early if there aren't any planes */
743 	if (!cnt)
744 		return 0;
745 
746 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
747 
748 	/*
749 	 * we need a right hwmixer if the mode's width is greater than a single
750 	 * LM's max width
751 	 */
752 	if (mode->hdisplay > hw_cfg->lm.max_width)
753 		need_right_mixer = true;
754 
755 	ret = mdp5_crtc_setup_pipeline(crtc, crtc_state, need_right_mixer);
756 	if (ret) {
757 		DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret);
758 		return ret;
759 	}
760 
761 	/* assign a stage based on sorted zpos property */
762 	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
763 
764 	/* trigger a warning if cursor isn't the highest zorder */
765 	WARN_ON(cursor_plane &&
766 		(pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));
767 
768 	start = get_start_stage(crtc, crtc_state, &pstates[0].state->base);
769 
770 	/* verify that there are not too many planes attached to crtc
771 	 * and that we don't have conflicting mixer stages:
772 	 */
773 	if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
774 		DRM_DEV_ERROR(dev->dev, "too many planes! cnt=%d, start stage=%d\n",
775 			cnt, start);
776 		return -EINVAL;
777 	}
778 
779 	for (i = 0; i < cnt; i++) {
780 		if (cursor_plane && (i == (cnt - 1)))
781 			pstates[i].state->stage = hw_cfg->lm.nb_stages;
782 		else
783 			pstates[i].state->stage = start + i;
784 		DBG("%s: assign pipe %s on stage=%d", crtc->name,
785 				pstates[i].plane->name,
786 				pstates[i].state->stage);
787 	}
788 
789 	return 0;
790 }
791 
792 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
793 				   struct drm_atomic_state *state)
794 {
795 	DBG("%s: begin", crtc->name);
796 }
797 
798 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
799 				   struct drm_atomic_state *state)
800 {
801 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
802 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
803 	struct drm_device *dev = crtc->dev;
804 	unsigned long flags;
805 
806 	DBG("%s: event: %p", crtc->name, crtc->state->event);
807 
808 	WARN_ON(mdp5_crtc->event);
809 
810 	spin_lock_irqsave(&dev->event_lock, flags);
811 	mdp5_crtc->event = crtc->state->event;
812 	crtc->state->event = NULL;
813 	spin_unlock_irqrestore(&dev->event_lock, flags);
814 
815 	/*
816 	 * If no CTL has been allocated in mdp5_crtc_atomic_check(),
817 	 * it means we are trying to flush a CRTC whose state is disabled:
818 	 * nothing else needs to be done.
819 	 */
820 	/* XXX: Can this happen now ? */
821 	if (unlikely(!mdp5_cstate->ctl))
822 		return;
823 
824 	blend_setup(crtc);
825 
826 	/* PP_DONE irq is only used by command mode for now.
827 	 * It is better to request pending before FLUSH and START trigger
828 	 * to make sure no pp_done irq missed.
829 	 * This is safe because no pp_done will happen before SW trigger
830 	 * in command mode.
831 	 */
832 	if (mdp5_cstate->cmd_mode)
833 		request_pp_done_pending(crtc);
834 
835 	mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
836 
837 	/* XXX are we leaking out state here? */
838 	mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask;
839 	mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask;
840 	mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask;
841 
842 	request_pending(crtc, PENDING_FLIP);
843 }
844 
845 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
846 {
847 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
848 	uint32_t xres = crtc->mode.hdisplay;
849 	uint32_t yres = crtc->mode.vdisplay;
850 
851 	/*
852 	 * Cursor Region Of Interest (ROI) is a plane read from cursor
853 	 * buffer to render. The ROI region is determined by the visibility of
854 	 * the cursor point. In the default Cursor image the cursor point will
855 	 * be at the top left of the cursor image.
856 	 *
857 	 * Without rotation:
858 	 * If the cursor point reaches the right (xres - x < cursor.width) or
859 	 * bottom (yres - y < cursor.height) boundary of the screen, then ROI
860 	 * width and ROI height need to be evaluated to crop the cursor image
861 	 * accordingly.
862 	 * (xres-x) will be new cursor width when x > (xres - cursor.width)
863 	 * (yres-y) will be new cursor height when y > (yres - cursor.height)
864 	 *
865 	 * With rotation:
866 	 * We get negative x and/or y coordinates.
867 	 * (cursor.width - abs(x)) will be new cursor width when x < 0
868 	 * (cursor.height - abs(y)) will be new cursor width when y < 0
869 	 */
870 	if (mdp5_crtc->cursor.x >= 0)
871 		*roi_w = min(mdp5_crtc->cursor.width, xres -
872 			mdp5_crtc->cursor.x);
873 	else
874 		*roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x);
875 	if (mdp5_crtc->cursor.y >= 0)
876 		*roi_h = min(mdp5_crtc->cursor.height, yres -
877 			mdp5_crtc->cursor.y);
878 	else
879 		*roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y);
880 }
881 
882 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
883 {
884 	const struct drm_format_info *info = drm_format_info(DRM_FORMAT_ARGB8888);
885 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
886 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
887 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
888 	const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
889 	uint32_t blendcfg, stride;
890 	uint32_t x, y, src_x, src_y, width, height;
891 	uint32_t roi_w, roi_h;
892 	int lm;
893 
894 	assert_spin_locked(&mdp5_crtc->cursor.lock);
895 
896 	lm = mdp5_cstate->pipeline.mixer->lm;
897 
898 	x = mdp5_crtc->cursor.x;
899 	y = mdp5_crtc->cursor.y;
900 	width = mdp5_crtc->cursor.width;
901 	height = mdp5_crtc->cursor.height;
902 
903 	stride = width * info->cpp[0];
904 
905 	get_roi(crtc, &roi_w, &roi_h);
906 
907 	/* If cusror buffer overlaps due to rotation on the
908 	 * upper or left screen border the pixel offset inside
909 	 * the cursor buffer of the ROI is the positive overlap
910 	 * distance.
911 	 */
912 	if (mdp5_crtc->cursor.x < 0) {
913 		src_x = abs(mdp5_crtc->cursor.x);
914 		x = 0;
915 	} else {
916 		src_x = 0;
917 	}
918 	if (mdp5_crtc->cursor.y < 0) {
919 		src_y = abs(mdp5_crtc->cursor.y);
920 		y = 0;
921 	} else {
922 		src_y = 0;
923 	}
924 	DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d",
925 		crtc->name, x, y, roi_w, roi_h, src_x, src_y);
926 
927 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
928 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
929 			MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
930 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
931 			MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
932 			MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
933 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
934 			MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
935 			MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
936 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
937 			MDP5_LM_CURSOR_START_XY_Y_START(y) |
938 			MDP5_LM_CURSOR_START_XY_X_START(x));
939 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),
940 			MDP5_LM_CURSOR_XY_SRC_Y(src_y) |
941 			MDP5_LM_CURSOR_XY_SRC_X(src_x));
942 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
943 			mdp5_crtc->cursor.iova);
944 
945 	blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
946 	blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
947 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
948 }
949 
950 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
951 		struct drm_file *file, uint32_t handle,
952 		uint32_t width, uint32_t height)
953 {
954 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
955 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
956 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
957 	struct drm_device *dev = crtc->dev;
958 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
959 	struct platform_device *pdev = mdp5_kms->pdev;
960 	struct msm_kms *kms = &mdp5_kms->base.base;
961 	struct drm_gem_object *cursor_bo, *old_bo = NULL;
962 	struct mdp5_ctl *ctl;
963 	int ret;
964 	uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
965 	bool cursor_enable = true;
966 	unsigned long flags;
967 
968 	if (!mdp5_crtc->lm_cursor_enabled) {
969 		dev_warn(dev->dev,
970 			 "cursor_set is deprecated with cursor planes\n");
971 		return -EINVAL;
972 	}
973 
974 	if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
975 		DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height);
976 		return -EINVAL;
977 	}
978 
979 	ctl = mdp5_cstate->ctl;
980 	if (!ctl)
981 		return -EINVAL;
982 
983 	/* don't support LM cursors when we have source split enabled */
984 	if (mdp5_cstate->pipeline.r_mixer)
985 		return -EINVAL;
986 
987 	if (!handle) {
988 		DBG("Cursor off");
989 		cursor_enable = false;
990 		mdp5_crtc->cursor.iova = 0;
991 		pm_runtime_get_sync(&pdev->dev);
992 		goto set_cursor;
993 	}
994 
995 	cursor_bo = drm_gem_object_lookup(file, handle);
996 	if (!cursor_bo)
997 		return -ENOENT;
998 
999 	ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace,
1000 			&mdp5_crtc->cursor.iova);
1001 	if (ret) {
1002 		drm_gem_object_put(cursor_bo);
1003 		return -EINVAL;
1004 	}
1005 
1006 	pm_runtime_get_sync(&pdev->dev);
1007 
1008 	spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
1009 	old_bo = mdp5_crtc->cursor.scanout_bo;
1010 
1011 	mdp5_crtc->cursor.scanout_bo = cursor_bo;
1012 	mdp5_crtc->cursor.width = width;
1013 	mdp5_crtc->cursor.height = height;
1014 
1015 	mdp5_crtc_restore_cursor(crtc);
1016 
1017 	spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
1018 
1019 set_cursor:
1020 	ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable);
1021 	if (ret) {
1022 		DRM_DEV_ERROR(dev->dev, "failed to %sable cursor: %d\n",
1023 				cursor_enable ? "en" : "dis", ret);
1024 		goto end;
1025 	}
1026 
1027 	crtc_flush(crtc, flush_mask);
1028 
1029 end:
1030 	pm_runtime_put_sync(&pdev->dev);
1031 	if (old_bo) {
1032 		drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
1033 		/* enable vblank to complete cursor work: */
1034 		request_pending(crtc, PENDING_CURSOR);
1035 	}
1036 	return ret;
1037 }
1038 
1039 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1040 {
1041 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
1042 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1043 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1044 	uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
1045 	struct drm_device *dev = crtc->dev;
1046 	uint32_t roi_w;
1047 	uint32_t roi_h;
1048 	unsigned long flags;
1049 
1050 	if (!mdp5_crtc->lm_cursor_enabled) {
1051 		dev_warn(dev->dev,
1052 			 "cursor_move is deprecated with cursor planes\n");
1053 		return -EINVAL;
1054 	}
1055 
1056 	/* don't support LM cursors when we have source split enabled */
1057 	if (mdp5_cstate->pipeline.r_mixer)
1058 		return -EINVAL;
1059 
1060 	/* In case the CRTC is disabled, just drop the cursor update */
1061 	if (unlikely(!crtc->state->enable))
1062 		return 0;
1063 
1064 	/* accept negative x/y coordinates up to maximum cursor overlap */
1065 	mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width);
1066 	mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height);
1067 
1068 	get_roi(crtc, &roi_w, &roi_h);
1069 
1070 	pm_runtime_get_sync(&mdp5_kms->pdev->dev);
1071 
1072 	spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
1073 	mdp5_crtc_restore_cursor(crtc);
1074 	spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
1075 
1076 	crtc_flush(crtc, flush_mask);
1077 
1078 	pm_runtime_put_sync(&mdp5_kms->pdev->dev);
1079 
1080 	return 0;
1081 }
1082 
1083 static void
1084 mdp5_crtc_atomic_print_state(struct drm_printer *p,
1085 			     const struct drm_crtc_state *state)
1086 {
1087 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1088 	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
1089 	struct mdp5_kms *mdp5_kms = get_kms(state->crtc);
1090 
1091 	if (WARN_ON(!pipeline))
1092 		return;
1093 
1094 	if (mdp5_cstate->ctl)
1095 		drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl));
1096 
1097 	drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ?
1098 			pipeline->mixer->name : "(null)");
1099 
1100 	if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
1101 		drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ?
1102 			   pipeline->r_mixer->name : "(null)");
1103 
1104 	drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode);
1105 }
1106 
1107 static struct drm_crtc_state *
1108 mdp5_crtc_duplicate_state(struct drm_crtc *crtc)
1109 {
1110 	struct mdp5_crtc_state *mdp5_cstate;
1111 
1112 	if (WARN_ON(!crtc->state))
1113 		return NULL;
1114 
1115 	mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state),
1116 			      sizeof(*mdp5_cstate), GFP_KERNEL);
1117 	if (!mdp5_cstate)
1118 		return NULL;
1119 
1120 	__drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base);
1121 
1122 	return &mdp5_cstate->base;
1123 }
1124 
1125 static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state)
1126 {
1127 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1128 
1129 	__drm_atomic_helper_crtc_destroy_state(state);
1130 
1131 	kfree(mdp5_cstate);
1132 }
1133 
1134 static void mdp5_crtc_reset(struct drm_crtc *crtc)
1135 {
1136 	struct mdp5_crtc_state *mdp5_cstate =
1137 		kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
1138 
1139 	if (crtc->state)
1140 		mdp5_crtc_destroy_state(crtc, crtc->state);
1141 
1142 	if (mdp5_cstate)
1143 		__drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base);
1144 	else
1145 		__drm_atomic_helper_crtc_reset(crtc, NULL);
1146 }
1147 
1148 static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {
1149 	.set_config = drm_atomic_helper_set_config,
1150 	.destroy = mdp5_crtc_destroy,
1151 	.page_flip = drm_atomic_helper_page_flip,
1152 	.reset = mdp5_crtc_reset,
1153 	.atomic_duplicate_state = mdp5_crtc_duplicate_state,
1154 	.atomic_destroy_state = mdp5_crtc_destroy_state,
1155 	.atomic_print_state = mdp5_crtc_atomic_print_state,
1156 	.get_vblank_counter = mdp5_crtc_get_vblank_counter,
1157 	.enable_vblank  = msm_crtc_enable_vblank,
1158 	.disable_vblank = msm_crtc_disable_vblank,
1159 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1160 };
1161 
1162 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
1163 	.set_config = drm_atomic_helper_set_config,
1164 	.destroy = mdp5_crtc_destroy,
1165 	.page_flip = drm_atomic_helper_page_flip,
1166 	.reset = mdp5_crtc_reset,
1167 	.atomic_duplicate_state = mdp5_crtc_duplicate_state,
1168 	.atomic_destroy_state = mdp5_crtc_destroy_state,
1169 	.cursor_set = mdp5_crtc_cursor_set,
1170 	.cursor_move = mdp5_crtc_cursor_move,
1171 	.atomic_print_state = mdp5_crtc_atomic_print_state,
1172 	.get_vblank_counter = mdp5_crtc_get_vblank_counter,
1173 	.enable_vblank  = msm_crtc_enable_vblank,
1174 	.disable_vblank = msm_crtc_disable_vblank,
1175 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1176 };
1177 
1178 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
1179 	.mode_set_nofb = mdp5_crtc_mode_set_nofb,
1180 	.atomic_check = mdp5_crtc_atomic_check,
1181 	.atomic_begin = mdp5_crtc_atomic_begin,
1182 	.atomic_flush = mdp5_crtc_atomic_flush,
1183 	.atomic_enable = mdp5_crtc_atomic_enable,
1184 	.atomic_disable = mdp5_crtc_atomic_disable,
1185 	.get_scanout_position = mdp5_crtc_get_scanout_position,
1186 };
1187 
1188 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
1189 {
1190 	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
1191 	struct drm_crtc *crtc = &mdp5_crtc->base;
1192 	struct msm_drm_private *priv = crtc->dev->dev_private;
1193 	unsigned pending;
1194 
1195 	mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
1196 
1197 	pending = atomic_xchg(&mdp5_crtc->pending, 0);
1198 
1199 	if (pending & PENDING_FLIP) {
1200 		complete_flip(crtc, NULL);
1201 	}
1202 
1203 	if (pending & PENDING_CURSOR)
1204 		drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
1205 }
1206 
1207 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
1208 {
1209 	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
1210 
1211 	DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus);
1212 }
1213 
1214 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
1215 {
1216 	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
1217 								pp_done);
1218 
1219 	complete_all(&mdp5_crtc->pp_completion);
1220 }
1221 
1222 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
1223 {
1224 	struct drm_device *dev = crtc->dev;
1225 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1226 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1227 	int ret;
1228 
1229 	ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
1230 						msecs_to_jiffies(50));
1231 	if (ret == 0)
1232 		dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
1233 				     mdp5_cstate->pipeline.mixer->lm);
1234 }
1235 
1236 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
1237 {
1238 	struct drm_device *dev = crtc->dev;
1239 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1240 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1241 	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
1242 	int ret;
1243 
1244 	/* Should not call this function if crtc is disabled. */
1245 	if (!ctl)
1246 		return;
1247 
1248 	ret = drm_crtc_vblank_get(crtc);
1249 	if (ret)
1250 		return;
1251 
1252 	ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
1253 		((mdp5_ctl_get_commit_status(ctl) &
1254 		mdp5_crtc->flushed_mask) == 0),
1255 		msecs_to_jiffies(50));
1256 	if (ret <= 0)
1257 		dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
1258 
1259 	mdp5_crtc->flushed_mask = 0;
1260 
1261 	drm_crtc_vblank_put(crtc);
1262 }
1263 
1264 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
1265 {
1266 	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1267 	return mdp5_crtc->vblank.irqmask;
1268 }
1269 
1270 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc)
1271 {
1272 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1273 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
1274 
1275 	/* should this be done elsewhere ? */
1276 	mdp_irq_update(&mdp5_kms->base);
1277 
1278 	mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
1279 }
1280 
1281 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
1282 {
1283 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1284 
1285 	return mdp5_cstate->ctl;
1286 }
1287 
1288 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc)
1289 {
1290 	struct mdp5_crtc_state *mdp5_cstate;
1291 
1292 	if (WARN_ON(!crtc))
1293 		return ERR_PTR(-EINVAL);
1294 
1295 	mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1296 
1297 	return WARN_ON(!mdp5_cstate->pipeline.mixer) ?
1298 		ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
1299 }
1300 
1301 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)
1302 {
1303 	struct mdp5_crtc_state *mdp5_cstate;
1304 
1305 	if (WARN_ON(!crtc))
1306 		return ERR_PTR(-EINVAL);
1307 
1308 	mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1309 
1310 	return &mdp5_cstate->pipeline;
1311 }
1312 
1313 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
1314 {
1315 	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1316 
1317 	if (mdp5_cstate->cmd_mode)
1318 		mdp5_crtc_wait_for_pp_done(crtc);
1319 	else
1320 		mdp5_crtc_wait_for_flush_done(crtc);
1321 }
1322 
1323 /* initialize crtc */
1324 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
1325 				struct drm_plane *plane,
1326 				struct drm_plane *cursor_plane, int id)
1327 {
1328 	struct drm_crtc *crtc = NULL;
1329 	struct mdp5_crtc *mdp5_crtc;
1330 
1331 	mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
1332 	if (!mdp5_crtc)
1333 		return ERR_PTR(-ENOMEM);
1334 
1335 	crtc = &mdp5_crtc->base;
1336 
1337 	mdp5_crtc->id = id;
1338 
1339 	spin_lock_init(&mdp5_crtc->lm_lock);
1340 	spin_lock_init(&mdp5_crtc->cursor.lock);
1341 	init_completion(&mdp5_crtc->pp_completion);
1342 
1343 	mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
1344 	mdp5_crtc->err.irq = mdp5_crtc_err_irq;
1345 	mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
1346 
1347 	mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true;
1348 
1349 	drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane,
1350 				  cursor_plane ?
1351 				  &mdp5_crtc_no_lm_cursor_funcs :
1352 				  &mdp5_crtc_funcs, NULL);
1353 
1354 	drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
1355 			"unref cursor", unref_cursor_worker);
1356 
1357 	drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
1358 
1359 	return crtc;
1360 }
1361