1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/sort.h> 9 10 #include <drm/drm_mode.h> 11 #include <drm/drm_crtc.h> 12 #include <drm/drm_flip_work.h> 13 #include <drm/drm_fourcc.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_vblank.h> 16 17 #include "mdp5_kms.h" 18 19 #define CURSOR_WIDTH 64 20 #define CURSOR_HEIGHT 64 21 22 struct mdp5_crtc { 23 struct drm_crtc base; 24 int id; 25 bool enabled; 26 27 spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */ 28 29 /* if there is a pending flip, these will be non-null: */ 30 struct drm_pending_vblank_event *event; 31 32 /* Bits have been flushed at the last commit, 33 * used to decide if a vsync has happened since last commit. 34 */ 35 u32 flushed_mask; 36 37 #define PENDING_CURSOR 0x1 38 #define PENDING_FLIP 0x2 39 atomic_t pending; 40 41 /* for unref'ing cursor bo's after scanout completes: */ 42 struct drm_flip_work unref_cursor_work; 43 44 struct mdp_irq vblank; 45 struct mdp_irq err; 46 struct mdp_irq pp_done; 47 48 struct completion pp_completion; 49 50 bool lm_cursor_enabled; 51 52 struct { 53 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/ 54 spinlock_t lock; 55 56 /* current cursor being scanned out: */ 57 struct drm_gem_object *scanout_bo; 58 uint64_t iova; 59 uint32_t width, height; 60 int x, y; 61 } cursor; 62 }; 63 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base) 64 65 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc); 66 67 static struct mdp5_kms *get_kms(struct drm_crtc *crtc) 68 { 69 struct msm_drm_private *priv = crtc->dev->dev_private; 70 return to_mdp5_kms(to_mdp_kms(priv->kms)); 71 } 72 73 static void request_pending(struct drm_crtc *crtc, uint32_t pending) 74 { 75 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 76 77 atomic_or(pending, &mdp5_crtc->pending); 78 mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); 79 } 80 81 static void request_pp_done_pending(struct drm_crtc *crtc) 82 { 83 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 84 reinit_completion(&mdp5_crtc->pp_completion); 85 } 86 87 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) 88 { 89 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 90 struct mdp5_ctl *ctl = mdp5_cstate->ctl; 91 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 92 bool start = !mdp5_cstate->defer_start; 93 94 mdp5_cstate->defer_start = false; 95 96 DBG("%s: flush=%08x", crtc->name, flush_mask); 97 98 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); 99 } 100 101 /* 102 * flush updates, to make sure hw is updated to new scanout fb, 103 * so that we can safely queue unref to current fb (ie. next 104 * vblank we know hw is done w/ previous scanout_fb). 105 */ 106 static u32 crtc_flush_all(struct drm_crtc *crtc) 107 { 108 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 109 struct mdp5_hw_mixer *mixer, *r_mixer; 110 struct drm_plane *plane; 111 uint32_t flush_mask = 0; 112 113 /* this should not happen: */ 114 if (WARN_ON(!mdp5_cstate->ctl)) 115 return 0; 116 117 drm_atomic_crtc_for_each_plane(plane, crtc) { 118 if (!plane->state->visible) 119 continue; 120 flush_mask |= mdp5_plane_get_flush(plane); 121 } 122 123 mixer = mdp5_cstate->pipeline.mixer; 124 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); 125 126 r_mixer = mdp5_cstate->pipeline.r_mixer; 127 if (r_mixer) 128 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); 129 130 return crtc_flush(crtc, flush_mask); 131 } 132 133 /* if file!=NULL, this is preclose potential cancel-flip path */ 134 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) 135 { 136 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 137 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 138 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 139 struct mdp5_ctl *ctl = mdp5_cstate->ctl; 140 struct drm_device *dev = crtc->dev; 141 struct drm_pending_vblank_event *event; 142 unsigned long flags; 143 144 spin_lock_irqsave(&dev->event_lock, flags); 145 event = mdp5_crtc->event; 146 if (event) { 147 mdp5_crtc->event = NULL; 148 DBG("%s: send event: %p", crtc->name, event); 149 drm_crtc_send_vblank_event(crtc, event); 150 } 151 spin_unlock_irqrestore(&dev->event_lock, flags); 152 153 if (ctl && !crtc->state->enable) { 154 /* set STAGE_UNUSED for all layers */ 155 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); 156 /* XXX: What to do here? */ 157 /* mdp5_crtc->ctl = NULL; */ 158 } 159 } 160 161 static void unref_cursor_worker(struct drm_flip_work *work, void *val) 162 { 163 struct mdp5_crtc *mdp5_crtc = 164 container_of(work, struct mdp5_crtc, unref_cursor_work); 165 struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); 166 struct msm_kms *kms = &mdp5_kms->base.base; 167 168 msm_gem_unpin_iova(val, kms->aspace); 169 drm_gem_object_put_unlocked(val); 170 } 171 172 static void mdp5_crtc_destroy(struct drm_crtc *crtc) 173 { 174 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 175 176 drm_crtc_cleanup(crtc); 177 drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work); 178 179 kfree(mdp5_crtc); 180 } 181 182 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage) 183 { 184 switch (stage) { 185 case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA; 186 case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA; 187 case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA; 188 case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA; 189 case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA; 190 case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA; 191 case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA; 192 default: 193 return 0; 194 } 195 } 196 197 /* 198 * left/right pipe offsets for the stage array used in blend_setup() 199 */ 200 #define PIPE_LEFT 0 201 #define PIPE_RIGHT 1 202 203 /* 204 * blend_setup() - blend all the planes of a CRTC 205 * 206 * If no base layer is available, border will be enabled as the base layer. 207 * Otherwise all layers will be blended based on their stage calculated 208 * in mdp5_crtc_atomic_check. 209 */ 210 static void blend_setup(struct drm_crtc *crtc) 211 { 212 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 213 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 214 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 215 struct mdp5_kms *mdp5_kms = get_kms(crtc); 216 struct drm_plane *plane; 217 struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL}; 218 const struct mdp_format *format; 219 struct mdp5_hw_mixer *mixer = pipeline->mixer; 220 uint32_t lm = mixer->lm; 221 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; 222 uint32_t r_lm = r_mixer ? r_mixer->lm : 0; 223 struct mdp5_ctl *ctl = mdp5_cstate->ctl; 224 uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0; 225 unsigned long flags; 226 enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; 227 enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; 228 int i, plane_cnt = 0; 229 bool bg_alpha_enabled = false; 230 u32 mixer_op_mode = 0; 231 u32 val; 232 #define blender(stage) ((stage) - STAGE0) 233 234 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags); 235 236 /* ctl could be released already when we are shutting down: */ 237 /* XXX: Can this happen now? */ 238 if (!ctl) 239 goto out; 240 241 /* Collect all plane information */ 242 drm_atomic_crtc_for_each_plane(plane, crtc) { 243 enum mdp5_pipe right_pipe; 244 245 if (!plane->state->visible) 246 continue; 247 248 pstate = to_mdp5_plane_state(plane->state); 249 pstates[pstate->stage] = pstate; 250 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane); 251 /* 252 * if we have a right mixer, stage the same pipe as we 253 * have on the left mixer 254 */ 255 if (r_mixer) 256 r_stage[pstate->stage][PIPE_LEFT] = 257 mdp5_plane_pipe(plane); 258 /* 259 * if we have a right pipe (i.e, the plane comprises of 2 260 * hwpipes, then stage the right pipe on the right side of both 261 * the layer mixers 262 */ 263 right_pipe = mdp5_plane_right_pipe(plane); 264 if (right_pipe) { 265 stage[pstate->stage][PIPE_RIGHT] = right_pipe; 266 r_stage[pstate->stage][PIPE_RIGHT] = right_pipe; 267 } 268 269 plane_cnt++; 270 } 271 272 if (!pstates[STAGE_BASE]) { 273 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT; 274 DBG("Border Color is enabled"); 275 } else if (plane_cnt) { 276 format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb)); 277 278 if (format->alpha_enable) 279 bg_alpha_enabled = true; 280 } 281 282 /* The reset for blending */ 283 for (i = STAGE0; i <= STAGE_MAX; i++) { 284 if (!pstates[i]) 285 continue; 286 287 format = to_mdp_format( 288 msm_framebuffer_format(pstates[i]->base.fb)); 289 plane = pstates[i]->base.plane; 290 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | 291 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST); 292 fg_alpha = pstates[i]->alpha; 293 bg_alpha = 0xFF - pstates[i]->alpha; 294 295 if (!format->alpha_enable && bg_alpha_enabled) 296 mixer_op_mode = 0; 297 else 298 mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i); 299 300 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha); 301 302 if (format->alpha_enable && pstates[i]->premultiplied) { 303 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | 304 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); 305 if (fg_alpha != 0xff) { 306 bg_alpha = fg_alpha; 307 blend_op |= 308 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA | 309 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA; 310 } else { 311 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; 312 } 313 } else if (format->alpha_enable) { 314 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) | 315 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); 316 if (fg_alpha != 0xff) { 317 bg_alpha = fg_alpha; 318 blend_op |= 319 MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA | 320 MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA | 321 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA | 322 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA; 323 } else { 324 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; 325 } 326 } 327 328 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm, 329 blender(i)), blend_op); 330 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm, 331 blender(i)), fg_alpha); 332 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm, 333 blender(i)), bg_alpha); 334 if (r_mixer) { 335 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm, 336 blender(i)), blend_op); 337 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm, 338 blender(i)), fg_alpha); 339 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm, 340 blender(i)), bg_alpha); 341 } 342 } 343 344 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); 345 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), 346 val | mixer_op_mode); 347 if (r_mixer) { 348 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); 349 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), 350 val | mixer_op_mode); 351 } 352 353 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, 354 ctl_blend_flags); 355 out: 356 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags); 357 } 358 359 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc) 360 { 361 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 362 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 363 struct mdp5_kms *mdp5_kms = get_kms(crtc); 364 struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer; 365 struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer; 366 uint32_t lm = mixer->lm; 367 u32 mixer_width, val; 368 unsigned long flags; 369 struct drm_display_mode *mode; 370 371 if (WARN_ON(!crtc->state)) 372 return; 373 374 mode = &crtc->state->adjusted_mode; 375 376 DBG("%s: set mode: " DRM_MODE_FMT, crtc->name, DRM_MODE_ARG(mode)); 377 378 mixer_width = mode->hdisplay; 379 if (r_mixer) 380 mixer_width /= 2; 381 382 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags); 383 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm), 384 MDP5_LM_OUT_SIZE_WIDTH(mixer_width) | 385 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay)); 386 387 /* Assign mixer to LEFT side in source split mode */ 388 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); 389 val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; 390 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val); 391 392 if (r_mixer) { 393 u32 r_lm = r_mixer->lm; 394 395 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm), 396 MDP5_LM_OUT_SIZE_WIDTH(mixer_width) | 397 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay)); 398 399 /* Assign mixer to RIGHT side in source split mode */ 400 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); 401 val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; 402 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val); 403 } 404 405 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags); 406 } 407 408 static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, 409 struct drm_crtc_state *old_state) 410 { 411 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 412 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 413 struct mdp5_kms *mdp5_kms = get_kms(crtc); 414 struct device *dev = &mdp5_kms->pdev->dev; 415 unsigned long flags; 416 417 DBG("%s", crtc->name); 418 419 if (WARN_ON(!mdp5_crtc->enabled)) 420 return; 421 422 /* Disable/save vblank irq handling before power is disabled */ 423 drm_crtc_vblank_off(crtc); 424 425 if (mdp5_cstate->cmd_mode) 426 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); 427 428 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); 429 pm_runtime_put_sync(dev); 430 431 if (crtc->state->event && !crtc->state->active) { 432 WARN_ON(mdp5_crtc->event); 433 spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags); 434 drm_crtc_send_vblank_event(crtc, crtc->state->event); 435 crtc->state->event = NULL; 436 spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags); 437 } 438 439 mdp5_crtc->enabled = false; 440 } 441 442 static void mdp5_crtc_vblank_on(struct drm_crtc *crtc) 443 { 444 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 445 struct mdp5_interface *intf = mdp5_cstate->pipeline.intf; 446 u32 count; 447 448 count = intf->mode == MDP5_INTF_DSI_MODE_COMMAND ? 0 : 0xffffffff; 449 drm_crtc_set_max_vblank_count(crtc, count); 450 451 drm_crtc_vblank_on(crtc); 452 } 453 454 static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, 455 struct drm_crtc_state *old_state) 456 { 457 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 458 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 459 struct mdp5_kms *mdp5_kms = get_kms(crtc); 460 struct device *dev = &mdp5_kms->pdev->dev; 461 462 DBG("%s", crtc->name); 463 464 if (WARN_ON(mdp5_crtc->enabled)) 465 return; 466 467 pm_runtime_get_sync(dev); 468 469 if (mdp5_crtc->lm_cursor_enabled) { 470 /* 471 * Restore LM cursor state, as it might have been lost 472 * with suspend: 473 */ 474 if (mdp5_crtc->cursor.iova) { 475 unsigned long flags; 476 477 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); 478 mdp5_crtc_restore_cursor(crtc); 479 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); 480 481 mdp5_ctl_set_cursor(mdp5_cstate->ctl, 482 &mdp5_cstate->pipeline, 0, true); 483 } else { 484 mdp5_ctl_set_cursor(mdp5_cstate->ctl, 485 &mdp5_cstate->pipeline, 0, false); 486 } 487 } 488 489 /* Restore vblank irq handling after power is enabled */ 490 mdp5_crtc_vblank_on(crtc); 491 492 mdp5_crtc_mode_set_nofb(crtc); 493 494 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); 495 496 if (mdp5_cstate->cmd_mode) 497 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done); 498 499 mdp5_crtc->enabled = true; 500 } 501 502 int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, 503 struct drm_crtc_state *new_crtc_state, 504 bool need_right_mixer) 505 { 506 struct mdp5_crtc_state *mdp5_cstate = 507 to_mdp5_crtc_state(new_crtc_state); 508 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 509 struct mdp5_interface *intf; 510 bool new_mixer = false; 511 512 new_mixer = !pipeline->mixer; 513 514 if ((need_right_mixer && !pipeline->r_mixer) || 515 (!need_right_mixer && pipeline->r_mixer)) 516 new_mixer = true; 517 518 if (new_mixer) { 519 struct mdp5_hw_mixer *old_mixer = pipeline->mixer; 520 struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer; 521 u32 caps; 522 int ret; 523 524 caps = MDP_LM_CAP_DISPLAY; 525 if (need_right_mixer) 526 caps |= MDP_LM_CAP_PAIR; 527 528 ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps, 529 &pipeline->mixer, need_right_mixer ? 530 &pipeline->r_mixer : NULL); 531 if (ret) 532 return ret; 533 534 mdp5_mixer_release(new_crtc_state->state, old_mixer); 535 if (old_r_mixer) { 536 mdp5_mixer_release(new_crtc_state->state, old_r_mixer); 537 if (!need_right_mixer) 538 pipeline->r_mixer = NULL; 539 } 540 } 541 542 /* 543 * these should have been already set up in the encoder's atomic 544 * check (called by drm_atomic_helper_check_modeset) 545 */ 546 intf = pipeline->intf; 547 548 mdp5_cstate->err_irqmask = intf2err(intf->num); 549 mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf); 550 551 if ((intf->type == INTF_DSI) && 552 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) { 553 mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer); 554 mdp5_cstate->cmd_mode = true; 555 } else { 556 mdp5_cstate->pp_done_irqmask = 0; 557 mdp5_cstate->cmd_mode = false; 558 } 559 560 return 0; 561 } 562 563 struct plane_state { 564 struct drm_plane *plane; 565 struct mdp5_plane_state *state; 566 }; 567 568 static int pstate_cmp(const void *a, const void *b) 569 { 570 struct plane_state *pa = (struct plane_state *)a; 571 struct plane_state *pb = (struct plane_state *)b; 572 return pa->state->zpos - pb->state->zpos; 573 } 574 575 /* is there a helper for this? */ 576 static bool is_fullscreen(struct drm_crtc_state *cstate, 577 struct drm_plane_state *pstate) 578 { 579 return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) && 580 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) && 581 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); 582 } 583 584 static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, 585 struct drm_crtc_state *new_crtc_state, 586 struct drm_plane_state *bpstate) 587 { 588 struct mdp5_crtc_state *mdp5_cstate = 589 to_mdp5_crtc_state(new_crtc_state); 590 591 /* 592 * if we're in source split mode, it's mandatory to have 593 * border out on the base stage 594 */ 595 if (mdp5_cstate->pipeline.r_mixer) 596 return STAGE0; 597 598 /* if the bottom-most layer is not fullscreen, we need to use 599 * it for solid-color: 600 */ 601 if (!is_fullscreen(new_crtc_state, bpstate)) 602 return STAGE0; 603 604 return STAGE_BASE; 605 } 606 607 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, 608 struct drm_crtc_state *state) 609 { 610 struct mdp5_kms *mdp5_kms = get_kms(crtc); 611 struct drm_plane *plane; 612 struct drm_device *dev = crtc->dev; 613 struct plane_state pstates[STAGE_MAX + 1]; 614 const struct mdp5_cfg_hw *hw_cfg; 615 const struct drm_plane_state *pstate; 616 const struct drm_display_mode *mode = &state->adjusted_mode; 617 bool cursor_plane = false; 618 bool need_right_mixer = false; 619 int cnt = 0, i; 620 int ret; 621 enum mdp_mixer_stage_id start; 622 623 DBG("%s: check", crtc->name); 624 625 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 626 if (!pstate->visible) 627 continue; 628 629 pstates[cnt].plane = plane; 630 pstates[cnt].state = to_mdp5_plane_state(pstate); 631 632 /* 633 * if any plane on this crtc uses 2 hwpipes, then we need 634 * the crtc to have a right hwmixer. 635 */ 636 if (pstates[cnt].state->r_hwpipe) 637 need_right_mixer = true; 638 cnt++; 639 640 if (plane->type == DRM_PLANE_TYPE_CURSOR) 641 cursor_plane = true; 642 } 643 644 /* bail out early if there aren't any planes */ 645 if (!cnt) 646 return 0; 647 648 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 649 650 /* 651 * we need a right hwmixer if the mode's width is greater than a single 652 * LM's max width 653 */ 654 if (mode->hdisplay > hw_cfg->lm.max_width) 655 need_right_mixer = true; 656 657 ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer); 658 if (ret) { 659 DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret); 660 return ret; 661 } 662 663 /* assign a stage based on sorted zpos property */ 664 sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); 665 666 /* trigger a warning if cursor isn't the highest zorder */ 667 WARN_ON(cursor_plane && 668 (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR)); 669 670 start = get_start_stage(crtc, state, &pstates[0].state->base); 671 672 /* verify that there are not too many planes attached to crtc 673 * and that we don't have conflicting mixer stages: 674 */ 675 if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) { 676 DRM_DEV_ERROR(dev->dev, "too many planes! cnt=%d, start stage=%d\n", 677 cnt, start); 678 return -EINVAL; 679 } 680 681 for (i = 0; i < cnt; i++) { 682 if (cursor_plane && (i == (cnt - 1))) 683 pstates[i].state->stage = hw_cfg->lm.nb_stages; 684 else 685 pstates[i].state->stage = start + i; 686 DBG("%s: assign pipe %s on stage=%d", crtc->name, 687 pstates[i].plane->name, 688 pstates[i].state->stage); 689 } 690 691 return 0; 692 } 693 694 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc, 695 struct drm_crtc_state *old_crtc_state) 696 { 697 DBG("%s: begin", crtc->name); 698 } 699 700 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc, 701 struct drm_crtc_state *old_crtc_state) 702 { 703 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 704 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 705 struct drm_device *dev = crtc->dev; 706 unsigned long flags; 707 708 DBG("%s: event: %p", crtc->name, crtc->state->event); 709 710 WARN_ON(mdp5_crtc->event); 711 712 spin_lock_irqsave(&dev->event_lock, flags); 713 mdp5_crtc->event = crtc->state->event; 714 crtc->state->event = NULL; 715 spin_unlock_irqrestore(&dev->event_lock, flags); 716 717 /* 718 * If no CTL has been allocated in mdp5_crtc_atomic_check(), 719 * it means we are trying to flush a CRTC whose state is disabled: 720 * nothing else needs to be done. 721 */ 722 /* XXX: Can this happen now ? */ 723 if (unlikely(!mdp5_cstate->ctl)) 724 return; 725 726 blend_setup(crtc); 727 728 /* PP_DONE irq is only used by command mode for now. 729 * It is better to request pending before FLUSH and START trigger 730 * to make sure no pp_done irq missed. 731 * This is safe because no pp_done will happen before SW trigger 732 * in command mode. 733 */ 734 if (mdp5_cstate->cmd_mode) 735 request_pp_done_pending(crtc); 736 737 mdp5_crtc->flushed_mask = crtc_flush_all(crtc); 738 739 /* XXX are we leaking out state here? */ 740 mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask; 741 mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask; 742 mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask; 743 744 request_pending(crtc, PENDING_FLIP); 745 } 746 747 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h) 748 { 749 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 750 uint32_t xres = crtc->mode.hdisplay; 751 uint32_t yres = crtc->mode.vdisplay; 752 753 /* 754 * Cursor Region Of Interest (ROI) is a plane read from cursor 755 * buffer to render. The ROI region is determined by the visibility of 756 * the cursor point. In the default Cursor image the cursor point will 757 * be at the top left of the cursor image. 758 * 759 * Without rotation: 760 * If the cursor point reaches the right (xres - x < cursor.width) or 761 * bottom (yres - y < cursor.height) boundary of the screen, then ROI 762 * width and ROI height need to be evaluated to crop the cursor image 763 * accordingly. 764 * (xres-x) will be new cursor width when x > (xres - cursor.width) 765 * (yres-y) will be new cursor height when y > (yres - cursor.height) 766 * 767 * With rotation: 768 * We get negative x and/or y coordinates. 769 * (cursor.width - abs(x)) will be new cursor width when x < 0 770 * (cursor.height - abs(y)) will be new cursor width when y < 0 771 */ 772 if (mdp5_crtc->cursor.x >= 0) 773 *roi_w = min(mdp5_crtc->cursor.width, xres - 774 mdp5_crtc->cursor.x); 775 else 776 *roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x); 777 if (mdp5_crtc->cursor.y >= 0) 778 *roi_h = min(mdp5_crtc->cursor.height, yres - 779 mdp5_crtc->cursor.y); 780 else 781 *roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y); 782 } 783 784 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc) 785 { 786 const struct drm_format_info *info = drm_format_info(DRM_FORMAT_ARGB8888); 787 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 788 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 789 struct mdp5_kms *mdp5_kms = get_kms(crtc); 790 const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; 791 uint32_t blendcfg, stride; 792 uint32_t x, y, src_x, src_y, width, height; 793 uint32_t roi_w, roi_h; 794 int lm; 795 796 assert_spin_locked(&mdp5_crtc->cursor.lock); 797 798 lm = mdp5_cstate->pipeline.mixer->lm; 799 800 x = mdp5_crtc->cursor.x; 801 y = mdp5_crtc->cursor.y; 802 width = mdp5_crtc->cursor.width; 803 height = mdp5_crtc->cursor.height; 804 805 stride = width * info->cpp[0]; 806 807 get_roi(crtc, &roi_w, &roi_h); 808 809 /* If cusror buffer overlaps due to rotation on the 810 * upper or left screen border the pixel offset inside 811 * the cursor buffer of the ROI is the positive overlap 812 * distance. 813 */ 814 if (mdp5_crtc->cursor.x < 0) { 815 src_x = abs(mdp5_crtc->cursor.x); 816 x = 0; 817 } else { 818 src_x = 0; 819 } 820 if (mdp5_crtc->cursor.y < 0) { 821 src_y = abs(mdp5_crtc->cursor.y); 822 y = 0; 823 } else { 824 src_y = 0; 825 } 826 DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d", 827 crtc->name, x, y, roi_w, roi_h, src_x, src_y); 828 829 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); 830 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), 831 MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888)); 832 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm), 833 MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) | 834 MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width)); 835 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), 836 MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) | 837 MDP5_LM_CURSOR_SIZE_ROI_W(roi_w)); 838 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm), 839 MDP5_LM_CURSOR_START_XY_Y_START(y) | 840 MDP5_LM_CURSOR_START_XY_X_START(x)); 841 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm), 842 MDP5_LM_CURSOR_XY_SRC_Y(src_y) | 843 MDP5_LM_CURSOR_XY_SRC_X(src_x)); 844 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), 845 mdp5_crtc->cursor.iova); 846 847 blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN; 848 blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha); 849 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); 850 } 851 852 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, 853 struct drm_file *file, uint32_t handle, 854 uint32_t width, uint32_t height) 855 { 856 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 857 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 858 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 859 struct drm_device *dev = crtc->dev; 860 struct mdp5_kms *mdp5_kms = get_kms(crtc); 861 struct platform_device *pdev = mdp5_kms->pdev; 862 struct msm_kms *kms = &mdp5_kms->base.base; 863 struct drm_gem_object *cursor_bo, *old_bo = NULL; 864 struct mdp5_ctl *ctl; 865 int ret; 866 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); 867 bool cursor_enable = true; 868 unsigned long flags; 869 870 if (!mdp5_crtc->lm_cursor_enabled) { 871 dev_warn(dev->dev, 872 "cursor_set is deprecated with cursor planes\n"); 873 return -EINVAL; 874 } 875 876 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { 877 DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height); 878 return -EINVAL; 879 } 880 881 ctl = mdp5_cstate->ctl; 882 if (!ctl) 883 return -EINVAL; 884 885 /* don't support LM cursors when we we have source split enabled */ 886 if (mdp5_cstate->pipeline.r_mixer) 887 return -EINVAL; 888 889 if (!handle) { 890 DBG("Cursor off"); 891 cursor_enable = false; 892 mdp5_crtc->cursor.iova = 0; 893 pm_runtime_get_sync(&pdev->dev); 894 goto set_cursor; 895 } 896 897 cursor_bo = drm_gem_object_lookup(file, handle); 898 if (!cursor_bo) 899 return -ENOENT; 900 901 ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, 902 &mdp5_crtc->cursor.iova); 903 if (ret) 904 return -EINVAL; 905 906 pm_runtime_get_sync(&pdev->dev); 907 908 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); 909 old_bo = mdp5_crtc->cursor.scanout_bo; 910 911 mdp5_crtc->cursor.scanout_bo = cursor_bo; 912 mdp5_crtc->cursor.width = width; 913 mdp5_crtc->cursor.height = height; 914 915 mdp5_crtc_restore_cursor(crtc); 916 917 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); 918 919 set_cursor: 920 ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable); 921 if (ret) { 922 DRM_DEV_ERROR(dev->dev, "failed to %sable cursor: %d\n", 923 cursor_enable ? "en" : "dis", ret); 924 goto end; 925 } 926 927 crtc_flush(crtc, flush_mask); 928 929 end: 930 pm_runtime_put_sync(&pdev->dev); 931 if (old_bo) { 932 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo); 933 /* enable vblank to complete cursor work: */ 934 request_pending(crtc, PENDING_CURSOR); 935 } 936 return ret; 937 } 938 939 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 940 { 941 struct mdp5_kms *mdp5_kms = get_kms(crtc); 942 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 943 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 944 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); 945 struct drm_device *dev = crtc->dev; 946 uint32_t roi_w; 947 uint32_t roi_h; 948 unsigned long flags; 949 950 if (!mdp5_crtc->lm_cursor_enabled) { 951 dev_warn(dev->dev, 952 "cursor_move is deprecated with cursor planes\n"); 953 return -EINVAL; 954 } 955 956 /* don't support LM cursors when we we have source split enabled */ 957 if (mdp5_cstate->pipeline.r_mixer) 958 return -EINVAL; 959 960 /* In case the CRTC is disabled, just drop the cursor update */ 961 if (unlikely(!crtc->state->enable)) 962 return 0; 963 964 /* accept negative x/y coordinates up to maximum cursor overlap */ 965 mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width); 966 mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height); 967 968 get_roi(crtc, &roi_w, &roi_h); 969 970 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 971 972 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); 973 mdp5_crtc_restore_cursor(crtc); 974 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); 975 976 crtc_flush(crtc, flush_mask); 977 978 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 979 980 return 0; 981 } 982 983 static void 984 mdp5_crtc_atomic_print_state(struct drm_printer *p, 985 const struct drm_crtc_state *state) 986 { 987 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state); 988 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 989 struct mdp5_kms *mdp5_kms = get_kms(state->crtc); 990 991 if (WARN_ON(!pipeline)) 992 return; 993 994 if (mdp5_cstate->ctl) 995 drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl)); 996 997 drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ? 998 pipeline->mixer->name : "(null)"); 999 1000 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) 1001 drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ? 1002 pipeline->r_mixer->name : "(null)"); 1003 1004 drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode); 1005 } 1006 1007 static struct drm_crtc_state * 1008 mdp5_crtc_duplicate_state(struct drm_crtc *crtc) 1009 { 1010 struct mdp5_crtc_state *mdp5_cstate; 1011 1012 if (WARN_ON(!crtc->state)) 1013 return NULL; 1014 1015 mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state), 1016 sizeof(*mdp5_cstate), GFP_KERNEL); 1017 if (!mdp5_cstate) 1018 return NULL; 1019 1020 __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base); 1021 1022 return &mdp5_cstate->base; 1023 } 1024 1025 static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) 1026 { 1027 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state); 1028 1029 __drm_atomic_helper_crtc_destroy_state(state); 1030 1031 kfree(mdp5_cstate); 1032 } 1033 1034 static void mdp5_crtc_reset(struct drm_crtc *crtc) 1035 { 1036 struct mdp5_crtc_state *mdp5_cstate = 1037 kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL); 1038 1039 if (crtc->state) 1040 mdp5_crtc_destroy_state(crtc, crtc->state); 1041 1042 __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); 1043 1044 drm_crtc_vblank_reset(crtc); 1045 } 1046 1047 static const struct drm_crtc_funcs mdp5_crtc_funcs = { 1048 .set_config = drm_atomic_helper_set_config, 1049 .destroy = mdp5_crtc_destroy, 1050 .page_flip = drm_atomic_helper_page_flip, 1051 .reset = mdp5_crtc_reset, 1052 .atomic_duplicate_state = mdp5_crtc_duplicate_state, 1053 .atomic_destroy_state = mdp5_crtc_destroy_state, 1054 .cursor_set = mdp5_crtc_cursor_set, 1055 .cursor_move = mdp5_crtc_cursor_move, 1056 .atomic_print_state = mdp5_crtc_atomic_print_state, 1057 }; 1058 1059 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = { 1060 .mode_set_nofb = mdp5_crtc_mode_set_nofb, 1061 .atomic_check = mdp5_crtc_atomic_check, 1062 .atomic_begin = mdp5_crtc_atomic_begin, 1063 .atomic_flush = mdp5_crtc_atomic_flush, 1064 .atomic_enable = mdp5_crtc_atomic_enable, 1065 .atomic_disable = mdp5_crtc_atomic_disable, 1066 }; 1067 1068 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) 1069 { 1070 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank); 1071 struct drm_crtc *crtc = &mdp5_crtc->base; 1072 struct msm_drm_private *priv = crtc->dev->dev_private; 1073 unsigned pending; 1074 1075 mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank); 1076 1077 pending = atomic_xchg(&mdp5_crtc->pending, 0); 1078 1079 if (pending & PENDING_FLIP) { 1080 complete_flip(crtc, NULL); 1081 } 1082 1083 if (pending & PENDING_CURSOR) 1084 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq); 1085 } 1086 1087 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) 1088 { 1089 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err); 1090 1091 DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus); 1092 } 1093 1094 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus) 1095 { 1096 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, 1097 pp_done); 1098 1099 complete(&mdp5_crtc->pp_completion); 1100 } 1101 1102 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc) 1103 { 1104 struct drm_device *dev = crtc->dev; 1105 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 1106 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1107 int ret; 1108 1109 ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion, 1110 msecs_to_jiffies(50)); 1111 if (ret == 0) 1112 dev_warn(dev->dev, "pp done time out, lm=%d\n", 1113 mdp5_cstate->pipeline.mixer->lm); 1114 } 1115 1116 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc) 1117 { 1118 struct drm_device *dev = crtc->dev; 1119 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 1120 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1121 struct mdp5_ctl *ctl = mdp5_cstate->ctl; 1122 int ret; 1123 1124 /* Should not call this function if crtc is disabled. */ 1125 if (!ctl) 1126 return; 1127 1128 ret = drm_crtc_vblank_get(crtc); 1129 if (ret) 1130 return; 1131 1132 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue, 1133 ((mdp5_ctl_get_commit_status(ctl) & 1134 mdp5_crtc->flushed_mask) == 0), 1135 msecs_to_jiffies(50)); 1136 if (ret <= 0) 1137 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id); 1138 1139 mdp5_crtc->flushed_mask = 0; 1140 1141 drm_crtc_vblank_put(crtc); 1142 } 1143 1144 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc) 1145 { 1146 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 1147 return mdp5_crtc->vblank.irqmask; 1148 } 1149 1150 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc) 1151 { 1152 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1153 struct mdp5_kms *mdp5_kms = get_kms(crtc); 1154 1155 /* should this be done elsewhere ? */ 1156 mdp_irq_update(&mdp5_kms->base); 1157 1158 mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline); 1159 } 1160 1161 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc) 1162 { 1163 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1164 1165 return mdp5_cstate->ctl; 1166 } 1167 1168 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc) 1169 { 1170 struct mdp5_crtc_state *mdp5_cstate; 1171 1172 if (WARN_ON(!crtc)) 1173 return ERR_PTR(-EINVAL); 1174 1175 mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1176 1177 return WARN_ON(!mdp5_cstate->pipeline.mixer) ? 1178 ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer; 1179 } 1180 1181 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc) 1182 { 1183 struct mdp5_crtc_state *mdp5_cstate; 1184 1185 if (WARN_ON(!crtc)) 1186 return ERR_PTR(-EINVAL); 1187 1188 mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1189 1190 return &mdp5_cstate->pipeline; 1191 } 1192 1193 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc) 1194 { 1195 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1196 1197 if (mdp5_cstate->cmd_mode) 1198 mdp5_crtc_wait_for_pp_done(crtc); 1199 else 1200 mdp5_crtc_wait_for_flush_done(crtc); 1201 } 1202 1203 /* initialize crtc */ 1204 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, 1205 struct drm_plane *plane, 1206 struct drm_plane *cursor_plane, int id) 1207 { 1208 struct drm_crtc *crtc = NULL; 1209 struct mdp5_crtc *mdp5_crtc; 1210 1211 mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL); 1212 if (!mdp5_crtc) 1213 return ERR_PTR(-ENOMEM); 1214 1215 crtc = &mdp5_crtc->base; 1216 1217 mdp5_crtc->id = id; 1218 1219 spin_lock_init(&mdp5_crtc->lm_lock); 1220 spin_lock_init(&mdp5_crtc->cursor.lock); 1221 init_completion(&mdp5_crtc->pp_completion); 1222 1223 mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq; 1224 mdp5_crtc->err.irq = mdp5_crtc_err_irq; 1225 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq; 1226 1227 mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true; 1228 1229 drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane, 1230 &mdp5_crtc_funcs, NULL); 1231 1232 drm_flip_work_init(&mdp5_crtc->unref_cursor_work, 1233 "unref cursor", unref_cursor_worker); 1234 1235 drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs); 1236 1237 return crtc; 1238 } 1239