1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "mdp5_kms.h" 7 #include "mdp5_cfg.h" 8 9 struct mdp5_cfg_handler { 10 int revision; 11 struct mdp5_cfg config; 12 }; 13 14 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */ 15 const struct mdp5_cfg_hw *mdp5_cfg = NULL; 16 17 static const struct mdp5_cfg_hw msm8x74v1_config = { 18 .name = "msm8x74v1", 19 .mdp = { 20 .count = 1, 21 .caps = MDP_CAP_SMP | 22 0, 23 }, 24 .smp = { 25 .mmb_count = 22, 26 .mmb_size = 4096, 27 .clients = { 28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7, 29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 30 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18, 31 }, 32 }, 33 .ctl = { 34 .count = 5, 35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, 36 .flush_hw_mask = 0x0003ffff, 37 }, 38 .pipe_vig = { 39 .count = 3, 40 .base = { 0x01100, 0x01500, 0x01900 }, 41 .caps = MDP_PIPE_CAP_HFLIP | 42 MDP_PIPE_CAP_VFLIP | 43 MDP_PIPE_CAP_SCALE | 44 MDP_PIPE_CAP_CSC | 45 0, 46 }, 47 .pipe_rgb = { 48 .count = 3, 49 .base = { 0x01d00, 0x02100, 0x02500 }, 50 .caps = MDP_PIPE_CAP_HFLIP | 51 MDP_PIPE_CAP_VFLIP | 52 MDP_PIPE_CAP_SCALE | 53 0, 54 }, 55 .pipe_dma = { 56 .count = 2, 57 .base = { 0x02900, 0x02d00 }, 58 .caps = MDP_PIPE_CAP_HFLIP | 59 MDP_PIPE_CAP_VFLIP | 60 0, 61 }, 62 .lm = { 63 .count = 5, 64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 }, 65 .instances = { 66 { .id = 0, .pp = 0, .dspp = 0, 67 .caps = MDP_LM_CAP_DISPLAY, }, 68 { .id = 1, .pp = 1, .dspp = 1, 69 .caps = MDP_LM_CAP_DISPLAY, }, 70 { .id = 2, .pp = 2, .dspp = 2, 71 .caps = MDP_LM_CAP_DISPLAY, }, 72 { .id = 3, .pp = -1, .dspp = -1, 73 .caps = MDP_LM_CAP_WB }, 74 { .id = 4, .pp = -1, .dspp = -1, 75 .caps = MDP_LM_CAP_WB }, 76 }, 77 .nb_stages = 5, 78 .max_width = 2048, 79 .max_height = 0xFFFF, 80 }, 81 .dspp = { 82 .count = 3, 83 .base = { 0x04500, 0x04900, 0x04d00 }, 84 }, 85 .pp = { 86 .count = 3, 87 .base = { 0x21a00, 0x21b00, 0x21c00 }, 88 }, 89 .intf = { 90 .base = { 0x21000, 0x21200, 0x21400, 0x21600 }, 91 .connect = { 92 [0] = INTF_eDP, 93 [1] = INTF_DSI, 94 [2] = INTF_DSI, 95 [3] = INTF_HDMI, 96 }, 97 }, 98 .perf = { 99 .ab_inefficiency = 200, 100 .ib_inefficiency = 120, 101 .clk_inefficiency = 125 102 }, 103 .max_clk = 200000000, 104 }; 105 106 static const struct mdp5_cfg_hw msm8x74v2_config = { 107 .name = "msm8x74", 108 .mdp = { 109 .count = 1, 110 .caps = MDP_CAP_SMP | 111 0, 112 }, 113 .smp = { 114 .mmb_count = 22, 115 .mmb_size = 4096, 116 .clients = { 117 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7, 118 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 119 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18, 120 }, 121 }, 122 .ctl = { 123 .count = 5, 124 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, 125 .flush_hw_mask = 0x0003ffff, 126 }, 127 .pipe_vig = { 128 .count = 3, 129 .base = { 0x01100, 0x01500, 0x01900 }, 130 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 131 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | 132 MDP_PIPE_CAP_DECIMATION, 133 }, 134 .pipe_rgb = { 135 .count = 3, 136 .base = { 0x01d00, 0x02100, 0x02500 }, 137 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 138 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, 139 }, 140 .pipe_dma = { 141 .count = 2, 142 .base = { 0x02900, 0x02d00 }, 143 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, 144 }, 145 .lm = { 146 .count = 5, 147 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 }, 148 .instances = { 149 { .id = 0, .pp = 0, .dspp = 0, 150 .caps = MDP_LM_CAP_DISPLAY, }, 151 { .id = 1, .pp = 1, .dspp = 1, 152 .caps = MDP_LM_CAP_DISPLAY, }, 153 { .id = 2, .pp = 2, .dspp = 2, 154 .caps = MDP_LM_CAP_DISPLAY, }, 155 { .id = 3, .pp = -1, .dspp = -1, 156 .caps = MDP_LM_CAP_WB, }, 157 { .id = 4, .pp = -1, .dspp = -1, 158 .caps = MDP_LM_CAP_WB, }, 159 }, 160 .nb_stages = 5, 161 .max_width = 2048, 162 .max_height = 0xFFFF, 163 }, 164 .dspp = { 165 .count = 3, 166 .base = { 0x04500, 0x04900, 0x04d00 }, 167 }, 168 .ad = { 169 .count = 2, 170 .base = { 0x13000, 0x13200 }, 171 }, 172 .pp = { 173 .count = 3, 174 .base = { 0x12c00, 0x12d00, 0x12e00 }, 175 }, 176 .intf = { 177 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 }, 178 .connect = { 179 [0] = INTF_eDP, 180 [1] = INTF_DSI, 181 [2] = INTF_DSI, 182 [3] = INTF_HDMI, 183 }, 184 }, 185 .perf = { 186 .ab_inefficiency = 200, 187 .ib_inefficiency = 120, 188 .clk_inefficiency = 125 189 }, 190 .max_clk = 320000000, 191 }; 192 193 static const struct mdp5_cfg_hw apq8084_config = { 194 .name = "apq8084", 195 .mdp = { 196 .count = 1, 197 .caps = MDP_CAP_SMP | 198 MDP_CAP_SRC_SPLIT | 199 0, 200 }, 201 .smp = { 202 .mmb_count = 44, 203 .mmb_size = 8192, 204 .clients = { 205 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, 206 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19, 207 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 208 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, 209 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22, 210 }, 211 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */ 212 .reserved = { 213 /* Two SMP blocks are statically tied to RGB pipes: */ 214 [16] = 2, [17] = 2, [18] = 2, [22] = 2, 215 }, 216 }, 217 .ctl = { 218 .count = 5, 219 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, 220 .flush_hw_mask = 0x003fffff, 221 }, 222 .pipe_vig = { 223 .count = 4, 224 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 }, 225 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 226 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | 227 MDP_PIPE_CAP_DECIMATION, 228 }, 229 .pipe_rgb = { 230 .count = 4, 231 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 }, 232 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 233 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, 234 }, 235 .pipe_dma = { 236 .count = 2, 237 .base = { 0x03100, 0x03500 }, 238 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, 239 }, 240 .lm = { 241 .count = 6, 242 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 }, 243 .instances = { 244 { .id = 0, .pp = 0, .dspp = 0, 245 .caps = MDP_LM_CAP_DISPLAY | 246 MDP_LM_CAP_PAIR, }, 247 { .id = 1, .pp = 1, .dspp = 1, 248 .caps = MDP_LM_CAP_DISPLAY, }, 249 { .id = 2, .pp = 2, .dspp = 2, 250 .caps = MDP_LM_CAP_DISPLAY | 251 MDP_LM_CAP_PAIR, }, 252 { .id = 3, .pp = -1, .dspp = -1, 253 .caps = MDP_LM_CAP_WB, }, 254 { .id = 4, .pp = -1, .dspp = -1, 255 .caps = MDP_LM_CAP_WB, }, 256 { .id = 5, .pp = 3, .dspp = 3, 257 .caps = MDP_LM_CAP_DISPLAY, }, 258 }, 259 .nb_stages = 5, 260 .max_width = 2048, 261 .max_height = 0xFFFF, 262 }, 263 .dspp = { 264 .count = 4, 265 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 }, 266 267 }, 268 .ad = { 269 .count = 3, 270 .base = { 0x13400, 0x13600, 0x13800 }, 271 }, 272 .pp = { 273 .count = 4, 274 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 }, 275 }, 276 .intf = { 277 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 }, 278 .connect = { 279 [0] = INTF_eDP, 280 [1] = INTF_DSI, 281 [2] = INTF_DSI, 282 [3] = INTF_HDMI, 283 }, 284 }, 285 .perf = { 286 .ab_inefficiency = 200, 287 .ib_inefficiency = 120, 288 .clk_inefficiency = 105 289 }, 290 .max_clk = 320000000, 291 }; 292 293 static const struct mdp5_cfg_hw msm8x16_config = { 294 .name = "msm8x16", 295 .mdp = { 296 .count = 1, 297 .base = { 0x0 }, 298 .caps = MDP_CAP_SMP | 299 0, 300 }, 301 .smp = { 302 .mmb_count = 8, 303 .mmb_size = 8192, 304 .clients = { 305 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4, 306 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8, 307 }, 308 }, 309 .ctl = { 310 .count = 5, 311 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, 312 .flush_hw_mask = 0x4003ffff, 313 }, 314 .pipe_vig = { 315 .count = 1, 316 .base = { 0x04000 }, 317 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 318 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | 319 MDP_PIPE_CAP_DECIMATION, 320 }, 321 .pipe_rgb = { 322 .count = 2, 323 .base = { 0x14000, 0x16000 }, 324 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 325 MDP_PIPE_CAP_DECIMATION, 326 }, 327 .pipe_dma = { 328 .count = 1, 329 .base = { 0x24000 }, 330 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, 331 }, 332 .lm = { 333 .count = 2, /* LM0 and LM3 */ 334 .base = { 0x44000, 0x47000 }, 335 .instances = { 336 { .id = 0, .pp = 0, .dspp = 0, 337 .caps = MDP_LM_CAP_DISPLAY, }, 338 { .id = 3, .pp = -1, .dspp = -1, 339 .caps = MDP_LM_CAP_WB }, 340 }, 341 .nb_stages = 8, 342 .max_width = 2048, 343 .max_height = 0xFFFF, 344 }, 345 .dspp = { 346 .count = 1, 347 .base = { 0x54000 }, 348 349 }, 350 .intf = { 351 .base = { 0x00000, 0x6a800 }, 352 .connect = { 353 [0] = INTF_DISABLED, 354 [1] = INTF_DSI, 355 }, 356 }, 357 .perf = { 358 .ab_inefficiency = 100, 359 .ib_inefficiency = 200, 360 .clk_inefficiency = 105 361 }, 362 .max_clk = 320000000, 363 }; 364 365 static const struct mdp5_cfg_hw msm8x36_config = { 366 .name = "msm8x36", 367 .mdp = { 368 .count = 1, 369 .base = { 0x0 }, 370 .caps = MDP_CAP_SMP | 371 0, 372 }, 373 .smp = { 374 .mmb_count = 8, 375 .mmb_size = 10240, 376 .clients = { 377 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4, 378 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8, 379 }, 380 }, 381 .ctl = { 382 .count = 3, 383 .base = { 0x01000, 0x01200, 0x01400 }, 384 .flush_hw_mask = 0x4003ffff, 385 }, 386 .pipe_vig = { 387 .count = 1, 388 .base = { 0x04000 }, 389 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 390 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | 391 MDP_PIPE_CAP_DECIMATION, 392 }, 393 .pipe_rgb = { 394 .count = 2, 395 .base = { 0x14000, 0x16000 }, 396 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 397 MDP_PIPE_CAP_DECIMATION, 398 }, 399 .pipe_dma = { 400 .count = 1, 401 .base = { 0x24000 }, 402 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, 403 }, 404 .lm = { 405 .count = 2, 406 .base = { 0x44000, 0x47000 }, 407 .instances = { 408 { .id = 0, .pp = 0, .dspp = 0, 409 .caps = MDP_LM_CAP_DISPLAY, }, 410 { .id = 1, .pp = -1, .dspp = -1, 411 .caps = MDP_LM_CAP_WB, }, 412 }, 413 .nb_stages = 8, 414 .max_width = 2560, 415 .max_height = 0xFFFF, 416 }, 417 .pp = { 418 .count = 1, 419 .base = { 0x70000 }, 420 }, 421 .ad = { 422 .count = 1, 423 .base = { 0x78000 }, 424 }, 425 .dspp = { 426 .count = 1, 427 .base = { 0x54000 }, 428 }, 429 .intf = { 430 .base = { 0x00000, 0x6a800, 0x6b000 }, 431 .connect = { 432 [0] = INTF_DISABLED, 433 [1] = INTF_DSI, 434 [2] = INTF_DSI, 435 }, 436 }, 437 .perf = { 438 .ab_inefficiency = 100, 439 .ib_inefficiency = 200, 440 .clk_inefficiency = 105 441 }, 442 .max_clk = 366670000, 443 }; 444 445 static const struct mdp5_cfg_hw msm8x94_config = { 446 .name = "msm8x94", 447 .mdp = { 448 .count = 1, 449 .caps = MDP_CAP_SMP | 450 MDP_CAP_SRC_SPLIT | 451 0, 452 }, 453 .smp = { 454 .mmb_count = 44, 455 .mmb_size = 8192, 456 .clients = { 457 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, 458 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19, 459 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 460 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, 461 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22, 462 }, 463 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */ 464 .reserved = { 465 [1] = 1, [4] = 1, [7] = 1, [19] = 1, 466 [16] = 5, [17] = 5, [18] = 5, [22] = 5, 467 }, 468 }, 469 .ctl = { 470 .count = 5, 471 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, 472 .flush_hw_mask = 0xf0ffffff, 473 }, 474 .pipe_vig = { 475 .count = 4, 476 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, 477 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 478 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | 479 MDP_PIPE_CAP_DECIMATION, 480 }, 481 .pipe_rgb = { 482 .count = 4, 483 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, 484 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 485 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, 486 }, 487 .pipe_dma = { 488 .count = 2, 489 .base = { 0x24000, 0x26000 }, 490 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, 491 }, 492 .lm = { 493 .count = 6, 494 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, 495 .instances = { 496 { .id = 0, .pp = 0, .dspp = 0, 497 .caps = MDP_LM_CAP_DISPLAY | 498 MDP_LM_CAP_PAIR, }, 499 { .id = 1, .pp = 1, .dspp = 1, 500 .caps = MDP_LM_CAP_DISPLAY, }, 501 { .id = 2, .pp = 2, .dspp = 2, 502 .caps = MDP_LM_CAP_DISPLAY | 503 MDP_LM_CAP_PAIR, }, 504 { .id = 3, .pp = -1, .dspp = -1, 505 .caps = MDP_LM_CAP_WB, }, 506 { .id = 4, .pp = -1, .dspp = -1, 507 .caps = MDP_LM_CAP_WB, }, 508 { .id = 5, .pp = 3, .dspp = 3, 509 .caps = MDP_LM_CAP_DISPLAY, }, 510 }, 511 .nb_stages = 8, 512 .max_width = 2048, 513 .max_height = 0xFFFF, 514 }, 515 .dspp = { 516 .count = 4, 517 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 }, 518 519 }, 520 .ad = { 521 .count = 3, 522 .base = { 0x78000, 0x78800, 0x79000 }, 523 }, 524 .pp = { 525 .count = 4, 526 .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, 527 }, 528 .intf = { 529 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, 530 .connect = { 531 [0] = INTF_DISABLED, 532 [1] = INTF_DSI, 533 [2] = INTF_DSI, 534 [3] = INTF_HDMI, 535 }, 536 }, 537 .perf = { 538 .ab_inefficiency = 100, 539 .ib_inefficiency = 100, 540 .clk_inefficiency = 105 541 }, 542 .max_clk = 400000000, 543 }; 544 545 static const struct mdp5_cfg_hw msm8x96_config = { 546 .name = "msm8x96", 547 .mdp = { 548 .count = 1, 549 .caps = MDP_CAP_DSC | 550 MDP_CAP_CDM | 551 MDP_CAP_SRC_SPLIT | 552 0, 553 }, 554 .ctl = { 555 .count = 5, 556 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, 557 .flush_hw_mask = 0xf4ffffff, 558 }, 559 .pipe_vig = { 560 .count = 4, 561 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, 562 .caps = MDP_PIPE_CAP_HFLIP | 563 MDP_PIPE_CAP_VFLIP | 564 MDP_PIPE_CAP_SCALE | 565 MDP_PIPE_CAP_CSC | 566 MDP_PIPE_CAP_DECIMATION | 567 MDP_PIPE_CAP_SW_PIX_EXT | 568 0, 569 }, 570 .pipe_rgb = { 571 .count = 4, 572 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, 573 .caps = MDP_PIPE_CAP_HFLIP | 574 MDP_PIPE_CAP_VFLIP | 575 MDP_PIPE_CAP_SCALE | 576 MDP_PIPE_CAP_DECIMATION | 577 MDP_PIPE_CAP_SW_PIX_EXT | 578 0, 579 }, 580 .pipe_dma = { 581 .count = 2, 582 .base = { 0x24000, 0x26000 }, 583 .caps = MDP_PIPE_CAP_HFLIP | 584 MDP_PIPE_CAP_VFLIP | 585 MDP_PIPE_CAP_SW_PIX_EXT | 586 0, 587 }, 588 .pipe_cursor = { 589 .count = 2, 590 .base = { 0x34000, 0x36000 }, 591 .caps = MDP_PIPE_CAP_HFLIP | 592 MDP_PIPE_CAP_VFLIP | 593 MDP_PIPE_CAP_SW_PIX_EXT | 594 MDP_PIPE_CAP_CURSOR | 595 0, 596 }, 597 598 .lm = { 599 .count = 6, 600 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, 601 .instances = { 602 { .id = 0, .pp = 0, .dspp = 0, 603 .caps = MDP_LM_CAP_DISPLAY | 604 MDP_LM_CAP_PAIR, }, 605 { .id = 1, .pp = 1, .dspp = 1, 606 .caps = MDP_LM_CAP_DISPLAY, }, 607 { .id = 2, .pp = 2, .dspp = -1, 608 .caps = MDP_LM_CAP_DISPLAY | 609 MDP_LM_CAP_PAIR, }, 610 { .id = 3, .pp = -1, .dspp = -1, 611 .caps = MDP_LM_CAP_WB, }, 612 { .id = 4, .pp = -1, .dspp = -1, 613 .caps = MDP_LM_CAP_WB, }, 614 { .id = 5, .pp = 3, .dspp = -1, 615 .caps = MDP_LM_CAP_DISPLAY, }, 616 }, 617 .nb_stages = 8, 618 .max_width = 2560, 619 .max_height = 0xFFFF, 620 }, 621 .dspp = { 622 .count = 2, 623 .base = { 0x54000, 0x56000 }, 624 }, 625 .ad = { 626 .count = 3, 627 .base = { 0x78000, 0x78800, 0x79000 }, 628 }, 629 .pp = { 630 .count = 4, 631 .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, 632 }, 633 .cdm = { 634 .count = 1, 635 .base = { 0x79200 }, 636 }, 637 .dsc = { 638 .count = 2, 639 .base = { 0x80000, 0x80400 }, 640 }, 641 .intf = { 642 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, 643 .connect = { 644 [0] = INTF_DISABLED, 645 [1] = INTF_DSI, 646 [2] = INTF_DSI, 647 [3] = INTF_HDMI, 648 }, 649 }, 650 .perf = { 651 .ab_inefficiency = 100, 652 .ib_inefficiency = 200, 653 .clk_inefficiency = 105 654 }, 655 .max_clk = 412500000, 656 }; 657 658 const struct mdp5_cfg_hw msm8x76_config = { 659 .name = "msm8x76", 660 .mdp = { 661 .count = 1, 662 .caps = MDP_CAP_SMP | 663 MDP_CAP_DSC | 664 MDP_CAP_SRC_SPLIT | 665 0, 666 }, 667 .ctl = { 668 .count = 3, 669 .base = { 0x01000, 0x01200, 0x01400 }, 670 .flush_hw_mask = 0xffffffff, 671 }, 672 .smp = { 673 .mmb_count = 10, 674 .mmb_size = 10240, 675 .clients = { 676 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9, 677 [SSPP_DMA0] = 4, 678 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8, 679 }, 680 }, 681 .pipe_vig = { 682 .count = 2, 683 .base = { 0x04000, 0x06000 }, 684 .caps = MDP_PIPE_CAP_HFLIP | 685 MDP_PIPE_CAP_VFLIP | 686 MDP_PIPE_CAP_SCALE | 687 MDP_PIPE_CAP_CSC | 688 MDP_PIPE_CAP_DECIMATION | 689 MDP_PIPE_CAP_SW_PIX_EXT | 690 0, 691 }, 692 .pipe_rgb = { 693 .count = 2, 694 .base = { 0x14000, 0x16000 }, 695 .caps = MDP_PIPE_CAP_HFLIP | 696 MDP_PIPE_CAP_VFLIP | 697 MDP_PIPE_CAP_DECIMATION | 698 MDP_PIPE_CAP_SW_PIX_EXT | 699 0, 700 }, 701 .pipe_dma = { 702 .count = 1, 703 .base = { 0x24000 }, 704 .caps = MDP_PIPE_CAP_HFLIP | 705 MDP_PIPE_CAP_VFLIP | 706 MDP_PIPE_CAP_SW_PIX_EXT | 707 0, 708 }, 709 .pipe_cursor = { 710 .count = 1, 711 .base = { 0x440DC }, 712 .caps = MDP_PIPE_CAP_HFLIP | 713 MDP_PIPE_CAP_VFLIP | 714 MDP_PIPE_CAP_SW_PIX_EXT | 715 MDP_PIPE_CAP_CURSOR | 716 0, 717 }, 718 .lm = { 719 .count = 2, 720 .base = { 0x44000, 0x45000 }, 721 .instances = { 722 { .id = 0, .pp = 0, .dspp = 0, 723 .caps = MDP_LM_CAP_DISPLAY, }, 724 { .id = 1, .pp = -1, .dspp = -1, 725 .caps = MDP_LM_CAP_WB }, 726 }, 727 .nb_stages = 8, 728 .max_width = 2560, 729 .max_height = 0xFFFF, 730 }, 731 .dspp = { 732 .count = 1, 733 .base = { 0x54000 }, 734 735 }, 736 .pp = { 737 .count = 3, 738 .base = { 0x70000, 0x70800, 0x72000 }, 739 }, 740 .dsc = { 741 .count = 2, 742 .base = { 0x80000, 0x80400 }, 743 }, 744 .intf = { 745 .base = { 0x6a000, 0x6a800, 0x6b000 }, 746 .connect = { 747 [0] = INTF_DISABLED, 748 [1] = INTF_DSI, 749 [2] = INTF_DSI, 750 }, 751 }, 752 .max_clk = 360000000, 753 }; 754 755 static const struct mdp5_cfg_hw msm8x53_config = { 756 .name = "msm8x53", 757 .mdp = { 758 .count = 1, 759 .caps = MDP_CAP_CDM | 760 MDP_CAP_SRC_SPLIT, 761 }, 762 .ctl = { 763 .count = 3, 764 .base = { 0x01000, 0x01200, 0x01400 }, 765 .flush_hw_mask = 0xffffffff, 766 }, 767 .pipe_vig = { 768 .count = 1, 769 .base = { 0x04000 }, 770 .caps = MDP_PIPE_CAP_HFLIP | 771 MDP_PIPE_CAP_VFLIP | 772 MDP_PIPE_CAP_SCALE | 773 MDP_PIPE_CAP_CSC | 774 MDP_PIPE_CAP_DECIMATION | 775 MDP_PIPE_CAP_SW_PIX_EXT | 776 0, 777 }, 778 .pipe_rgb = { 779 .count = 2, 780 .base = { 0x14000, 0x16000 }, 781 .caps = MDP_PIPE_CAP_HFLIP | 782 MDP_PIPE_CAP_VFLIP | 783 MDP_PIPE_CAP_DECIMATION | 784 MDP_PIPE_CAP_SW_PIX_EXT | 785 0, 786 }, 787 .pipe_dma = { 788 .count = 1, 789 .base = { 0x24000 }, 790 .caps = MDP_PIPE_CAP_HFLIP | 791 MDP_PIPE_CAP_VFLIP | 792 MDP_PIPE_CAP_SW_PIX_EXT | 793 0, 794 }, 795 .pipe_cursor = { 796 .count = 1, 797 .base = { 0x34000 }, 798 .caps = MDP_PIPE_CAP_HFLIP | 799 MDP_PIPE_CAP_VFLIP | 800 MDP_PIPE_CAP_SW_PIX_EXT | 801 MDP_PIPE_CAP_CURSOR | 802 0, 803 }, 804 805 .lm = { 806 .count = 3, 807 .base = { 0x44000, 0x45000 }, 808 .instances = { 809 { .id = 0, .pp = 0, .dspp = 0, 810 .caps = MDP_LM_CAP_DISPLAY | 811 MDP_LM_CAP_PAIR }, 812 { .id = 1, .pp = 1, .dspp = -1, 813 .caps = MDP_LM_CAP_DISPLAY }, 814 }, 815 .nb_stages = 5, 816 .max_width = 2048, 817 .max_height = 0xFFFF, 818 }, 819 .dspp = { 820 .count = 1, 821 .base = { 0x54000 }, 822 823 }, 824 .pp = { 825 .count = 2, 826 .base = { 0x70000, 0x70800 }, 827 }, 828 .cdm = { 829 .count = 1, 830 .base = { 0x79200 }, 831 }, 832 .intf = { 833 .base = { 0x6a000, 0x6a800, 0x6b000 }, 834 .connect = { 835 [0] = INTF_DISABLED, 836 [1] = INTF_DSI, 837 [2] = INTF_DSI, 838 }, 839 }, 840 .max_clk = 400000000, 841 }; 842 843 static const struct mdp5_cfg_hw msm8917_config = { 844 .name = "msm8917", 845 .mdp = { 846 .count = 1, 847 .caps = MDP_CAP_CDM, 848 }, 849 .ctl = { 850 .count = 3, 851 .base = { 0x01000, 0x01200, 0x01400 }, 852 .flush_hw_mask = 0xffffffff, 853 }, 854 .pipe_vig = { 855 .count = 1, 856 .base = { 0x04000 }, 857 .caps = MDP_PIPE_CAP_HFLIP | 858 MDP_PIPE_CAP_VFLIP | 859 MDP_PIPE_CAP_SCALE | 860 MDP_PIPE_CAP_CSC | 861 MDP_PIPE_CAP_DECIMATION | 862 MDP_PIPE_CAP_SW_PIX_EXT | 863 0, 864 }, 865 .pipe_rgb = { 866 .count = 2, 867 .base = { 0x14000, 0x16000 }, 868 .caps = MDP_PIPE_CAP_HFLIP | 869 MDP_PIPE_CAP_VFLIP | 870 MDP_PIPE_CAP_DECIMATION | 871 MDP_PIPE_CAP_SW_PIX_EXT | 872 0, 873 }, 874 .pipe_dma = { 875 .count = 1, 876 .base = { 0x24000 }, 877 .caps = MDP_PIPE_CAP_HFLIP | 878 MDP_PIPE_CAP_VFLIP | 879 MDP_PIPE_CAP_SW_PIX_EXT | 880 0, 881 }, 882 .pipe_cursor = { 883 .count = 1, 884 .base = { 0x34000 }, 885 .caps = MDP_PIPE_CAP_HFLIP | 886 MDP_PIPE_CAP_VFLIP | 887 MDP_PIPE_CAP_SW_PIX_EXT | 888 MDP_PIPE_CAP_CURSOR | 889 0, 890 }, 891 892 .lm = { 893 .count = 2, 894 .base = { 0x44000, 0x45000 }, 895 .instances = { 896 { .id = 0, .pp = 0, .dspp = 0, 897 .caps = MDP_LM_CAP_DISPLAY, }, 898 { .id = 1, .pp = -1, .dspp = -1, 899 .caps = MDP_LM_CAP_WB }, 900 }, 901 .nb_stages = 8, 902 .max_width = 2048, 903 .max_height = 0xFFFF, 904 }, 905 .dspp = { 906 .count = 1, 907 .base = { 0x54000 }, 908 909 }, 910 .pp = { 911 .count = 1, 912 .base = { 0x70000 }, 913 }, 914 .cdm = { 915 .count = 1, 916 .base = { 0x79200 }, 917 }, 918 .intf = { 919 .base = { 0x6a000, 0x6a800 }, 920 .connect = { 921 [0] = INTF_DISABLED, 922 [1] = INTF_DSI, 923 }, 924 }, 925 .max_clk = 320000000, 926 }; 927 928 static const struct mdp5_cfg_hw msm8998_config = { 929 .name = "msm8998", 930 .mdp = { 931 .count = 1, 932 .caps = MDP_CAP_DSC | 933 MDP_CAP_CDM | 934 MDP_CAP_SRC_SPLIT | 935 0, 936 }, 937 .ctl = { 938 .count = 5, 939 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, 940 .flush_hw_mask = 0xf7ffffff, 941 }, 942 .pipe_vig = { 943 .count = 4, 944 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, 945 .caps = MDP_PIPE_CAP_HFLIP | 946 MDP_PIPE_CAP_VFLIP | 947 MDP_PIPE_CAP_SCALE | 948 MDP_PIPE_CAP_CSC | 949 MDP_PIPE_CAP_DECIMATION | 950 MDP_PIPE_CAP_SW_PIX_EXT | 951 0, 952 }, 953 .pipe_rgb = { 954 .count = 4, 955 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, 956 .caps = MDP_PIPE_CAP_HFLIP | 957 MDP_PIPE_CAP_VFLIP | 958 MDP_PIPE_CAP_SCALE | 959 MDP_PIPE_CAP_DECIMATION | 960 MDP_PIPE_CAP_SW_PIX_EXT | 961 0, 962 }, 963 .pipe_dma = { 964 .count = 2, /* driver supports max of 2 currently */ 965 .base = { 0x24000, 0x26000, 0x28000, 0x2a000 }, 966 .caps = MDP_PIPE_CAP_HFLIP | 967 MDP_PIPE_CAP_VFLIP | 968 MDP_PIPE_CAP_SW_PIX_EXT | 969 0, 970 }, 971 .pipe_cursor = { 972 .count = 2, 973 .base = { 0x34000, 0x36000 }, 974 .caps = MDP_PIPE_CAP_HFLIP | 975 MDP_PIPE_CAP_VFLIP | 976 MDP_PIPE_CAP_SW_PIX_EXT | 977 MDP_PIPE_CAP_CURSOR | 978 0, 979 }, 980 981 .lm = { 982 .count = 6, 983 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, 984 .instances = { 985 { .id = 0, .pp = 0, .dspp = 0, 986 .caps = MDP_LM_CAP_DISPLAY | 987 MDP_LM_CAP_PAIR, }, 988 { .id = 1, .pp = 1, .dspp = 1, 989 .caps = MDP_LM_CAP_DISPLAY, }, 990 { .id = 2, .pp = 2, .dspp = -1, 991 .caps = MDP_LM_CAP_DISPLAY | 992 MDP_LM_CAP_PAIR, }, 993 { .id = 3, .pp = -1, .dspp = -1, 994 .caps = MDP_LM_CAP_WB, }, 995 { .id = 4, .pp = -1, .dspp = -1, 996 .caps = MDP_LM_CAP_WB, }, 997 { .id = 5, .pp = 3, .dspp = -1, 998 .caps = MDP_LM_CAP_DISPLAY, }, 999 }, 1000 .nb_stages = 8, 1001 .max_width = 2560, 1002 .max_height = 0xFFFF, 1003 }, 1004 .dspp = { 1005 .count = 2, 1006 .base = { 0x54000, 0x56000 }, 1007 }, 1008 .ad = { 1009 .count = 3, 1010 .base = { 0x78000, 0x78800, 0x79000 }, 1011 }, 1012 .pp = { 1013 .count = 4, 1014 .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, 1015 }, 1016 .cdm = { 1017 .count = 1, 1018 .base = { 0x79200 }, 1019 }, 1020 .dsc = { 1021 .count = 2, 1022 .base = { 0x80000, 0x80400 }, 1023 }, 1024 .intf = { 1025 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, 1026 .connect = { 1027 [0] = INTF_eDP, 1028 [1] = INTF_DSI, 1029 [2] = INTF_DSI, 1030 [3] = INTF_HDMI, 1031 }, 1032 }, 1033 .max_clk = 412500000, 1034 }; 1035 1036 static const struct mdp5_cfg_hw sdm630_config = { 1037 .name = "sdm630", 1038 .mdp = { 1039 .count = 1, 1040 .caps = MDP_CAP_CDM | 1041 MDP_CAP_SRC_SPLIT | 1042 0, 1043 }, 1044 .ctl = { 1045 .count = 5, 1046 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, 1047 .flush_hw_mask = 0xf4ffffff, 1048 }, 1049 .pipe_vig = { 1050 .count = 1, 1051 .base = { 0x04000 }, 1052 .caps = MDP_PIPE_CAP_HFLIP | 1053 MDP_PIPE_CAP_VFLIP | 1054 MDP_PIPE_CAP_SCALE | 1055 MDP_PIPE_CAP_CSC | 1056 MDP_PIPE_CAP_DECIMATION | 1057 MDP_PIPE_CAP_SW_PIX_EXT | 1058 0, 1059 }, 1060 .pipe_rgb = { 1061 .count = 4, 1062 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, 1063 .caps = MDP_PIPE_CAP_HFLIP | 1064 MDP_PIPE_CAP_VFLIP | 1065 MDP_PIPE_CAP_SCALE | 1066 MDP_PIPE_CAP_DECIMATION | 1067 MDP_PIPE_CAP_SW_PIX_EXT | 1068 0, 1069 }, 1070 .pipe_dma = { 1071 .count = 2, /* driver supports max of 2 currently */ 1072 .base = { 0x24000, 0x26000, 0x28000 }, 1073 .caps = MDP_PIPE_CAP_HFLIP | 1074 MDP_PIPE_CAP_VFLIP | 1075 MDP_PIPE_CAP_SW_PIX_EXT | 1076 0, 1077 }, 1078 .pipe_cursor = { 1079 .count = 1, 1080 .base = { 0x34000 }, 1081 .caps = MDP_PIPE_CAP_HFLIP | 1082 MDP_PIPE_CAP_VFLIP | 1083 MDP_PIPE_CAP_SW_PIX_EXT | 1084 MDP_PIPE_CAP_CURSOR | 1085 0, 1086 }, 1087 1088 .lm = { 1089 .count = 2, 1090 .base = { 0x44000, 0x46000 }, 1091 .instances = { 1092 { .id = 0, .pp = 0, .dspp = 0, 1093 .caps = MDP_LM_CAP_DISPLAY | 1094 MDP_LM_CAP_PAIR, }, 1095 { .id = 1, .pp = 1, .dspp = -1, 1096 .caps = MDP_LM_CAP_WB, }, 1097 }, 1098 .nb_stages = 8, 1099 .max_width = 2048, 1100 .max_height = 0xFFFF, 1101 }, 1102 .dspp = { 1103 .count = 1, 1104 .base = { 0x54000 }, 1105 }, 1106 .ad = { 1107 .count = 2, 1108 .base = { 0x78000, 0x78800 }, 1109 }, 1110 .pp = { 1111 .count = 3, 1112 .base = { 0x70000, 0x71000, 0x72000 }, 1113 }, 1114 .cdm = { 1115 .count = 1, 1116 .base = { 0x79200 }, 1117 }, 1118 .intf = { 1119 .base = { 0x6a000, 0x6a800 }, 1120 .connect = { 1121 [0] = INTF_DISABLED, 1122 [1] = INTF_DSI, 1123 }, 1124 }, 1125 .max_clk = 412500000, 1126 }; 1127 1128 static const struct mdp5_cfg_hw sdm660_config = { 1129 .name = "sdm660", 1130 .mdp = { 1131 .count = 1, 1132 .caps = MDP_CAP_DSC | 1133 MDP_CAP_CDM | 1134 MDP_CAP_SRC_SPLIT | 1135 0, 1136 }, 1137 .ctl = { 1138 .count = 5, 1139 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, 1140 .flush_hw_mask = 0xf4ffffff, 1141 }, 1142 .pipe_vig = { 1143 .count = 2, 1144 .base = { 0x04000, 0x6000 }, 1145 .caps = MDP_PIPE_CAP_HFLIP | 1146 MDP_PIPE_CAP_VFLIP | 1147 MDP_PIPE_CAP_SCALE | 1148 MDP_PIPE_CAP_CSC | 1149 MDP_PIPE_CAP_DECIMATION | 1150 MDP_PIPE_CAP_SW_PIX_EXT | 1151 0, 1152 }, 1153 .pipe_rgb = { 1154 .count = 4, 1155 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, 1156 .caps = MDP_PIPE_CAP_HFLIP | 1157 MDP_PIPE_CAP_VFLIP | 1158 MDP_PIPE_CAP_SCALE | 1159 MDP_PIPE_CAP_DECIMATION | 1160 MDP_PIPE_CAP_SW_PIX_EXT | 1161 0, 1162 }, 1163 .pipe_dma = { 1164 .count = 2, /* driver supports max of 2 currently */ 1165 .base = { 0x24000, 0x26000, 0x28000 }, 1166 .caps = MDP_PIPE_CAP_HFLIP | 1167 MDP_PIPE_CAP_VFLIP | 1168 MDP_PIPE_CAP_SW_PIX_EXT | 1169 0, 1170 }, 1171 .pipe_cursor = { 1172 .count = 1, 1173 .base = { 0x34000 }, 1174 .caps = MDP_PIPE_CAP_HFLIP | 1175 MDP_PIPE_CAP_VFLIP | 1176 MDP_PIPE_CAP_SW_PIX_EXT | 1177 MDP_PIPE_CAP_CURSOR | 1178 0, 1179 }, 1180 1181 .lm = { 1182 .count = 4, 1183 .base = { 0x44000, 0x45000, 0x46000, 0x49000 }, 1184 .instances = { 1185 { .id = 0, .pp = 0, .dspp = 0, 1186 .caps = MDP_LM_CAP_DISPLAY | 1187 MDP_LM_CAP_PAIR, }, 1188 { .id = 1, .pp = 1, .dspp = 1, 1189 .caps = MDP_LM_CAP_DISPLAY, }, 1190 { .id = 2, .pp = 2, .dspp = -1, 1191 .caps = MDP_LM_CAP_DISPLAY | 1192 MDP_LM_CAP_PAIR, }, 1193 { .id = 3, .pp = 3, .dspp = -1, 1194 .caps = MDP_LM_CAP_WB, }, 1195 }, 1196 .nb_stages = 8, 1197 .max_width = 2560, 1198 .max_height = 0xFFFF, 1199 }, 1200 .dspp = { 1201 .count = 2, 1202 .base = { 0x54000, 0x56000 }, 1203 }, 1204 .ad = { 1205 .count = 2, 1206 .base = { 0x78000, 0x78800 }, 1207 }, 1208 .pp = { 1209 .count = 5, 1210 .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 }, 1211 }, 1212 .cdm = { 1213 .count = 1, 1214 .base = { 0x79200 }, 1215 }, 1216 .dsc = { 1217 .count = 2, 1218 .base = { 0x80000, 0x80400 }, 1219 }, 1220 .intf = { 1221 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 }, 1222 .connect = { 1223 [0] = INTF_DISABLED, 1224 [1] = INTF_DSI, 1225 [2] = INTF_DSI, 1226 [3] = INTF_HDMI, 1227 }, 1228 }, 1229 .max_clk = 412500000, 1230 }; 1231 1232 static const struct mdp5_cfg_handler cfg_handlers_v1[] = { 1233 { .revision = 0, .config = { .hw = &msm8x74v1_config } }, 1234 { .revision = 2, .config = { .hw = &msm8x74v2_config } }, 1235 { .revision = 3, .config = { .hw = &apq8084_config } }, 1236 { .revision = 6, .config = { .hw = &msm8x16_config } }, 1237 { .revision = 8, .config = { .hw = &msm8x36_config } }, 1238 { .revision = 9, .config = { .hw = &msm8x94_config } }, 1239 { .revision = 7, .config = { .hw = &msm8x96_config } }, 1240 { .revision = 11, .config = { .hw = &msm8x76_config } }, 1241 { .revision = 15, .config = { .hw = &msm8917_config } }, 1242 { .revision = 16, .config = { .hw = &msm8x53_config } }, 1243 }; 1244 1245 static const struct mdp5_cfg_handler cfg_handlers_v3[] = { 1246 { .revision = 0, .config = { .hw = &msm8998_config } }, 1247 { .revision = 2, .config = { .hw = &sdm660_config } }, 1248 { .revision = 3, .config = { .hw = &sdm630_config } }, 1249 }; 1250 1251 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev); 1252 1253 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler) 1254 { 1255 return cfg_handler->config.hw; 1256 } 1257 1258 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler) 1259 { 1260 return &cfg_handler->config; 1261 } 1262 1263 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler) 1264 { 1265 return cfg_handler->revision; 1266 } 1267 1268 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler) 1269 { 1270 kfree(cfg_handler); 1271 } 1272 1273 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms, 1274 uint32_t major, uint32_t minor) 1275 { 1276 struct drm_device *dev = mdp5_kms->dev; 1277 struct platform_device *pdev = to_platform_device(dev->dev); 1278 struct mdp5_cfg_handler *cfg_handler; 1279 const struct mdp5_cfg_handler *cfg_handlers; 1280 struct mdp5_cfg_platform *pconfig; 1281 int i, ret = 0, num_handlers; 1282 1283 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL); 1284 if (unlikely(!cfg_handler)) { 1285 ret = -ENOMEM; 1286 goto fail; 1287 } 1288 1289 switch (major) { 1290 case 1: 1291 cfg_handlers = cfg_handlers_v1; 1292 num_handlers = ARRAY_SIZE(cfg_handlers_v1); 1293 break; 1294 case 3: 1295 cfg_handlers = cfg_handlers_v3; 1296 num_handlers = ARRAY_SIZE(cfg_handlers_v3); 1297 break; 1298 default: 1299 DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n", 1300 major, minor); 1301 ret = -ENXIO; 1302 goto fail; 1303 } 1304 1305 /* only after mdp5_cfg global pointer's init can we access the hw */ 1306 for (i = 0; i < num_handlers; i++) { 1307 if (cfg_handlers[i].revision != minor) 1308 continue; 1309 mdp5_cfg = cfg_handlers[i].config.hw; 1310 1311 break; 1312 } 1313 if (unlikely(!mdp5_cfg)) { 1314 DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n", 1315 major, minor); 1316 ret = -ENXIO; 1317 goto fail; 1318 } 1319 1320 cfg_handler->revision = minor; 1321 cfg_handler->config.hw = mdp5_cfg; 1322 1323 pconfig = mdp5_get_config(pdev); 1324 memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig)); 1325 1326 DBG("MDP5: %s hw config selected", mdp5_cfg->name); 1327 1328 return cfg_handler; 1329 1330 fail: 1331 if (cfg_handler) 1332 mdp5_cfg_destroy(cfg_handler); 1333 1334 return ERR_PTR(ret); 1335 } 1336 1337 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev) 1338 { 1339 static struct mdp5_cfg_platform config = {}; 1340 1341 config.iommu = iommu_domain_alloc(&platform_bus_type); 1342 1343 return &config; 1344 } 1345