1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #include <linux/delay.h>
8 
9 #include <drm/drm_vblank.h>
10 
11 #include "msm_drv.h"
12 #include "msm_gem.h"
13 #include "msm_mmu.h"
14 #include "mdp4_kms.h"
15 
16 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
17 
18 static int mdp4_hw_init(struct msm_kms *kms)
19 {
20 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
21 	struct drm_device *dev = mdp4_kms->dev;
22 	uint32_t version, major, minor, dmap_cfg, vg_cfg;
23 	unsigned long clk;
24 	int ret = 0;
25 
26 	pm_runtime_get_sync(dev->dev);
27 
28 	mdp4_enable(mdp4_kms);
29 	version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
30 	mdp4_disable(mdp4_kms);
31 
32 	major = FIELD(version, MDP4_VERSION_MAJOR);
33 	minor = FIELD(version, MDP4_VERSION_MINOR);
34 
35 	DBG("found MDP4 version v%d.%d", major, minor);
36 
37 	if (major != 4) {
38 		DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
39 				major, minor);
40 		ret = -ENXIO;
41 		goto out;
42 	}
43 
44 	mdp4_kms->rev = minor;
45 
46 	if (mdp4_kms->rev > 1) {
47 		mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
48 		mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
49 	}
50 
51 	mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
52 
53 	/* max read pending cmd config, 3 pending requests: */
54 	mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
55 
56 	clk = clk_get_rate(mdp4_kms->clk);
57 
58 	if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
59 		dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
60 		vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
61 	} else {
62 		dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
63 		vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
64 	}
65 
66 	DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
67 
68 	mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
69 	mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
70 
71 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
72 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
73 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
74 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
75 
76 	if (mdp4_kms->rev >= 2)
77 		mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
78 	mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
79 
80 	/* disable CSC matrix / YUV by default: */
81 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
82 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
83 	mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
84 	mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
85 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
86 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
87 
88 	if (mdp4_kms->rev > 1)
89 		mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
90 
91 out:
92 	pm_runtime_put_sync(dev->dev);
93 
94 	return ret;
95 }
96 
97 static void mdp4_enable_commit(struct msm_kms *kms)
98 {
99 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
100 	mdp4_enable(mdp4_kms);
101 }
102 
103 static void mdp4_disable_commit(struct msm_kms *kms)
104 {
105 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
106 	mdp4_disable(mdp4_kms);
107 }
108 
109 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
110 {
111 	int i;
112 	struct drm_crtc *crtc;
113 	struct drm_crtc_state *crtc_state;
114 
115 	/* see 119ecb7fd */
116 	for_each_new_crtc_in_state(state, crtc, crtc_state, i)
117 		drm_crtc_vblank_get(crtc);
118 }
119 
120 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
121 {
122 	/* TODO */
123 }
124 
125 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
126 {
127 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
128 	struct drm_crtc *crtc;
129 
130 	for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
131 		mdp4_crtc_wait_for_commit_done(crtc);
132 }
133 
134 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
135 {
136 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
137 	struct drm_crtc *crtc;
138 
139 	/* see 119ecb7fd */
140 	for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
141 		drm_crtc_vblank_put(crtc);
142 }
143 
144 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
145 		struct drm_encoder *encoder)
146 {
147 	/* if we had >1 encoder, we'd need something more clever: */
148 	switch (encoder->encoder_type) {
149 	case DRM_MODE_ENCODER_TMDS:
150 		return mdp4_dtv_round_pixclk(encoder, rate);
151 	case DRM_MODE_ENCODER_LVDS:
152 	case DRM_MODE_ENCODER_DSI:
153 	default:
154 		return rate;
155 	}
156 }
157 
158 static void mdp4_destroy(struct msm_kms *kms)
159 {
160 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
161 	struct device *dev = mdp4_kms->dev->dev;
162 	struct msm_gem_address_space *aspace = kms->aspace;
163 
164 	if (mdp4_kms->blank_cursor_iova)
165 		msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
166 	drm_gem_object_put(mdp4_kms->blank_cursor_bo);
167 
168 	if (aspace) {
169 		aspace->mmu->funcs->detach(aspace->mmu);
170 		msm_gem_address_space_put(aspace);
171 	}
172 
173 	if (mdp4_kms->rpm_enabled)
174 		pm_runtime_disable(dev);
175 
176 	mdp_kms_destroy(&mdp4_kms->base);
177 
178 	kfree(mdp4_kms);
179 }
180 
181 static const struct mdp_kms_funcs kms_funcs = {
182 	.base = {
183 		.hw_init         = mdp4_hw_init,
184 		.irq_preinstall  = mdp4_irq_preinstall,
185 		.irq_postinstall = mdp4_irq_postinstall,
186 		.irq_uninstall   = mdp4_irq_uninstall,
187 		.irq             = mdp4_irq,
188 		.enable_vblank   = mdp4_enable_vblank,
189 		.disable_vblank  = mdp4_disable_vblank,
190 		.enable_commit   = mdp4_enable_commit,
191 		.disable_commit  = mdp4_disable_commit,
192 		.prepare_commit  = mdp4_prepare_commit,
193 		.flush_commit    = mdp4_flush_commit,
194 		.wait_flush      = mdp4_wait_flush,
195 		.complete_commit = mdp4_complete_commit,
196 		.get_format      = mdp_get_format,
197 		.round_pixclk    = mdp4_round_pixclk,
198 		.destroy         = mdp4_destroy,
199 	},
200 	.set_irqmask         = mdp4_set_irqmask,
201 };
202 
203 int mdp4_disable(struct mdp4_kms *mdp4_kms)
204 {
205 	DBG("");
206 
207 	clk_disable_unprepare(mdp4_kms->clk);
208 	if (mdp4_kms->pclk)
209 		clk_disable_unprepare(mdp4_kms->pclk);
210 	if (mdp4_kms->lut_clk)
211 		clk_disable_unprepare(mdp4_kms->lut_clk);
212 	if (mdp4_kms->axi_clk)
213 		clk_disable_unprepare(mdp4_kms->axi_clk);
214 
215 	return 0;
216 }
217 
218 int mdp4_enable(struct mdp4_kms *mdp4_kms)
219 {
220 	DBG("");
221 
222 	clk_prepare_enable(mdp4_kms->clk);
223 	if (mdp4_kms->pclk)
224 		clk_prepare_enable(mdp4_kms->pclk);
225 	if (mdp4_kms->lut_clk)
226 		clk_prepare_enable(mdp4_kms->lut_clk);
227 	if (mdp4_kms->axi_clk)
228 		clk_prepare_enable(mdp4_kms->axi_clk);
229 
230 	return 0;
231 }
232 
233 
234 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
235 				  int intf_type)
236 {
237 	struct drm_device *dev = mdp4_kms->dev;
238 	struct msm_drm_private *priv = dev->dev_private;
239 	struct drm_encoder *encoder;
240 	struct drm_connector *connector;
241 	struct device_node *panel_node;
242 	int dsi_id;
243 	int ret;
244 
245 	switch (intf_type) {
246 	case DRM_MODE_ENCODER_LVDS:
247 		/*
248 		 * bail out early if there is no panel node (no need to
249 		 * initialize LCDC encoder and LVDS connector)
250 		 */
251 		panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
252 		if (!panel_node)
253 			return 0;
254 
255 		encoder = mdp4_lcdc_encoder_init(dev, panel_node);
256 		if (IS_ERR(encoder)) {
257 			DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
258 			return PTR_ERR(encoder);
259 		}
260 
261 		/* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
262 		encoder->possible_crtcs = 1 << DMA_P;
263 
264 		connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
265 		if (IS_ERR(connector)) {
266 			DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
267 			return PTR_ERR(connector);
268 		}
269 
270 		priv->encoders[priv->num_encoders++] = encoder;
271 		priv->connectors[priv->num_connectors++] = connector;
272 
273 		break;
274 	case DRM_MODE_ENCODER_TMDS:
275 		encoder = mdp4_dtv_encoder_init(dev);
276 		if (IS_ERR(encoder)) {
277 			DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
278 			return PTR_ERR(encoder);
279 		}
280 
281 		/* DTV can be hooked to DMA_E: */
282 		encoder->possible_crtcs = 1 << 1;
283 
284 		if (priv->hdmi) {
285 			/* Construct bridge/connector for HDMI: */
286 			ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
287 			if (ret) {
288 				DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
289 				return ret;
290 			}
291 		}
292 
293 		priv->encoders[priv->num_encoders++] = encoder;
294 
295 		break;
296 	case DRM_MODE_ENCODER_DSI:
297 		/* only DSI1 supported for now */
298 		dsi_id = 0;
299 
300 		if (!priv->dsi[dsi_id])
301 			break;
302 
303 		encoder = mdp4_dsi_encoder_init(dev);
304 		if (IS_ERR(encoder)) {
305 			ret = PTR_ERR(encoder);
306 			DRM_DEV_ERROR(dev->dev,
307 				"failed to construct DSI encoder: %d\n", ret);
308 			return ret;
309 		}
310 
311 		/* TODO: Add DMA_S later? */
312 		encoder->possible_crtcs = 1 << DMA_P;
313 		priv->encoders[priv->num_encoders++] = encoder;
314 
315 		ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
316 		if (ret) {
317 			DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
318 				ret);
319 			return ret;
320 		}
321 
322 		break;
323 	default:
324 		DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
325 		return -EINVAL;
326 	}
327 
328 	return 0;
329 }
330 
331 static int modeset_init(struct mdp4_kms *mdp4_kms)
332 {
333 	struct drm_device *dev = mdp4_kms->dev;
334 	struct msm_drm_private *priv = dev->dev_private;
335 	struct drm_plane *plane;
336 	struct drm_crtc *crtc;
337 	int i, ret;
338 	static const enum mdp4_pipe rgb_planes[] = {
339 		RGB1, RGB2,
340 	};
341 	static const enum mdp4_pipe vg_planes[] = {
342 		VG1, VG2,
343 	};
344 	static const enum mdp4_dma mdp4_crtcs[] = {
345 		DMA_P, DMA_E,
346 	};
347 	static const char * const mdp4_crtc_names[] = {
348 		"DMA_P", "DMA_E",
349 	};
350 	static const int mdp4_intfs[] = {
351 		DRM_MODE_ENCODER_LVDS,
352 		DRM_MODE_ENCODER_DSI,
353 		DRM_MODE_ENCODER_TMDS,
354 	};
355 
356 	/* construct non-private planes: */
357 	for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
358 		plane = mdp4_plane_init(dev, vg_planes[i], false);
359 		if (IS_ERR(plane)) {
360 			DRM_DEV_ERROR(dev->dev,
361 				"failed to construct plane for VG%d\n", i + 1);
362 			ret = PTR_ERR(plane);
363 			goto fail;
364 		}
365 		priv->planes[priv->num_planes++] = plane;
366 	}
367 
368 	for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
369 		plane = mdp4_plane_init(dev, rgb_planes[i], true);
370 		if (IS_ERR(plane)) {
371 			DRM_DEV_ERROR(dev->dev,
372 				"failed to construct plane for RGB%d\n", i + 1);
373 			ret = PTR_ERR(plane);
374 			goto fail;
375 		}
376 
377 		crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
378 				mdp4_crtcs[i]);
379 		if (IS_ERR(crtc)) {
380 			DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
381 				mdp4_crtc_names[i]);
382 			ret = PTR_ERR(crtc);
383 			goto fail;
384 		}
385 
386 		priv->crtcs[priv->num_crtcs++] = crtc;
387 	}
388 
389 	/*
390 	 * we currently set up two relatively fixed paths:
391 	 *
392 	 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
393 	 *			or
394 	 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
395 	 *
396 	 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
397 	 */
398 
399 	for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
400 		ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
401 		if (ret) {
402 			DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
403 				i, ret);
404 			goto fail;
405 		}
406 	}
407 
408 	return 0;
409 
410 fail:
411 	return ret;
412 }
413 
414 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
415 {
416 	struct platform_device *pdev = to_platform_device(dev->dev);
417 	struct mdp4_platform_config *config = mdp4_get_config(pdev);
418 	struct mdp4_kms *mdp4_kms;
419 	struct msm_kms *kms = NULL;
420 	struct msm_gem_address_space *aspace;
421 	int irq, ret;
422 
423 	mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
424 	if (!mdp4_kms) {
425 		DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n");
426 		ret = -ENOMEM;
427 		goto fail;
428 	}
429 
430 	ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
431 	if (ret) {
432 		DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
433 		goto fail;
434 	}
435 
436 	kms = &mdp4_kms->base.base;
437 
438 	mdp4_kms->dev = dev;
439 
440 	mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
441 	if (IS_ERR(mdp4_kms->mmio)) {
442 		ret = PTR_ERR(mdp4_kms->mmio);
443 		goto fail;
444 	}
445 
446 	irq = platform_get_irq(pdev, 0);
447 	if (irq < 0) {
448 		ret = irq;
449 		DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
450 		goto fail;
451 	}
452 
453 	kms->irq = irq;
454 
455 	/* NOTE: driver for this regulator still missing upstream.. use
456 	 * _get_exclusive() and ignore the error if it does not exist
457 	 * (and hope that the bootloader left it on for us)
458 	 */
459 	mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
460 	if (IS_ERR(mdp4_kms->vdd))
461 		mdp4_kms->vdd = NULL;
462 
463 	if (mdp4_kms->vdd) {
464 		ret = regulator_enable(mdp4_kms->vdd);
465 		if (ret) {
466 			DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
467 			goto fail;
468 		}
469 	}
470 
471 	mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
472 	if (IS_ERR(mdp4_kms->clk)) {
473 		DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n");
474 		ret = PTR_ERR(mdp4_kms->clk);
475 		goto fail;
476 	}
477 
478 	mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
479 	if (IS_ERR(mdp4_kms->pclk))
480 		mdp4_kms->pclk = NULL;
481 
482 	if (mdp4_kms->rev >= 2) {
483 		mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
484 		if (IS_ERR(mdp4_kms->lut_clk)) {
485 			DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
486 			ret = PTR_ERR(mdp4_kms->lut_clk);
487 			goto fail;
488 		}
489 	}
490 
491 	mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
492 	if (IS_ERR(mdp4_kms->axi_clk)) {
493 		DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n");
494 		ret = PTR_ERR(mdp4_kms->axi_clk);
495 		goto fail;
496 	}
497 
498 	clk_set_rate(mdp4_kms->clk, config->max_clk);
499 	if (mdp4_kms->lut_clk)
500 		clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
501 
502 	pm_runtime_enable(dev->dev);
503 	mdp4_kms->rpm_enabled = true;
504 
505 	/* make sure things are off before attaching iommu (bootloader could
506 	 * have left things on, in which case we'll start getting faults if
507 	 * we don't disable):
508 	 */
509 	mdp4_enable(mdp4_kms);
510 	mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
511 	mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
512 	mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
513 	mdp4_disable(mdp4_kms);
514 	mdelay(16);
515 
516 	if (config->iommu) {
517 		struct msm_mmu *mmu = msm_iommu_new(&pdev->dev,
518 			config->iommu);
519 
520 		aspace  = msm_gem_address_space_create(mmu,
521 			"mdp4", 0x1000, 0x100000000 - 0x1000);
522 
523 		if (IS_ERR(aspace)) {
524 			if (!IS_ERR(mmu))
525 				mmu->funcs->destroy(mmu);
526 			ret = PTR_ERR(aspace);
527 			goto fail;
528 		}
529 
530 		kms->aspace = aspace;
531 	} else {
532 		DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
533 				"contig buffers for scanout\n");
534 		aspace = NULL;
535 	}
536 
537 	ret = modeset_init(mdp4_kms);
538 	if (ret) {
539 		DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
540 		goto fail;
541 	}
542 
543 	mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
544 	if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
545 		ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
546 		DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
547 		mdp4_kms->blank_cursor_bo = NULL;
548 		goto fail;
549 	}
550 
551 	ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
552 			&mdp4_kms->blank_cursor_iova);
553 	if (ret) {
554 		DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
555 		goto fail;
556 	}
557 
558 	dev->mode_config.min_width = 0;
559 	dev->mode_config.min_height = 0;
560 	dev->mode_config.max_width = 2048;
561 	dev->mode_config.max_height = 2048;
562 
563 	return kms;
564 
565 fail:
566 	if (kms)
567 		mdp4_destroy(kms);
568 	return ERR_PTR(ret);
569 }
570 
571 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
572 {
573 	static struct mdp4_platform_config config = {};
574 
575 	/* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
576 	config.max_clk = 266667000;
577 	config.iommu = iommu_domain_alloc(&platform_bus_type);
578 
579 	return &config;
580 }
581