1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #include <linux/delay.h>
8 
9 #include <drm/drm_vblank.h>
10 
11 #include "msm_drv.h"
12 #include "msm_gem.h"
13 #include "msm_mmu.h"
14 #include "mdp4_kms.h"
15 
16 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
17 
18 static int mdp4_hw_init(struct msm_kms *kms)
19 {
20 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
21 	struct drm_device *dev = mdp4_kms->dev;
22 	u32 dmap_cfg, vg_cfg;
23 	unsigned long clk;
24 	int ret = 0;
25 
26 	pm_runtime_get_sync(dev->dev);
27 
28 	if (mdp4_kms->rev > 1) {
29 		mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
30 		mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
31 	}
32 
33 	mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
34 
35 	/* max read pending cmd config, 3 pending requests: */
36 	mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
37 
38 	clk = clk_get_rate(mdp4_kms->clk);
39 
40 	if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
41 		dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
42 		vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
43 	} else {
44 		dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
45 		vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
46 	}
47 
48 	DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
49 
50 	mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
51 	mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
52 
53 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
54 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
55 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
56 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
57 
58 	if (mdp4_kms->rev >= 2)
59 		mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
60 	mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
61 
62 	/* disable CSC matrix / YUV by default: */
63 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
64 	mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
65 	mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
66 	mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
67 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
68 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
69 
70 	if (mdp4_kms->rev > 1)
71 		mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
72 
73 	pm_runtime_put_sync(dev->dev);
74 
75 	return ret;
76 }
77 
78 static void mdp4_enable_commit(struct msm_kms *kms)
79 {
80 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
81 	mdp4_enable(mdp4_kms);
82 }
83 
84 static void mdp4_disable_commit(struct msm_kms *kms)
85 {
86 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
87 	mdp4_disable(mdp4_kms);
88 }
89 
90 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
91 {
92 }
93 
94 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
95 {
96 	/* TODO */
97 }
98 
99 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
100 {
101 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
102 	struct drm_crtc *crtc;
103 
104 	for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
105 		mdp4_crtc_wait_for_commit_done(crtc);
106 }
107 
108 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
109 {
110 }
111 
112 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
113 		struct drm_encoder *encoder)
114 {
115 	/* if we had >1 encoder, we'd need something more clever: */
116 	switch (encoder->encoder_type) {
117 	case DRM_MODE_ENCODER_TMDS:
118 		return mdp4_dtv_round_pixclk(encoder, rate);
119 	case DRM_MODE_ENCODER_LVDS:
120 	case DRM_MODE_ENCODER_DSI:
121 	default:
122 		return rate;
123 	}
124 }
125 
126 static void mdp4_destroy(struct msm_kms *kms)
127 {
128 	struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
129 	struct device *dev = mdp4_kms->dev->dev;
130 	struct msm_gem_address_space *aspace = kms->aspace;
131 
132 	if (mdp4_kms->blank_cursor_iova)
133 		msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
134 	drm_gem_object_put(mdp4_kms->blank_cursor_bo);
135 
136 	if (aspace) {
137 		aspace->mmu->funcs->detach(aspace->mmu);
138 		msm_gem_address_space_put(aspace);
139 	}
140 
141 	if (mdp4_kms->rpm_enabled)
142 		pm_runtime_disable(dev);
143 
144 	mdp_kms_destroy(&mdp4_kms->base);
145 
146 	kfree(mdp4_kms);
147 }
148 
149 static const struct mdp_kms_funcs kms_funcs = {
150 	.base = {
151 		.hw_init         = mdp4_hw_init,
152 		.irq_preinstall  = mdp4_irq_preinstall,
153 		.irq_postinstall = mdp4_irq_postinstall,
154 		.irq_uninstall   = mdp4_irq_uninstall,
155 		.irq             = mdp4_irq,
156 		.enable_vblank   = mdp4_enable_vblank,
157 		.disable_vblank  = mdp4_disable_vblank,
158 		.enable_commit   = mdp4_enable_commit,
159 		.disable_commit  = mdp4_disable_commit,
160 		.prepare_commit  = mdp4_prepare_commit,
161 		.flush_commit    = mdp4_flush_commit,
162 		.wait_flush      = mdp4_wait_flush,
163 		.complete_commit = mdp4_complete_commit,
164 		.get_format      = mdp_get_format,
165 		.round_pixclk    = mdp4_round_pixclk,
166 		.destroy         = mdp4_destroy,
167 	},
168 	.set_irqmask         = mdp4_set_irqmask,
169 };
170 
171 int mdp4_disable(struct mdp4_kms *mdp4_kms)
172 {
173 	DBG("");
174 
175 	clk_disable_unprepare(mdp4_kms->clk);
176 	clk_disable_unprepare(mdp4_kms->pclk);
177 	clk_disable_unprepare(mdp4_kms->lut_clk);
178 	clk_disable_unprepare(mdp4_kms->axi_clk);
179 
180 	return 0;
181 }
182 
183 int mdp4_enable(struct mdp4_kms *mdp4_kms)
184 {
185 	DBG("");
186 
187 	clk_prepare_enable(mdp4_kms->clk);
188 	clk_prepare_enable(mdp4_kms->pclk);
189 	clk_prepare_enable(mdp4_kms->lut_clk);
190 	clk_prepare_enable(mdp4_kms->axi_clk);
191 
192 	return 0;
193 }
194 
195 
196 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
197 				  int intf_type)
198 {
199 	struct drm_device *dev = mdp4_kms->dev;
200 	struct msm_drm_private *priv = dev->dev_private;
201 	struct drm_encoder *encoder;
202 	struct drm_connector *connector;
203 	struct device_node *panel_node;
204 	int dsi_id;
205 	int ret;
206 
207 	switch (intf_type) {
208 	case DRM_MODE_ENCODER_LVDS:
209 		/*
210 		 * bail out early if there is no panel node (no need to
211 		 * initialize LCDC encoder and LVDS connector)
212 		 */
213 		panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
214 		if (!panel_node)
215 			return 0;
216 
217 		encoder = mdp4_lcdc_encoder_init(dev, panel_node);
218 		if (IS_ERR(encoder)) {
219 			DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
220 			return PTR_ERR(encoder);
221 		}
222 
223 		/* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
224 		encoder->possible_crtcs = 1 << DMA_P;
225 
226 		connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
227 		if (IS_ERR(connector)) {
228 			DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
229 			return PTR_ERR(connector);
230 		}
231 
232 		priv->encoders[priv->num_encoders++] = encoder;
233 		priv->connectors[priv->num_connectors++] = connector;
234 
235 		break;
236 	case DRM_MODE_ENCODER_TMDS:
237 		encoder = mdp4_dtv_encoder_init(dev);
238 		if (IS_ERR(encoder)) {
239 			DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
240 			return PTR_ERR(encoder);
241 		}
242 
243 		/* DTV can be hooked to DMA_E: */
244 		encoder->possible_crtcs = 1 << 1;
245 
246 		if (priv->hdmi) {
247 			/* Construct bridge/connector for HDMI: */
248 			ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
249 			if (ret) {
250 				DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
251 				return ret;
252 			}
253 		}
254 
255 		priv->encoders[priv->num_encoders++] = encoder;
256 
257 		break;
258 	case DRM_MODE_ENCODER_DSI:
259 		/* only DSI1 supported for now */
260 		dsi_id = 0;
261 
262 		if (!priv->dsi[dsi_id])
263 			break;
264 
265 		encoder = mdp4_dsi_encoder_init(dev);
266 		if (IS_ERR(encoder)) {
267 			ret = PTR_ERR(encoder);
268 			DRM_DEV_ERROR(dev->dev,
269 				"failed to construct DSI encoder: %d\n", ret);
270 			return ret;
271 		}
272 
273 		/* TODO: Add DMA_S later? */
274 		encoder->possible_crtcs = 1 << DMA_P;
275 		priv->encoders[priv->num_encoders++] = encoder;
276 
277 		ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
278 		if (ret) {
279 			DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
280 				ret);
281 			return ret;
282 		}
283 
284 		break;
285 	default:
286 		DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
287 		return -EINVAL;
288 	}
289 
290 	return 0;
291 }
292 
293 static int modeset_init(struct mdp4_kms *mdp4_kms)
294 {
295 	struct drm_device *dev = mdp4_kms->dev;
296 	struct msm_drm_private *priv = dev->dev_private;
297 	struct drm_plane *plane;
298 	struct drm_crtc *crtc;
299 	int i, ret;
300 	static const enum mdp4_pipe rgb_planes[] = {
301 		RGB1, RGB2,
302 	};
303 	static const enum mdp4_pipe vg_planes[] = {
304 		VG1, VG2,
305 	};
306 	static const enum mdp4_dma mdp4_crtcs[] = {
307 		DMA_P, DMA_E,
308 	};
309 	static const char * const mdp4_crtc_names[] = {
310 		"DMA_P", "DMA_E",
311 	};
312 	static const int mdp4_intfs[] = {
313 		DRM_MODE_ENCODER_LVDS,
314 		DRM_MODE_ENCODER_DSI,
315 		DRM_MODE_ENCODER_TMDS,
316 	};
317 
318 	/* construct non-private planes: */
319 	for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
320 		plane = mdp4_plane_init(dev, vg_planes[i], false);
321 		if (IS_ERR(plane)) {
322 			DRM_DEV_ERROR(dev->dev,
323 				"failed to construct plane for VG%d\n", i + 1);
324 			ret = PTR_ERR(plane);
325 			goto fail;
326 		}
327 		priv->planes[priv->num_planes++] = plane;
328 	}
329 
330 	for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
331 		plane = mdp4_plane_init(dev, rgb_planes[i], true);
332 		if (IS_ERR(plane)) {
333 			DRM_DEV_ERROR(dev->dev,
334 				"failed to construct plane for RGB%d\n", i + 1);
335 			ret = PTR_ERR(plane);
336 			goto fail;
337 		}
338 
339 		crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
340 				mdp4_crtcs[i]);
341 		if (IS_ERR(crtc)) {
342 			DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
343 				mdp4_crtc_names[i]);
344 			ret = PTR_ERR(crtc);
345 			goto fail;
346 		}
347 
348 		priv->crtcs[priv->num_crtcs++] = crtc;
349 	}
350 
351 	/*
352 	 * we currently set up two relatively fixed paths:
353 	 *
354 	 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
355 	 *			or
356 	 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
357 	 *
358 	 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
359 	 */
360 
361 	for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
362 		ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
363 		if (ret) {
364 			DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
365 				i, ret);
366 			goto fail;
367 		}
368 	}
369 
370 	return 0;
371 
372 fail:
373 	return ret;
374 }
375 
376 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
377 				 u32 *major, u32 *minor)
378 {
379 	struct drm_device *dev = mdp4_kms->dev;
380 	u32 version;
381 
382 	mdp4_enable(mdp4_kms);
383 	version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
384 	mdp4_disable(mdp4_kms);
385 
386 	*major = FIELD(version, MDP4_VERSION_MAJOR);
387 	*minor = FIELD(version, MDP4_VERSION_MINOR);
388 
389 	DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
390 }
391 
392 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
393 {
394 	struct platform_device *pdev = to_platform_device(dev->dev);
395 	struct mdp4_platform_config *config = mdp4_get_config(pdev);
396 	struct msm_drm_private *priv = dev->dev_private;
397 	struct mdp4_kms *mdp4_kms;
398 	struct msm_kms *kms = NULL;
399 	struct msm_gem_address_space *aspace;
400 	int irq, ret;
401 	u32 major, minor;
402 
403 	mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
404 	if (!mdp4_kms) {
405 		DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n");
406 		ret = -ENOMEM;
407 		goto fail;
408 	}
409 
410 	ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
411 	if (ret) {
412 		DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
413 		goto fail;
414 	}
415 
416 	priv->kms = &mdp4_kms->base.base;
417 	kms = priv->kms;
418 
419 	mdp4_kms->dev = dev;
420 
421 	mdp4_kms->mmio = msm_ioremap(pdev, NULL);
422 	if (IS_ERR(mdp4_kms->mmio)) {
423 		ret = PTR_ERR(mdp4_kms->mmio);
424 		goto fail;
425 	}
426 
427 	irq = platform_get_irq(pdev, 0);
428 	if (irq < 0) {
429 		ret = irq;
430 		DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
431 		goto fail;
432 	}
433 
434 	kms->irq = irq;
435 
436 	/* NOTE: driver for this regulator still missing upstream.. use
437 	 * _get_exclusive() and ignore the error if it does not exist
438 	 * (and hope that the bootloader left it on for us)
439 	 */
440 	mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
441 	if (IS_ERR(mdp4_kms->vdd))
442 		mdp4_kms->vdd = NULL;
443 
444 	if (mdp4_kms->vdd) {
445 		ret = regulator_enable(mdp4_kms->vdd);
446 		if (ret) {
447 			DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
448 			goto fail;
449 		}
450 	}
451 
452 	mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
453 	if (IS_ERR(mdp4_kms->clk)) {
454 		DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n");
455 		ret = PTR_ERR(mdp4_kms->clk);
456 		goto fail;
457 	}
458 
459 	mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
460 	if (IS_ERR(mdp4_kms->pclk))
461 		mdp4_kms->pclk = NULL;
462 
463 	mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
464 	if (IS_ERR(mdp4_kms->axi_clk)) {
465 		DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n");
466 		ret = PTR_ERR(mdp4_kms->axi_clk);
467 		goto fail;
468 	}
469 
470 	clk_set_rate(mdp4_kms->clk, config->max_clk);
471 
472 	read_mdp_hw_revision(mdp4_kms, &major, &minor);
473 
474 	if (major != 4) {
475 		DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
476 			      major, minor);
477 		ret = -ENXIO;
478 		goto fail;
479 	}
480 
481 	mdp4_kms->rev = minor;
482 
483 	if (mdp4_kms->rev >= 2) {
484 		mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
485 		if (IS_ERR(mdp4_kms->lut_clk)) {
486 			DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
487 			ret = PTR_ERR(mdp4_kms->lut_clk);
488 			goto fail;
489 		}
490 		clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
491 	}
492 
493 	pm_runtime_enable(dev->dev);
494 	mdp4_kms->rpm_enabled = true;
495 
496 	/* make sure things are off before attaching iommu (bootloader could
497 	 * have left things on, in which case we'll start getting faults if
498 	 * we don't disable):
499 	 */
500 	mdp4_enable(mdp4_kms);
501 	mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
502 	mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
503 	mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
504 	mdp4_disable(mdp4_kms);
505 	mdelay(16);
506 
507 	if (config->iommu) {
508 		struct msm_mmu *mmu = msm_iommu_new(&pdev->dev,
509 			config->iommu);
510 
511 		aspace  = msm_gem_address_space_create(mmu,
512 			"mdp4", 0x1000, 0x100000000 - 0x1000);
513 
514 		if (IS_ERR(aspace)) {
515 			if (!IS_ERR(mmu))
516 				mmu->funcs->destroy(mmu);
517 			ret = PTR_ERR(aspace);
518 			goto fail;
519 		}
520 
521 		kms->aspace = aspace;
522 	} else {
523 		DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
524 				"contig buffers for scanout\n");
525 		aspace = NULL;
526 	}
527 
528 	ret = modeset_init(mdp4_kms);
529 	if (ret) {
530 		DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
531 		goto fail;
532 	}
533 
534 	mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
535 	if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
536 		ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
537 		DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
538 		mdp4_kms->blank_cursor_bo = NULL;
539 		goto fail;
540 	}
541 
542 	ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
543 			&mdp4_kms->blank_cursor_iova);
544 	if (ret) {
545 		DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
546 		goto fail;
547 	}
548 
549 	dev->mode_config.min_width = 0;
550 	dev->mode_config.min_height = 0;
551 	dev->mode_config.max_width = 2048;
552 	dev->mode_config.max_height = 2048;
553 
554 	return kms;
555 
556 fail:
557 	if (kms)
558 		mdp4_destroy(kms);
559 	return ERR_PTR(ret);
560 }
561 
562 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
563 {
564 	static struct mdp4_platform_config config = {};
565 
566 	/* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
567 	config.max_clk = 266667000;
568 	config.iommu = iommu_domain_alloc(&platform_bus_type);
569 
570 	return &config;
571 }
572