1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 8 #include "msm_drv.h" 9 #include "msm_gem.h" 10 #include "msm_mmu.h" 11 #include "mdp4_kms.h" 12 13 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev); 14 15 static int mdp4_hw_init(struct msm_kms *kms) 16 { 17 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 18 struct drm_device *dev = mdp4_kms->dev; 19 uint32_t version, major, minor, dmap_cfg, vg_cfg; 20 unsigned long clk; 21 int ret = 0; 22 23 pm_runtime_get_sync(dev->dev); 24 25 mdp4_enable(mdp4_kms); 26 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); 27 mdp4_disable(mdp4_kms); 28 29 major = FIELD(version, MDP4_VERSION_MAJOR); 30 minor = FIELD(version, MDP4_VERSION_MINOR); 31 32 DBG("found MDP4 version v%d.%d", major, minor); 33 34 if (major != 4) { 35 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n", 36 major, minor); 37 ret = -ENXIO; 38 goto out; 39 } 40 41 mdp4_kms->rev = minor; 42 43 if (mdp4_kms->rev > 1) { 44 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); 45 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); 46 } 47 48 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); 49 50 /* max read pending cmd config, 3 pending requests: */ 51 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); 52 53 clk = clk_get_rate(mdp4_kms->clk); 54 55 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { 56 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */ 57 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */ 58 } else { 59 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */ 60 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */ 61 } 62 63 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg); 64 65 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); 66 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); 67 68 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); 69 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); 70 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); 71 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); 72 73 if (mdp4_kms->rev >= 2) 74 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); 75 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); 76 77 /* disable CSC matrix / YUV by default: */ 78 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); 79 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); 80 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); 81 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); 82 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); 83 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); 84 85 if (mdp4_kms->rev > 1) 86 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); 87 88 dev->mode_config.allow_fb_modifiers = true; 89 90 out: 91 pm_runtime_put_sync(dev->dev); 92 93 return ret; 94 } 95 96 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 97 { 98 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 99 int i; 100 struct drm_crtc *crtc; 101 struct drm_crtc_state *crtc_state; 102 103 mdp4_enable(mdp4_kms); 104 105 /* see 119ecb7fd */ 106 for_each_new_crtc_in_state(state, crtc, crtc_state, i) 107 drm_crtc_vblank_get(crtc); 108 } 109 110 static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) 111 { 112 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 113 int i; 114 struct drm_crtc *crtc; 115 struct drm_crtc_state *crtc_state; 116 117 drm_atomic_helper_wait_for_vblanks(mdp4_kms->dev, state); 118 119 /* see 119ecb7fd */ 120 for_each_new_crtc_in_state(state, crtc, crtc_state, i) 121 drm_crtc_vblank_put(crtc); 122 123 mdp4_disable(mdp4_kms); 124 } 125 126 static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms, 127 struct drm_crtc *crtc) 128 { 129 mdp4_crtc_wait_for_commit_done(crtc); 130 } 131 132 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate, 133 struct drm_encoder *encoder) 134 { 135 /* if we had >1 encoder, we'd need something more clever: */ 136 switch (encoder->encoder_type) { 137 case DRM_MODE_ENCODER_TMDS: 138 return mdp4_dtv_round_pixclk(encoder, rate); 139 case DRM_MODE_ENCODER_LVDS: 140 case DRM_MODE_ENCODER_DSI: 141 default: 142 return rate; 143 } 144 } 145 146 static const char * const iommu_ports[] = { 147 "mdp_port0_cb0", "mdp_port1_cb0", 148 }; 149 150 static void mdp4_destroy(struct msm_kms *kms) 151 { 152 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 153 struct device *dev = mdp4_kms->dev->dev; 154 struct msm_gem_address_space *aspace = kms->aspace; 155 156 if (mdp4_kms->blank_cursor_iova) 157 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace); 158 drm_gem_object_put_unlocked(mdp4_kms->blank_cursor_bo); 159 160 if (aspace) { 161 aspace->mmu->funcs->detach(aspace->mmu, 162 iommu_ports, ARRAY_SIZE(iommu_ports)); 163 msm_gem_address_space_put(aspace); 164 } 165 166 if (mdp4_kms->rpm_enabled) 167 pm_runtime_disable(dev); 168 169 kfree(mdp4_kms); 170 } 171 172 static const struct mdp_kms_funcs kms_funcs = { 173 .base = { 174 .hw_init = mdp4_hw_init, 175 .irq_preinstall = mdp4_irq_preinstall, 176 .irq_postinstall = mdp4_irq_postinstall, 177 .irq_uninstall = mdp4_irq_uninstall, 178 .irq = mdp4_irq, 179 .enable_vblank = mdp4_enable_vblank, 180 .disable_vblank = mdp4_disable_vblank, 181 .prepare_commit = mdp4_prepare_commit, 182 .complete_commit = mdp4_complete_commit, 183 .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done, 184 .get_format = mdp_get_format, 185 .round_pixclk = mdp4_round_pixclk, 186 .destroy = mdp4_destroy, 187 }, 188 .set_irqmask = mdp4_set_irqmask, 189 }; 190 191 int mdp4_disable(struct mdp4_kms *mdp4_kms) 192 { 193 DBG(""); 194 195 clk_disable_unprepare(mdp4_kms->clk); 196 if (mdp4_kms->pclk) 197 clk_disable_unprepare(mdp4_kms->pclk); 198 if (mdp4_kms->lut_clk) 199 clk_disable_unprepare(mdp4_kms->lut_clk); 200 if (mdp4_kms->axi_clk) 201 clk_disable_unprepare(mdp4_kms->axi_clk); 202 203 return 0; 204 } 205 206 int mdp4_enable(struct mdp4_kms *mdp4_kms) 207 { 208 DBG(""); 209 210 clk_prepare_enable(mdp4_kms->clk); 211 if (mdp4_kms->pclk) 212 clk_prepare_enable(mdp4_kms->pclk); 213 if (mdp4_kms->lut_clk) 214 clk_prepare_enable(mdp4_kms->lut_clk); 215 if (mdp4_kms->axi_clk) 216 clk_prepare_enable(mdp4_kms->axi_clk); 217 218 return 0; 219 } 220 221 222 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, 223 int intf_type) 224 { 225 struct drm_device *dev = mdp4_kms->dev; 226 struct msm_drm_private *priv = dev->dev_private; 227 struct drm_encoder *encoder; 228 struct drm_connector *connector; 229 struct device_node *panel_node; 230 int dsi_id; 231 int ret; 232 233 switch (intf_type) { 234 case DRM_MODE_ENCODER_LVDS: 235 /* 236 * bail out early if there is no panel node (no need to 237 * initialize LCDC encoder and LVDS connector) 238 */ 239 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0); 240 if (!panel_node) 241 return 0; 242 243 encoder = mdp4_lcdc_encoder_init(dev, panel_node); 244 if (IS_ERR(encoder)) { 245 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n"); 246 return PTR_ERR(encoder); 247 } 248 249 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */ 250 encoder->possible_crtcs = 1 << DMA_P; 251 252 connector = mdp4_lvds_connector_init(dev, panel_node, encoder); 253 if (IS_ERR(connector)) { 254 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n"); 255 return PTR_ERR(connector); 256 } 257 258 priv->encoders[priv->num_encoders++] = encoder; 259 priv->connectors[priv->num_connectors++] = connector; 260 261 break; 262 case DRM_MODE_ENCODER_TMDS: 263 encoder = mdp4_dtv_encoder_init(dev); 264 if (IS_ERR(encoder)) { 265 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n"); 266 return PTR_ERR(encoder); 267 } 268 269 /* DTV can be hooked to DMA_E: */ 270 encoder->possible_crtcs = 1 << 1; 271 272 if (priv->hdmi) { 273 /* Construct bridge/connector for HDMI: */ 274 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 275 if (ret) { 276 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret); 277 return ret; 278 } 279 } 280 281 priv->encoders[priv->num_encoders++] = encoder; 282 283 break; 284 case DRM_MODE_ENCODER_DSI: 285 /* only DSI1 supported for now */ 286 dsi_id = 0; 287 288 if (!priv->dsi[dsi_id]) 289 break; 290 291 encoder = mdp4_dsi_encoder_init(dev); 292 if (IS_ERR(encoder)) { 293 ret = PTR_ERR(encoder); 294 DRM_DEV_ERROR(dev->dev, 295 "failed to construct DSI encoder: %d\n", ret); 296 return ret; 297 } 298 299 /* TODO: Add DMA_S later? */ 300 encoder->possible_crtcs = 1 << DMA_P; 301 priv->encoders[priv->num_encoders++] = encoder; 302 303 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 304 if (ret) { 305 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n", 306 ret); 307 return ret; 308 } 309 310 break; 311 default: 312 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n"); 313 return -EINVAL; 314 } 315 316 return 0; 317 } 318 319 static int modeset_init(struct mdp4_kms *mdp4_kms) 320 { 321 struct drm_device *dev = mdp4_kms->dev; 322 struct msm_drm_private *priv = dev->dev_private; 323 struct drm_plane *plane; 324 struct drm_crtc *crtc; 325 int i, ret; 326 static const enum mdp4_pipe rgb_planes[] = { 327 RGB1, RGB2, 328 }; 329 static const enum mdp4_pipe vg_planes[] = { 330 VG1, VG2, 331 }; 332 static const enum mdp4_dma mdp4_crtcs[] = { 333 DMA_P, DMA_E, 334 }; 335 static const char * const mdp4_crtc_names[] = { 336 "DMA_P", "DMA_E", 337 }; 338 static const int mdp4_intfs[] = { 339 DRM_MODE_ENCODER_LVDS, 340 DRM_MODE_ENCODER_DSI, 341 DRM_MODE_ENCODER_TMDS, 342 }; 343 344 /* construct non-private planes: */ 345 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) { 346 plane = mdp4_plane_init(dev, vg_planes[i], false); 347 if (IS_ERR(plane)) { 348 DRM_DEV_ERROR(dev->dev, 349 "failed to construct plane for VG%d\n", i + 1); 350 ret = PTR_ERR(plane); 351 goto fail; 352 } 353 priv->planes[priv->num_planes++] = plane; 354 } 355 356 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) { 357 plane = mdp4_plane_init(dev, rgb_planes[i], true); 358 if (IS_ERR(plane)) { 359 DRM_DEV_ERROR(dev->dev, 360 "failed to construct plane for RGB%d\n", i + 1); 361 ret = PTR_ERR(plane); 362 goto fail; 363 } 364 365 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i, 366 mdp4_crtcs[i]); 367 if (IS_ERR(crtc)) { 368 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n", 369 mdp4_crtc_names[i]); 370 ret = PTR_ERR(crtc); 371 goto fail; 372 } 373 374 priv->crtcs[priv->num_crtcs++] = crtc; 375 } 376 377 /* 378 * we currently set up two relatively fixed paths: 379 * 380 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS 381 * or 382 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel 383 * 384 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI 385 */ 386 387 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) { 388 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]); 389 if (ret) { 390 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n", 391 i, ret); 392 goto fail; 393 } 394 } 395 396 return 0; 397 398 fail: 399 return ret; 400 } 401 402 struct msm_kms *mdp4_kms_init(struct drm_device *dev) 403 { 404 struct platform_device *pdev = to_platform_device(dev->dev); 405 struct mdp4_platform_config *config = mdp4_get_config(pdev); 406 struct mdp4_kms *mdp4_kms; 407 struct msm_kms *kms = NULL; 408 struct msm_gem_address_space *aspace; 409 int irq, ret; 410 411 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); 412 if (!mdp4_kms) { 413 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n"); 414 ret = -ENOMEM; 415 goto fail; 416 } 417 418 mdp_kms_init(&mdp4_kms->base, &kms_funcs); 419 420 kms = &mdp4_kms->base.base; 421 422 mdp4_kms->dev = dev; 423 424 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4"); 425 if (IS_ERR(mdp4_kms->mmio)) { 426 ret = PTR_ERR(mdp4_kms->mmio); 427 goto fail; 428 } 429 430 irq = platform_get_irq(pdev, 0); 431 if (irq < 0) { 432 ret = irq; 433 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); 434 goto fail; 435 } 436 437 kms->irq = irq; 438 439 /* NOTE: driver for this regulator still missing upstream.. use 440 * _get_exclusive() and ignore the error if it does not exist 441 * (and hope that the bootloader left it on for us) 442 */ 443 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); 444 if (IS_ERR(mdp4_kms->vdd)) 445 mdp4_kms->vdd = NULL; 446 447 if (mdp4_kms->vdd) { 448 ret = regulator_enable(mdp4_kms->vdd); 449 if (ret) { 450 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret); 451 goto fail; 452 } 453 } 454 455 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk"); 456 if (IS_ERR(mdp4_kms->clk)) { 457 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n"); 458 ret = PTR_ERR(mdp4_kms->clk); 459 goto fail; 460 } 461 462 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk"); 463 if (IS_ERR(mdp4_kms->pclk)) 464 mdp4_kms->pclk = NULL; 465 466 if (mdp4_kms->rev >= 2) { 467 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk"); 468 if (IS_ERR(mdp4_kms->lut_clk)) { 469 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n"); 470 ret = PTR_ERR(mdp4_kms->lut_clk); 471 goto fail; 472 } 473 } 474 475 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk"); 476 if (IS_ERR(mdp4_kms->axi_clk)) { 477 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n"); 478 ret = PTR_ERR(mdp4_kms->axi_clk); 479 goto fail; 480 } 481 482 clk_set_rate(mdp4_kms->clk, config->max_clk); 483 if (mdp4_kms->lut_clk) 484 clk_set_rate(mdp4_kms->lut_clk, config->max_clk); 485 486 pm_runtime_enable(dev->dev); 487 mdp4_kms->rpm_enabled = true; 488 489 /* make sure things are off before attaching iommu (bootloader could 490 * have left things on, in which case we'll start getting faults if 491 * we don't disable): 492 */ 493 mdp4_enable(mdp4_kms); 494 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 495 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); 496 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); 497 mdp4_disable(mdp4_kms); 498 mdelay(16); 499 500 if (config->iommu) { 501 aspace = msm_gem_address_space_create(&pdev->dev, 502 config->iommu, "mdp4"); 503 if (IS_ERR(aspace)) { 504 ret = PTR_ERR(aspace); 505 goto fail; 506 } 507 508 kms->aspace = aspace; 509 510 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, 511 ARRAY_SIZE(iommu_ports)); 512 if (ret) 513 goto fail; 514 } else { 515 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys " 516 "contig buffers for scanout\n"); 517 aspace = NULL; 518 } 519 520 ret = modeset_init(mdp4_kms); 521 if (ret) { 522 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret); 523 goto fail; 524 } 525 526 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT); 527 if (IS_ERR(mdp4_kms->blank_cursor_bo)) { 528 ret = PTR_ERR(mdp4_kms->blank_cursor_bo); 529 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret); 530 mdp4_kms->blank_cursor_bo = NULL; 531 goto fail; 532 } 533 534 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace, 535 &mdp4_kms->blank_cursor_iova); 536 if (ret) { 537 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret); 538 goto fail; 539 } 540 541 dev->mode_config.min_width = 0; 542 dev->mode_config.min_height = 0; 543 dev->mode_config.max_width = 2048; 544 dev->mode_config.max_height = 2048; 545 546 return kms; 547 548 fail: 549 if (kms) 550 mdp4_destroy(kms); 551 return ERR_PTR(ret); 552 } 553 554 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev) 555 { 556 static struct mdp4_platform_config config = {}; 557 558 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ 559 config.max_clk = 266667000; 560 config.iommu = iommu_domain_alloc(&platform_bus_type); 561 if (config.iommu) { 562 config.iommu->geometry.aperture_start = 0x1000; 563 config.iommu->geometry.aperture_end = 0xffffffff; 564 } 565 566 return &config; 567 } 568