1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 19 #include "msm_drv.h" 20 #include "msm_gem.h" 21 #include "msm_mmu.h" 22 #include "mdp4_kms.h" 23 24 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev); 25 26 static int mdp4_hw_init(struct msm_kms *kms) 27 { 28 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 29 struct drm_device *dev = mdp4_kms->dev; 30 uint32_t version, major, minor, dmap_cfg, vg_cfg; 31 unsigned long clk; 32 int ret = 0; 33 34 pm_runtime_get_sync(dev->dev); 35 36 mdp4_enable(mdp4_kms); 37 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); 38 mdp4_disable(mdp4_kms); 39 40 major = FIELD(version, MDP4_VERSION_MAJOR); 41 minor = FIELD(version, MDP4_VERSION_MINOR); 42 43 DBG("found MDP4 version v%d.%d", major, minor); 44 45 if (major != 4) { 46 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n", 47 major, minor); 48 ret = -ENXIO; 49 goto out; 50 } 51 52 mdp4_kms->rev = minor; 53 54 if (mdp4_kms->rev > 1) { 55 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); 56 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); 57 } 58 59 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); 60 61 /* max read pending cmd config, 3 pending requests: */ 62 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); 63 64 clk = clk_get_rate(mdp4_kms->clk); 65 66 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { 67 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */ 68 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */ 69 } else { 70 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */ 71 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */ 72 } 73 74 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg); 75 76 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); 77 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); 78 79 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); 80 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); 81 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); 82 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); 83 84 if (mdp4_kms->rev >= 2) 85 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); 86 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); 87 88 /* disable CSC matrix / YUV by default: */ 89 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); 90 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); 91 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); 92 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); 93 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); 94 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); 95 96 if (mdp4_kms->rev > 1) 97 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); 98 99 dev->mode_config.allow_fb_modifiers = true; 100 101 out: 102 pm_runtime_put_sync(dev->dev); 103 104 return ret; 105 } 106 107 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 108 { 109 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 110 int i; 111 struct drm_crtc *crtc; 112 struct drm_crtc_state *crtc_state; 113 114 mdp4_enable(mdp4_kms); 115 116 /* see 119ecb7fd */ 117 for_each_new_crtc_in_state(state, crtc, crtc_state, i) 118 drm_crtc_vblank_get(crtc); 119 } 120 121 static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) 122 { 123 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 124 int i; 125 struct drm_crtc *crtc; 126 struct drm_crtc_state *crtc_state; 127 128 drm_atomic_helper_wait_for_vblanks(mdp4_kms->dev, state); 129 130 /* see 119ecb7fd */ 131 for_each_new_crtc_in_state(state, crtc, crtc_state, i) 132 drm_crtc_vblank_put(crtc); 133 134 mdp4_disable(mdp4_kms); 135 } 136 137 static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms, 138 struct drm_crtc *crtc) 139 { 140 mdp4_crtc_wait_for_commit_done(crtc); 141 } 142 143 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate, 144 struct drm_encoder *encoder) 145 { 146 /* if we had >1 encoder, we'd need something more clever: */ 147 switch (encoder->encoder_type) { 148 case DRM_MODE_ENCODER_TMDS: 149 return mdp4_dtv_round_pixclk(encoder, rate); 150 case DRM_MODE_ENCODER_LVDS: 151 case DRM_MODE_ENCODER_DSI: 152 default: 153 return rate; 154 } 155 } 156 157 static const char * const iommu_ports[] = { 158 "mdp_port0_cb0", "mdp_port1_cb0", 159 }; 160 161 static void mdp4_destroy(struct msm_kms *kms) 162 { 163 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 164 struct device *dev = mdp4_kms->dev->dev; 165 struct msm_gem_address_space *aspace = kms->aspace; 166 167 if (mdp4_kms->blank_cursor_iova) 168 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace); 169 drm_gem_object_put_unlocked(mdp4_kms->blank_cursor_bo); 170 171 if (aspace) { 172 aspace->mmu->funcs->detach(aspace->mmu, 173 iommu_ports, ARRAY_SIZE(iommu_ports)); 174 msm_gem_address_space_put(aspace); 175 } 176 177 if (mdp4_kms->rpm_enabled) 178 pm_runtime_disable(dev); 179 180 kfree(mdp4_kms); 181 } 182 183 static const struct mdp_kms_funcs kms_funcs = { 184 .base = { 185 .hw_init = mdp4_hw_init, 186 .irq_preinstall = mdp4_irq_preinstall, 187 .irq_postinstall = mdp4_irq_postinstall, 188 .irq_uninstall = mdp4_irq_uninstall, 189 .irq = mdp4_irq, 190 .enable_vblank = mdp4_enable_vblank, 191 .disable_vblank = mdp4_disable_vblank, 192 .prepare_commit = mdp4_prepare_commit, 193 .complete_commit = mdp4_complete_commit, 194 .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done, 195 .get_format = mdp_get_format, 196 .round_pixclk = mdp4_round_pixclk, 197 .destroy = mdp4_destroy, 198 }, 199 .set_irqmask = mdp4_set_irqmask, 200 }; 201 202 int mdp4_disable(struct mdp4_kms *mdp4_kms) 203 { 204 DBG(""); 205 206 clk_disable_unprepare(mdp4_kms->clk); 207 if (mdp4_kms->pclk) 208 clk_disable_unprepare(mdp4_kms->pclk); 209 if (mdp4_kms->lut_clk) 210 clk_disable_unprepare(mdp4_kms->lut_clk); 211 if (mdp4_kms->axi_clk) 212 clk_disable_unprepare(mdp4_kms->axi_clk); 213 214 return 0; 215 } 216 217 int mdp4_enable(struct mdp4_kms *mdp4_kms) 218 { 219 DBG(""); 220 221 clk_prepare_enable(mdp4_kms->clk); 222 if (mdp4_kms->pclk) 223 clk_prepare_enable(mdp4_kms->pclk); 224 if (mdp4_kms->lut_clk) 225 clk_prepare_enable(mdp4_kms->lut_clk); 226 if (mdp4_kms->axi_clk) 227 clk_prepare_enable(mdp4_kms->axi_clk); 228 229 return 0; 230 } 231 232 233 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, 234 int intf_type) 235 { 236 struct drm_device *dev = mdp4_kms->dev; 237 struct msm_drm_private *priv = dev->dev_private; 238 struct drm_encoder *encoder; 239 struct drm_connector *connector; 240 struct device_node *panel_node; 241 int dsi_id; 242 int ret; 243 244 switch (intf_type) { 245 case DRM_MODE_ENCODER_LVDS: 246 /* 247 * bail out early if there is no panel node (no need to 248 * initialize LCDC encoder and LVDS connector) 249 */ 250 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0); 251 if (!panel_node) 252 return 0; 253 254 encoder = mdp4_lcdc_encoder_init(dev, panel_node); 255 if (IS_ERR(encoder)) { 256 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n"); 257 return PTR_ERR(encoder); 258 } 259 260 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */ 261 encoder->possible_crtcs = 1 << DMA_P; 262 263 connector = mdp4_lvds_connector_init(dev, panel_node, encoder); 264 if (IS_ERR(connector)) { 265 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n"); 266 return PTR_ERR(connector); 267 } 268 269 priv->encoders[priv->num_encoders++] = encoder; 270 priv->connectors[priv->num_connectors++] = connector; 271 272 break; 273 case DRM_MODE_ENCODER_TMDS: 274 encoder = mdp4_dtv_encoder_init(dev); 275 if (IS_ERR(encoder)) { 276 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n"); 277 return PTR_ERR(encoder); 278 } 279 280 /* DTV can be hooked to DMA_E: */ 281 encoder->possible_crtcs = 1 << 1; 282 283 if (priv->hdmi) { 284 /* Construct bridge/connector for HDMI: */ 285 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 286 if (ret) { 287 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret); 288 return ret; 289 } 290 } 291 292 priv->encoders[priv->num_encoders++] = encoder; 293 294 break; 295 case DRM_MODE_ENCODER_DSI: 296 /* only DSI1 supported for now */ 297 dsi_id = 0; 298 299 if (!priv->dsi[dsi_id]) 300 break; 301 302 encoder = mdp4_dsi_encoder_init(dev); 303 if (IS_ERR(encoder)) { 304 ret = PTR_ERR(encoder); 305 DRM_DEV_ERROR(dev->dev, 306 "failed to construct DSI encoder: %d\n", ret); 307 return ret; 308 } 309 310 /* TODO: Add DMA_S later? */ 311 encoder->possible_crtcs = 1 << DMA_P; 312 priv->encoders[priv->num_encoders++] = encoder; 313 314 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 315 if (ret) { 316 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n", 317 ret); 318 return ret; 319 } 320 321 break; 322 default: 323 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n"); 324 return -EINVAL; 325 } 326 327 return 0; 328 } 329 330 static int modeset_init(struct mdp4_kms *mdp4_kms) 331 { 332 struct drm_device *dev = mdp4_kms->dev; 333 struct msm_drm_private *priv = dev->dev_private; 334 struct drm_plane *plane; 335 struct drm_crtc *crtc; 336 int i, ret; 337 static const enum mdp4_pipe rgb_planes[] = { 338 RGB1, RGB2, 339 }; 340 static const enum mdp4_pipe vg_planes[] = { 341 VG1, VG2, 342 }; 343 static const enum mdp4_dma mdp4_crtcs[] = { 344 DMA_P, DMA_E, 345 }; 346 static const char * const mdp4_crtc_names[] = { 347 "DMA_P", "DMA_E", 348 }; 349 static const int mdp4_intfs[] = { 350 DRM_MODE_ENCODER_LVDS, 351 DRM_MODE_ENCODER_DSI, 352 DRM_MODE_ENCODER_TMDS, 353 }; 354 355 /* construct non-private planes: */ 356 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) { 357 plane = mdp4_plane_init(dev, vg_planes[i], false); 358 if (IS_ERR(plane)) { 359 DRM_DEV_ERROR(dev->dev, 360 "failed to construct plane for VG%d\n", i + 1); 361 ret = PTR_ERR(plane); 362 goto fail; 363 } 364 priv->planes[priv->num_planes++] = plane; 365 } 366 367 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) { 368 plane = mdp4_plane_init(dev, rgb_planes[i], true); 369 if (IS_ERR(plane)) { 370 DRM_DEV_ERROR(dev->dev, 371 "failed to construct plane for RGB%d\n", i + 1); 372 ret = PTR_ERR(plane); 373 goto fail; 374 } 375 376 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i, 377 mdp4_crtcs[i]); 378 if (IS_ERR(crtc)) { 379 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n", 380 mdp4_crtc_names[i]); 381 ret = PTR_ERR(crtc); 382 goto fail; 383 } 384 385 priv->crtcs[priv->num_crtcs++] = crtc; 386 } 387 388 /* 389 * we currently set up two relatively fixed paths: 390 * 391 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS 392 * or 393 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel 394 * 395 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI 396 */ 397 398 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) { 399 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]); 400 if (ret) { 401 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n", 402 i, ret); 403 goto fail; 404 } 405 } 406 407 return 0; 408 409 fail: 410 return ret; 411 } 412 413 struct msm_kms *mdp4_kms_init(struct drm_device *dev) 414 { 415 struct platform_device *pdev = to_platform_device(dev->dev); 416 struct mdp4_platform_config *config = mdp4_get_config(pdev); 417 struct mdp4_kms *mdp4_kms; 418 struct msm_kms *kms = NULL; 419 struct msm_gem_address_space *aspace; 420 int irq, ret; 421 422 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); 423 if (!mdp4_kms) { 424 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n"); 425 ret = -ENOMEM; 426 goto fail; 427 } 428 429 mdp_kms_init(&mdp4_kms->base, &kms_funcs); 430 431 kms = &mdp4_kms->base.base; 432 433 mdp4_kms->dev = dev; 434 435 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4"); 436 if (IS_ERR(mdp4_kms->mmio)) { 437 ret = PTR_ERR(mdp4_kms->mmio); 438 goto fail; 439 } 440 441 irq = platform_get_irq(pdev, 0); 442 if (irq < 0) { 443 ret = irq; 444 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); 445 goto fail; 446 } 447 448 kms->irq = irq; 449 450 /* NOTE: driver for this regulator still missing upstream.. use 451 * _get_exclusive() and ignore the error if it does not exist 452 * (and hope that the bootloader left it on for us) 453 */ 454 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); 455 if (IS_ERR(mdp4_kms->vdd)) 456 mdp4_kms->vdd = NULL; 457 458 if (mdp4_kms->vdd) { 459 ret = regulator_enable(mdp4_kms->vdd); 460 if (ret) { 461 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret); 462 goto fail; 463 } 464 } 465 466 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk"); 467 if (IS_ERR(mdp4_kms->clk)) { 468 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n"); 469 ret = PTR_ERR(mdp4_kms->clk); 470 goto fail; 471 } 472 473 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk"); 474 if (IS_ERR(mdp4_kms->pclk)) 475 mdp4_kms->pclk = NULL; 476 477 if (mdp4_kms->rev >= 2) { 478 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk"); 479 if (IS_ERR(mdp4_kms->lut_clk)) { 480 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n"); 481 ret = PTR_ERR(mdp4_kms->lut_clk); 482 goto fail; 483 } 484 } 485 486 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk"); 487 if (IS_ERR(mdp4_kms->axi_clk)) { 488 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n"); 489 ret = PTR_ERR(mdp4_kms->axi_clk); 490 goto fail; 491 } 492 493 clk_set_rate(mdp4_kms->clk, config->max_clk); 494 if (mdp4_kms->lut_clk) 495 clk_set_rate(mdp4_kms->lut_clk, config->max_clk); 496 497 pm_runtime_enable(dev->dev); 498 mdp4_kms->rpm_enabled = true; 499 500 /* make sure things are off before attaching iommu (bootloader could 501 * have left things on, in which case we'll start getting faults if 502 * we don't disable): 503 */ 504 mdp4_enable(mdp4_kms); 505 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 506 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); 507 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); 508 mdp4_disable(mdp4_kms); 509 mdelay(16); 510 511 if (config->iommu) { 512 aspace = msm_gem_address_space_create(&pdev->dev, 513 config->iommu, "mdp4"); 514 if (IS_ERR(aspace)) { 515 ret = PTR_ERR(aspace); 516 goto fail; 517 } 518 519 kms->aspace = aspace; 520 521 ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports, 522 ARRAY_SIZE(iommu_ports)); 523 if (ret) 524 goto fail; 525 } else { 526 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys " 527 "contig buffers for scanout\n"); 528 aspace = NULL; 529 } 530 531 ret = modeset_init(mdp4_kms); 532 if (ret) { 533 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret); 534 goto fail; 535 } 536 537 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT); 538 if (IS_ERR(mdp4_kms->blank_cursor_bo)) { 539 ret = PTR_ERR(mdp4_kms->blank_cursor_bo); 540 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret); 541 mdp4_kms->blank_cursor_bo = NULL; 542 goto fail; 543 } 544 545 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace, 546 &mdp4_kms->blank_cursor_iova); 547 if (ret) { 548 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret); 549 goto fail; 550 } 551 552 dev->mode_config.min_width = 0; 553 dev->mode_config.min_height = 0; 554 dev->mode_config.max_width = 2048; 555 dev->mode_config.max_height = 2048; 556 557 return kms; 558 559 fail: 560 if (kms) 561 mdp4_destroy(kms); 562 return ERR_PTR(ret); 563 } 564 565 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev) 566 { 567 static struct mdp4_platform_config config = {}; 568 569 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ 570 config.max_clk = 266667000; 571 config.iommu = iommu_domain_alloc(&platform_bus_type); 572 if (config.iommu) { 573 config.iommu->geometry.aperture_start = 0x1000; 574 config.iommu->geometry.aperture_end = 0xffffffff; 575 } 576 577 return &config; 578 } 579