1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/delay.h> 8 9 #include <drm/drm_vblank.h> 10 11 #include "msm_drv.h" 12 #include "msm_gem.h" 13 #include "msm_mmu.h" 14 #include "mdp4_kms.h" 15 16 static int mdp4_hw_init(struct msm_kms *kms) 17 { 18 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 19 struct drm_device *dev = mdp4_kms->dev; 20 u32 dmap_cfg, vg_cfg; 21 unsigned long clk; 22 23 pm_runtime_get_sync(dev->dev); 24 25 if (mdp4_kms->rev > 1) { 26 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); 27 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); 28 } 29 30 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); 31 32 /* max read pending cmd config, 3 pending requests: */ 33 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); 34 35 clk = clk_get_rate(mdp4_kms->clk); 36 37 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { 38 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */ 39 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */ 40 } else { 41 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */ 42 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */ 43 } 44 45 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg); 46 47 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); 48 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); 49 50 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); 51 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); 52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); 53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); 54 55 if (mdp4_kms->rev >= 2) 56 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); 57 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); 58 59 /* disable CSC matrix / YUV by default: */ 60 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); 61 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); 62 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); 63 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); 64 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); 65 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); 66 67 if (mdp4_kms->rev > 1) 68 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); 69 70 pm_runtime_put_sync(dev->dev); 71 72 return 0; 73 } 74 75 static void mdp4_enable_commit(struct msm_kms *kms) 76 { 77 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 78 mdp4_enable(mdp4_kms); 79 } 80 81 static void mdp4_disable_commit(struct msm_kms *kms) 82 { 83 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 84 mdp4_disable(mdp4_kms); 85 } 86 87 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 88 { 89 /* TODO */ 90 } 91 92 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 93 { 94 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 95 struct drm_crtc *crtc; 96 97 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask) 98 mdp4_crtc_wait_for_commit_done(crtc); 99 } 100 101 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 102 { 103 } 104 105 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate, 106 struct drm_encoder *encoder) 107 { 108 /* if we had >1 encoder, we'd need something more clever: */ 109 switch (encoder->encoder_type) { 110 case DRM_MODE_ENCODER_TMDS: 111 return mdp4_dtv_round_pixclk(encoder, rate); 112 case DRM_MODE_ENCODER_LVDS: 113 case DRM_MODE_ENCODER_DSI: 114 default: 115 return rate; 116 } 117 } 118 119 static void mdp4_destroy(struct msm_kms *kms) 120 { 121 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 122 struct device *dev = mdp4_kms->dev->dev; 123 struct msm_gem_address_space *aspace = kms->aspace; 124 125 if (mdp4_kms->blank_cursor_iova) 126 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace); 127 drm_gem_object_put(mdp4_kms->blank_cursor_bo); 128 129 if (aspace) { 130 aspace->mmu->funcs->detach(aspace->mmu); 131 msm_gem_address_space_put(aspace); 132 } 133 134 if (mdp4_kms->rpm_enabled) 135 pm_runtime_disable(dev); 136 137 mdp_kms_destroy(&mdp4_kms->base); 138 139 kfree(mdp4_kms); 140 } 141 142 static const struct mdp_kms_funcs kms_funcs = { 143 .base = { 144 .hw_init = mdp4_hw_init, 145 .irq_preinstall = mdp4_irq_preinstall, 146 .irq_postinstall = mdp4_irq_postinstall, 147 .irq_uninstall = mdp4_irq_uninstall, 148 .irq = mdp4_irq, 149 .enable_vblank = mdp4_enable_vblank, 150 .disable_vblank = mdp4_disable_vblank, 151 .enable_commit = mdp4_enable_commit, 152 .disable_commit = mdp4_disable_commit, 153 .flush_commit = mdp4_flush_commit, 154 .wait_flush = mdp4_wait_flush, 155 .complete_commit = mdp4_complete_commit, 156 .get_format = mdp_get_format, 157 .round_pixclk = mdp4_round_pixclk, 158 .destroy = mdp4_destroy, 159 }, 160 .set_irqmask = mdp4_set_irqmask, 161 }; 162 163 int mdp4_disable(struct mdp4_kms *mdp4_kms) 164 { 165 DBG(""); 166 167 clk_disable_unprepare(mdp4_kms->clk); 168 clk_disable_unprepare(mdp4_kms->pclk); 169 clk_disable_unprepare(mdp4_kms->lut_clk); 170 clk_disable_unprepare(mdp4_kms->axi_clk); 171 172 return 0; 173 } 174 175 int mdp4_enable(struct mdp4_kms *mdp4_kms) 176 { 177 DBG(""); 178 179 clk_prepare_enable(mdp4_kms->clk); 180 clk_prepare_enable(mdp4_kms->pclk); 181 clk_prepare_enable(mdp4_kms->lut_clk); 182 clk_prepare_enable(mdp4_kms->axi_clk); 183 184 return 0; 185 } 186 187 188 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, 189 int intf_type) 190 { 191 struct drm_device *dev = mdp4_kms->dev; 192 struct msm_drm_private *priv = dev->dev_private; 193 struct drm_encoder *encoder; 194 struct drm_connector *connector; 195 struct device_node *panel_node; 196 int dsi_id; 197 int ret; 198 199 switch (intf_type) { 200 case DRM_MODE_ENCODER_LVDS: 201 /* 202 * bail out early if there is no panel node (no need to 203 * initialize LCDC encoder and LVDS connector) 204 */ 205 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0); 206 if (!panel_node) 207 return 0; 208 209 encoder = mdp4_lcdc_encoder_init(dev, panel_node); 210 if (IS_ERR(encoder)) { 211 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n"); 212 of_node_put(panel_node); 213 return PTR_ERR(encoder); 214 } 215 216 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */ 217 encoder->possible_crtcs = 1 << DMA_P; 218 219 connector = mdp4_lvds_connector_init(dev, panel_node, encoder); 220 if (IS_ERR(connector)) { 221 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n"); 222 of_node_put(panel_node); 223 return PTR_ERR(connector); 224 } 225 226 break; 227 case DRM_MODE_ENCODER_TMDS: 228 encoder = mdp4_dtv_encoder_init(dev); 229 if (IS_ERR(encoder)) { 230 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n"); 231 return PTR_ERR(encoder); 232 } 233 234 /* DTV can be hooked to DMA_E: */ 235 encoder->possible_crtcs = 1 << 1; 236 237 if (priv->hdmi) { 238 /* Construct bridge/connector for HDMI: */ 239 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 240 if (ret) { 241 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret); 242 return ret; 243 } 244 } 245 246 break; 247 case DRM_MODE_ENCODER_DSI: 248 /* only DSI1 supported for now */ 249 dsi_id = 0; 250 251 if (!priv->dsi[dsi_id]) 252 break; 253 254 encoder = mdp4_dsi_encoder_init(dev); 255 if (IS_ERR(encoder)) { 256 ret = PTR_ERR(encoder); 257 DRM_DEV_ERROR(dev->dev, 258 "failed to construct DSI encoder: %d\n", ret); 259 return ret; 260 } 261 262 /* TODO: Add DMA_S later? */ 263 encoder->possible_crtcs = 1 << DMA_P; 264 265 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 266 if (ret) { 267 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n", 268 ret); 269 return ret; 270 } 271 272 break; 273 default: 274 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n"); 275 return -EINVAL; 276 } 277 278 return 0; 279 } 280 281 static int modeset_init(struct mdp4_kms *mdp4_kms) 282 { 283 struct drm_device *dev = mdp4_kms->dev; 284 struct msm_drm_private *priv = dev->dev_private; 285 struct drm_plane *plane; 286 struct drm_crtc *crtc; 287 int i, ret; 288 static const enum mdp4_pipe rgb_planes[] = { 289 RGB1, RGB2, 290 }; 291 static const enum mdp4_pipe vg_planes[] = { 292 VG1, VG2, 293 }; 294 static const enum mdp4_dma mdp4_crtcs[] = { 295 DMA_P, DMA_E, 296 }; 297 static const char * const mdp4_crtc_names[] = { 298 "DMA_P", "DMA_E", 299 }; 300 static const int mdp4_intfs[] = { 301 DRM_MODE_ENCODER_LVDS, 302 DRM_MODE_ENCODER_DSI, 303 DRM_MODE_ENCODER_TMDS, 304 }; 305 306 /* construct non-private planes: */ 307 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) { 308 plane = mdp4_plane_init(dev, vg_planes[i], false); 309 if (IS_ERR(plane)) { 310 DRM_DEV_ERROR(dev->dev, 311 "failed to construct plane for VG%d\n", i + 1); 312 ret = PTR_ERR(plane); 313 goto fail; 314 } 315 } 316 317 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) { 318 plane = mdp4_plane_init(dev, rgb_planes[i], true); 319 if (IS_ERR(plane)) { 320 DRM_DEV_ERROR(dev->dev, 321 "failed to construct plane for RGB%d\n", i + 1); 322 ret = PTR_ERR(plane); 323 goto fail; 324 } 325 326 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i, 327 mdp4_crtcs[i]); 328 if (IS_ERR(crtc)) { 329 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n", 330 mdp4_crtc_names[i]); 331 ret = PTR_ERR(crtc); 332 goto fail; 333 } 334 335 priv->num_crtcs++; 336 } 337 338 /* 339 * we currently set up two relatively fixed paths: 340 * 341 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS 342 * or 343 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel 344 * 345 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI 346 */ 347 348 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) { 349 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]); 350 if (ret) { 351 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n", 352 i, ret); 353 goto fail; 354 } 355 } 356 357 return 0; 358 359 fail: 360 return ret; 361 } 362 363 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms, 364 u32 *major, u32 *minor) 365 { 366 struct drm_device *dev = mdp4_kms->dev; 367 u32 version; 368 369 mdp4_enable(mdp4_kms); 370 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); 371 mdp4_disable(mdp4_kms); 372 373 *major = FIELD(version, MDP4_VERSION_MAJOR); 374 *minor = FIELD(version, MDP4_VERSION_MINOR); 375 376 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor); 377 } 378 379 static int mdp4_kms_init(struct drm_device *dev) 380 { 381 struct platform_device *pdev = to_platform_device(dev->dev); 382 struct msm_drm_private *priv = dev->dev_private; 383 struct mdp4_kms *mdp4_kms; 384 struct msm_kms *kms = NULL; 385 struct msm_mmu *mmu; 386 struct msm_gem_address_space *aspace; 387 int irq, ret; 388 u32 major, minor; 389 unsigned long max_clk; 390 391 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ 392 max_clk = 266667000; 393 394 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); 395 if (!mdp4_kms) { 396 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n"); 397 return -ENOMEM; 398 } 399 400 ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs); 401 if (ret) { 402 DRM_DEV_ERROR(dev->dev, "failed to init kms\n"); 403 goto fail; 404 } 405 406 priv->kms = &mdp4_kms->base.base; 407 kms = priv->kms; 408 409 mdp4_kms->dev = dev; 410 411 mdp4_kms->mmio = msm_ioremap(pdev, NULL); 412 if (IS_ERR(mdp4_kms->mmio)) { 413 ret = PTR_ERR(mdp4_kms->mmio); 414 goto fail; 415 } 416 417 irq = platform_get_irq(pdev, 0); 418 if (irq < 0) { 419 ret = irq; 420 goto fail; 421 } 422 423 kms->irq = irq; 424 425 /* NOTE: driver for this regulator still missing upstream.. use 426 * _get_exclusive() and ignore the error if it does not exist 427 * (and hope that the bootloader left it on for us) 428 */ 429 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); 430 if (IS_ERR(mdp4_kms->vdd)) 431 mdp4_kms->vdd = NULL; 432 433 if (mdp4_kms->vdd) { 434 ret = regulator_enable(mdp4_kms->vdd); 435 if (ret) { 436 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret); 437 goto fail; 438 } 439 } 440 441 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk"); 442 if (IS_ERR(mdp4_kms->clk)) { 443 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n"); 444 ret = PTR_ERR(mdp4_kms->clk); 445 goto fail; 446 } 447 448 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk"); 449 if (IS_ERR(mdp4_kms->pclk)) 450 mdp4_kms->pclk = NULL; 451 452 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk"); 453 if (IS_ERR(mdp4_kms->axi_clk)) { 454 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n"); 455 ret = PTR_ERR(mdp4_kms->axi_clk); 456 goto fail; 457 } 458 459 clk_set_rate(mdp4_kms->clk, max_clk); 460 461 read_mdp_hw_revision(mdp4_kms, &major, &minor); 462 463 if (major != 4) { 464 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n", 465 major, minor); 466 ret = -ENXIO; 467 goto fail; 468 } 469 470 mdp4_kms->rev = minor; 471 472 if (mdp4_kms->rev >= 2) { 473 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk"); 474 if (IS_ERR(mdp4_kms->lut_clk)) { 475 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n"); 476 ret = PTR_ERR(mdp4_kms->lut_clk); 477 goto fail; 478 } 479 clk_set_rate(mdp4_kms->lut_clk, max_clk); 480 } 481 482 pm_runtime_enable(dev->dev); 483 mdp4_kms->rpm_enabled = true; 484 485 /* make sure things are off before attaching iommu (bootloader could 486 * have left things on, in which case we'll start getting faults if 487 * we don't disable): 488 */ 489 mdp4_enable(mdp4_kms); 490 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 491 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); 492 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); 493 mdp4_disable(mdp4_kms); 494 mdelay(16); 495 496 mmu = msm_iommu_new(&pdev->dev, 0); 497 if (IS_ERR(mmu)) { 498 ret = PTR_ERR(mmu); 499 goto fail; 500 } else if (!mmu) { 501 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys " 502 "contig buffers for scanout\n"); 503 aspace = NULL; 504 } else { 505 aspace = msm_gem_address_space_create(mmu, 506 "mdp4", 0x1000, 0x100000000 - 0x1000); 507 508 if (IS_ERR(aspace)) { 509 if (!IS_ERR(mmu)) 510 mmu->funcs->destroy(mmu); 511 ret = PTR_ERR(aspace); 512 goto fail; 513 } 514 515 kms->aspace = aspace; 516 } 517 518 ret = modeset_init(mdp4_kms); 519 if (ret) { 520 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret); 521 goto fail; 522 } 523 524 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT); 525 if (IS_ERR(mdp4_kms->blank_cursor_bo)) { 526 ret = PTR_ERR(mdp4_kms->blank_cursor_bo); 527 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret); 528 mdp4_kms->blank_cursor_bo = NULL; 529 goto fail; 530 } 531 532 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace, 533 &mdp4_kms->blank_cursor_iova); 534 if (ret) { 535 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret); 536 goto fail; 537 } 538 539 dev->mode_config.min_width = 0; 540 dev->mode_config.min_height = 0; 541 dev->mode_config.max_width = 2048; 542 dev->mode_config.max_height = 2048; 543 544 return 0; 545 546 fail: 547 if (kms) 548 mdp4_destroy(kms); 549 550 return ret; 551 } 552 553 static const struct dev_pm_ops mdp4_pm_ops = { 554 .prepare = msm_pm_prepare, 555 .complete = msm_pm_complete, 556 }; 557 558 static int mdp4_probe(struct platform_device *pdev) 559 { 560 return msm_drv_probe(&pdev->dev, mdp4_kms_init); 561 } 562 563 static int mdp4_remove(struct platform_device *pdev) 564 { 565 component_master_del(&pdev->dev, &msm_drm_ops); 566 567 return 0; 568 } 569 570 static const struct of_device_id mdp4_dt_match[] = { 571 { .compatible = "qcom,mdp4" }, 572 { /* sentinel */ } 573 }; 574 MODULE_DEVICE_TABLE(of, mdp4_dt_match); 575 576 static struct platform_driver mdp4_platform_driver = { 577 .probe = mdp4_probe, 578 .remove = mdp4_remove, 579 .shutdown = msm_drv_shutdown, 580 .driver = { 581 .name = "mdp4", 582 .of_match_table = mdp4_dt_match, 583 .pm = &mdp4_pm_ops, 584 }, 585 }; 586 587 void __init msm_mdp4_register(void) 588 { 589 platform_driver_register(&mdp4_platform_driver); 590 } 591 592 void __exit msm_mdp4_unregister(void) 593 { 594 platform_driver_unregister(&mdp4_platform_driver); 595 } 596