1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 21 #include "mdp4_kms.h" 22 23 struct mdp4_dtv_encoder { 24 struct drm_encoder base; 25 struct clk *hdmi_clk; 26 struct clk *mdp_clk; 27 unsigned long int pixclock; 28 bool enabled; 29 uint32_t bsc; 30 }; 31 #define to_mdp4_dtv_encoder(x) container_of(x, struct mdp4_dtv_encoder, base) 32 33 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) 34 { 35 struct msm_drm_private *priv = encoder->dev->dev_private; 36 return to_mdp4_kms(to_mdp_kms(priv->kms)); 37 } 38 39 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING 40 #include <mach/board.h> 41 /* not ironically named at all.. no, really.. */ 42 static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) 43 { 44 struct drm_device *dev = mdp4_dtv_encoder->base.dev; 45 struct lcdc_platform_data *dtv_pdata = mdp4_find_pdata("dtv.0"); 46 47 if (!dtv_pdata) { 48 dev_err(dev->dev, "could not find dtv pdata\n"); 49 return; 50 } 51 52 if (dtv_pdata->bus_scale_table) { 53 mdp4_dtv_encoder->bsc = msm_bus_scale_register_client( 54 dtv_pdata->bus_scale_table); 55 DBG("bus scale client: %08x", mdp4_dtv_encoder->bsc); 56 DBG("lcdc_power_save: %p", dtv_pdata->lcdc_power_save); 57 if (dtv_pdata->lcdc_power_save) 58 dtv_pdata->lcdc_power_save(1); 59 } 60 } 61 62 static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder) 63 { 64 if (mdp4_dtv_encoder->bsc) { 65 msm_bus_scale_unregister_client(mdp4_dtv_encoder->bsc); 66 mdp4_dtv_encoder->bsc = 0; 67 } 68 } 69 70 static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx) 71 { 72 if (mdp4_dtv_encoder->bsc) { 73 DBG("set bus scaling: %d", idx); 74 msm_bus_scale_client_update_request(mdp4_dtv_encoder->bsc, idx); 75 } 76 } 77 #else 78 static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {} 79 static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {} 80 static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx) {} 81 #endif 82 83 static void mdp4_dtv_encoder_destroy(struct drm_encoder *encoder) 84 { 85 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 86 bs_fini(mdp4_dtv_encoder); 87 drm_encoder_cleanup(encoder); 88 kfree(mdp4_dtv_encoder); 89 } 90 91 static const struct drm_encoder_funcs mdp4_dtv_encoder_funcs = { 92 .destroy = mdp4_dtv_encoder_destroy, 93 }; 94 95 static void mdp4_dtv_encoder_mode_set(struct drm_encoder *encoder, 96 struct drm_display_mode *mode, 97 struct drm_display_mode *adjusted_mode) 98 { 99 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 100 struct mdp4_kms *mdp4_kms = get_kms(encoder); 101 uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; 102 uint32_t display_v_start, display_v_end; 103 uint32_t hsync_start_x, hsync_end_x; 104 105 mode = adjusted_mode; 106 107 DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", 108 mode->base.id, mode->name, 109 mode->vrefresh, mode->clock, 110 mode->hdisplay, mode->hsync_start, 111 mode->hsync_end, mode->htotal, 112 mode->vdisplay, mode->vsync_start, 113 mode->vsync_end, mode->vtotal, 114 mode->type, mode->flags); 115 116 mdp4_dtv_encoder->pixclock = mode->clock * 1000; 117 118 DBG("pixclock=%lu", mdp4_dtv_encoder->pixclock); 119 120 ctrl_pol = 0; 121 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 122 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW; 123 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 124 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW; 125 /* probably need to get DATA_EN polarity from panel.. */ 126 127 dtv_hsync_skew = 0; /* get this from panel? */ 128 129 hsync_start_x = (mode->htotal - mode->hsync_start); 130 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; 131 132 vsync_period = mode->vtotal * mode->htotal; 133 vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; 134 display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; 135 display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1; 136 137 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, 138 MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) | 139 MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal)); 140 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); 141 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); 142 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, 143 MDP4_DTV_DISPLAY_HCTRL_START(hsync_start_x) | 144 MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x)); 145 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); 146 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); 147 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); 148 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, 149 MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY | 150 MDP4_DTV_UNDERFLOW_CLR_COLOR(0xff)); 151 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew); 152 mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); 153 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL, 154 MDP4_DTV_ACTIVE_HCTL_START(0) | 155 MDP4_DTV_ACTIVE_HCTL_END(0)); 156 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0); 157 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0); 158 } 159 160 static void mdp4_dtv_encoder_disable(struct drm_encoder *encoder) 161 { 162 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 163 struct mdp4_kms *mdp4_kms = get_kms(encoder); 164 165 if (WARN_ON(!mdp4_dtv_encoder->enabled)) 166 return; 167 168 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 169 170 /* 171 * Wait for a vsync so we know the ENABLE=0 latched before 172 * the (connector) source of the vsync's gets disabled, 173 * otherwise we end up in a funny state if we re-enable 174 * before the disable latches, which results that some of 175 * the settings changes for the new modeset (like new 176 * scanout buffer) don't latch properly.. 177 */ 178 mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC); 179 180 clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk); 181 clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk); 182 183 bs_set(mdp4_dtv_encoder, 0); 184 185 mdp4_dtv_encoder->enabled = false; 186 } 187 188 static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder) 189 { 190 struct drm_device *dev = encoder->dev; 191 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 192 struct mdp4_kms *mdp4_kms = get_kms(encoder); 193 unsigned long pc = mdp4_dtv_encoder->pixclock; 194 int ret; 195 196 if (WARN_ON(mdp4_dtv_encoder->enabled)) 197 return; 198 199 mdp4_crtc_set_config(encoder->crtc, 200 MDP4_DMA_CONFIG_R_BPC(BPC8) | 201 MDP4_DMA_CONFIG_G_BPC(BPC8) | 202 MDP4_DMA_CONFIG_B_BPC(BPC8) | 203 MDP4_DMA_CONFIG_PACK(0x21)); 204 mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 1); 205 206 bs_set(mdp4_dtv_encoder, 1); 207 208 DBG("setting mdp_clk=%lu", pc); 209 210 ret = clk_set_rate(mdp4_dtv_encoder->mdp_clk, pc); 211 if (ret) 212 dev_err(dev->dev, "failed to set mdp_clk to %lu: %d\n", 213 pc, ret); 214 215 ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk); 216 if (ret) 217 dev_err(dev->dev, "failed to enabled mdp_clk: %d\n", ret); 218 219 ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk); 220 if (ret) 221 dev_err(dev->dev, "failed to enable hdmi_clk: %d\n", ret); 222 223 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1); 224 225 mdp4_dtv_encoder->enabled = true; 226 } 227 228 static const struct drm_encoder_helper_funcs mdp4_dtv_encoder_helper_funcs = { 229 .mode_set = mdp4_dtv_encoder_mode_set, 230 .enable = mdp4_dtv_encoder_enable, 231 .disable = mdp4_dtv_encoder_disable, 232 }; 233 234 long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate) 235 { 236 struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 237 return clk_round_rate(mdp4_dtv_encoder->mdp_clk, rate); 238 } 239 240 /* initialize encoder */ 241 struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev) 242 { 243 struct drm_encoder *encoder = NULL; 244 struct mdp4_dtv_encoder *mdp4_dtv_encoder; 245 int ret; 246 247 mdp4_dtv_encoder = kzalloc(sizeof(*mdp4_dtv_encoder), GFP_KERNEL); 248 if (!mdp4_dtv_encoder) { 249 ret = -ENOMEM; 250 goto fail; 251 } 252 253 encoder = &mdp4_dtv_encoder->base; 254 255 drm_encoder_init(dev, encoder, &mdp4_dtv_encoder_funcs, 256 DRM_MODE_ENCODER_TMDS, NULL); 257 drm_encoder_helper_add(encoder, &mdp4_dtv_encoder_helper_funcs); 258 259 mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk"); 260 if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) { 261 dev_err(dev->dev, "failed to get hdmi_clk\n"); 262 ret = PTR_ERR(mdp4_dtv_encoder->hdmi_clk); 263 goto fail; 264 } 265 266 mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "tv_clk"); 267 if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) { 268 dev_err(dev->dev, "failed to get tv_clk\n"); 269 ret = PTR_ERR(mdp4_dtv_encoder->mdp_clk); 270 goto fail; 271 } 272 273 bs_init(mdp4_dtv_encoder); 274 275 return encoder; 276 277 fail: 278 if (encoder) 279 mdp4_dtv_encoder_destroy(encoder); 280 281 return ERR_PTR(ret); 282 } 283