1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
214be3200SRob Clark /*
314be3200SRob Clark  * Copyright (C) 2013 Red Hat
414be3200SRob Clark  * Author: Rob Clark <robdclark@gmail.com>
514be3200SRob Clark  */
614be3200SRob Clark 
714be3200SRob Clark #include <drm/drm_crtc.h>
8fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h>
914be3200SRob Clark 
1014be3200SRob Clark #include "mdp4_kms.h"
1114be3200SRob Clark 
1214be3200SRob Clark struct mdp4_dtv_encoder {
1314be3200SRob Clark 	struct drm_encoder base;
1414be3200SRob Clark 	struct clk *hdmi_clk;
1514be3200SRob Clark 	struct clk *mdp_clk;
1614be3200SRob Clark 	unsigned long int pixclock;
1714be3200SRob Clark 	bool enabled;
1814be3200SRob Clark 	uint32_t bsc;
1914be3200SRob Clark };
2014be3200SRob Clark #define to_mdp4_dtv_encoder(x) container_of(x, struct mdp4_dtv_encoder, base)
2114be3200SRob Clark 
2214be3200SRob Clark static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
2314be3200SRob Clark {
2414be3200SRob Clark 	struct msm_drm_private *priv = encoder->dev->dev_private;
2514be3200SRob Clark 	return to_mdp4_kms(to_mdp_kms(priv->kms));
2614be3200SRob Clark }
2714be3200SRob Clark 
2814be3200SRob Clark #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
2914be3200SRob Clark #include <mach/board.h>
3014be3200SRob Clark /* not ironically named at all.. no, really.. */
3114be3200SRob Clark static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
3214be3200SRob Clark {
3314be3200SRob Clark 	struct drm_device *dev = mdp4_dtv_encoder->base.dev;
3414be3200SRob Clark 	struct lcdc_platform_data *dtv_pdata = mdp4_find_pdata("dtv.0");
3514be3200SRob Clark 
3614be3200SRob Clark 	if (!dtv_pdata) {
376a41da17SMamta Shukla 		DRM_DEV_ERROR(dev->dev, "could not find dtv pdata\n");
3814be3200SRob Clark 		return;
3914be3200SRob Clark 	}
4014be3200SRob Clark 
4114be3200SRob Clark 	if (dtv_pdata->bus_scale_table) {
4214be3200SRob Clark 		mdp4_dtv_encoder->bsc = msm_bus_scale_register_client(
4314be3200SRob Clark 				dtv_pdata->bus_scale_table);
4414be3200SRob Clark 		DBG("bus scale client: %08x", mdp4_dtv_encoder->bsc);
4514be3200SRob Clark 		DBG("lcdc_power_save: %p", dtv_pdata->lcdc_power_save);
4614be3200SRob Clark 		if (dtv_pdata->lcdc_power_save)
4714be3200SRob Clark 			dtv_pdata->lcdc_power_save(1);
4814be3200SRob Clark 	}
4914be3200SRob Clark }
5014be3200SRob Clark 
5114be3200SRob Clark static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
5214be3200SRob Clark {
5314be3200SRob Clark 	if (mdp4_dtv_encoder->bsc) {
5414be3200SRob Clark 		msm_bus_scale_unregister_client(mdp4_dtv_encoder->bsc);
5514be3200SRob Clark 		mdp4_dtv_encoder->bsc = 0;
5614be3200SRob Clark 	}
5714be3200SRob Clark }
5814be3200SRob Clark 
5914be3200SRob Clark static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx)
6014be3200SRob Clark {
6114be3200SRob Clark 	if (mdp4_dtv_encoder->bsc) {
6214be3200SRob Clark 		DBG("set bus scaling: %d", idx);
6314be3200SRob Clark 		msm_bus_scale_client_update_request(mdp4_dtv_encoder->bsc, idx);
6414be3200SRob Clark 	}
6514be3200SRob Clark }
6614be3200SRob Clark #else
6714be3200SRob Clark static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {}
6814be3200SRob Clark static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {}
6914be3200SRob Clark static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx) {}
7014be3200SRob Clark #endif
7114be3200SRob Clark 
7214be3200SRob Clark static void mdp4_dtv_encoder_destroy(struct drm_encoder *encoder)
7314be3200SRob Clark {
7414be3200SRob Clark 	struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
7514be3200SRob Clark 	bs_fini(mdp4_dtv_encoder);
7614be3200SRob Clark 	drm_encoder_cleanup(encoder);
7714be3200SRob Clark 	kfree(mdp4_dtv_encoder);
7814be3200SRob Clark }
7914be3200SRob Clark 
8014be3200SRob Clark static const struct drm_encoder_funcs mdp4_dtv_encoder_funcs = {
8114be3200SRob Clark 	.destroy = mdp4_dtv_encoder_destroy,
8214be3200SRob Clark };
8314be3200SRob Clark 
8414be3200SRob Clark static void mdp4_dtv_encoder_mode_set(struct drm_encoder *encoder,
8514be3200SRob Clark 		struct drm_display_mode *mode,
8614be3200SRob Clark 		struct drm_display_mode *adjusted_mode)
8714be3200SRob Clark {
8814be3200SRob Clark 	struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
8914be3200SRob Clark 	struct mdp4_kms *mdp4_kms = get_kms(encoder);
9014be3200SRob Clark 	uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
9114be3200SRob Clark 	uint32_t display_v_start, display_v_end;
9214be3200SRob Clark 	uint32_t hsync_start_x, hsync_end_x;
9314be3200SRob Clark 
9414be3200SRob Clark 	mode = adjusted_mode;
9514be3200SRob Clark 
967510a9c6SShayenne Moura 	DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
9714be3200SRob Clark 
9814be3200SRob Clark 	mdp4_dtv_encoder->pixclock = mode->clock * 1000;
9914be3200SRob Clark 
10014be3200SRob Clark 	DBG("pixclock=%lu", mdp4_dtv_encoder->pixclock);
10114be3200SRob Clark 
10214be3200SRob Clark 	ctrl_pol = 0;
10314be3200SRob Clark 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
10414be3200SRob Clark 		ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW;
10514be3200SRob Clark 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
10614be3200SRob Clark 		ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW;
10714be3200SRob Clark 	/* probably need to get DATA_EN polarity from panel.. */
10814be3200SRob Clark 
10914be3200SRob Clark 	dtv_hsync_skew = 0;  /* get this from panel? */
11014be3200SRob Clark 
11114be3200SRob Clark 	hsync_start_x = (mode->htotal - mode->hsync_start);
11214be3200SRob Clark 	hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
11314be3200SRob Clark 
11414be3200SRob Clark 	vsync_period = mode->vtotal * mode->htotal;
11514be3200SRob Clark 	vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
11614be3200SRob Clark 	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
11714be3200SRob Clark 	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
11814be3200SRob Clark 
11914be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL,
12014be3200SRob Clark 			MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) |
12114be3200SRob Clark 			MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal));
12214be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period);
12314be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len);
12414be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL,
12514be3200SRob Clark 			MDP4_DTV_DISPLAY_HCTRL_START(hsync_start_x) |
12614be3200SRob Clark 			MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x));
12714be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start);
12814be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end);
12914be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0);
13014be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR,
13114be3200SRob Clark 			MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY |
13214be3200SRob Clark 			MDP4_DTV_UNDERFLOW_CLR_COLOR(0xff));
13314be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew);
13414be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol);
13514be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL,
13614be3200SRob Clark 			MDP4_DTV_ACTIVE_HCTL_START(0) |
13714be3200SRob Clark 			MDP4_DTV_ACTIVE_HCTL_END(0));
13814be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0);
13914be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0);
14014be3200SRob Clark }
14114be3200SRob Clark 
14214be3200SRob Clark static void mdp4_dtv_encoder_disable(struct drm_encoder *encoder)
14314be3200SRob Clark {
14414be3200SRob Clark 	struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
14514be3200SRob Clark 	struct mdp4_kms *mdp4_kms = get_kms(encoder);
14614be3200SRob Clark 
14714be3200SRob Clark 	if (WARN_ON(!mdp4_dtv_encoder->enabled))
14814be3200SRob Clark 		return;
14914be3200SRob Clark 
15014be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
15114be3200SRob Clark 
15214be3200SRob Clark 	/*
15314be3200SRob Clark 	 * Wait for a vsync so we know the ENABLE=0 latched before
15414be3200SRob Clark 	 * the (connector) source of the vsync's gets disabled,
15514be3200SRob Clark 	 * otherwise we end up in a funny state if we re-enable
15614be3200SRob Clark 	 * before the disable latches, which results that some of
15714be3200SRob Clark 	 * the settings changes for the new modeset (like new
15814be3200SRob Clark 	 * scanout buffer) don't latch properly..
15914be3200SRob Clark 	 */
16014be3200SRob Clark 	mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC);
16114be3200SRob Clark 
16214be3200SRob Clark 	clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk);
16314be3200SRob Clark 	clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk);
16414be3200SRob Clark 
16514be3200SRob Clark 	bs_set(mdp4_dtv_encoder, 0);
16614be3200SRob Clark 
16714be3200SRob Clark 	mdp4_dtv_encoder->enabled = false;
16814be3200SRob Clark }
16914be3200SRob Clark 
17014be3200SRob Clark static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder)
17114be3200SRob Clark {
17214be3200SRob Clark 	struct drm_device *dev = encoder->dev;
17314be3200SRob Clark 	struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
17414be3200SRob Clark 	struct mdp4_kms *mdp4_kms = get_kms(encoder);
17514be3200SRob Clark 	unsigned long pc = mdp4_dtv_encoder->pixclock;
17614be3200SRob Clark 	int ret;
17714be3200SRob Clark 
17814be3200SRob Clark 	if (WARN_ON(mdp4_dtv_encoder->enabled))
17914be3200SRob Clark 		return;
18014be3200SRob Clark 
18114be3200SRob Clark 	mdp4_crtc_set_config(encoder->crtc,
18214be3200SRob Clark 			MDP4_DMA_CONFIG_R_BPC(BPC8) |
18314be3200SRob Clark 			MDP4_DMA_CONFIG_G_BPC(BPC8) |
18414be3200SRob Clark 			MDP4_DMA_CONFIG_B_BPC(BPC8) |
18514be3200SRob Clark 			MDP4_DMA_CONFIG_PACK(0x21));
18614be3200SRob Clark 	mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 1);
18714be3200SRob Clark 
18814be3200SRob Clark 	bs_set(mdp4_dtv_encoder, 1);
18914be3200SRob Clark 
19014be3200SRob Clark 	DBG("setting mdp_clk=%lu", pc);
19114be3200SRob Clark 
19214be3200SRob Clark 	ret = clk_set_rate(mdp4_dtv_encoder->mdp_clk, pc);
19314be3200SRob Clark 	if (ret)
1946a41da17SMamta Shukla 		DRM_DEV_ERROR(dev->dev, "failed to set mdp_clk to %lu: %d\n",
19514be3200SRob Clark 			pc, ret);
19614be3200SRob Clark 
19714be3200SRob Clark 	ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk);
19814be3200SRob Clark 	if (ret)
1996a41da17SMamta Shukla 		DRM_DEV_ERROR(dev->dev, "failed to enabled mdp_clk: %d\n", ret);
20014be3200SRob Clark 
20114be3200SRob Clark 	ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk);
20214be3200SRob Clark 	if (ret)
2036a41da17SMamta Shukla 		DRM_DEV_ERROR(dev->dev, "failed to enable hdmi_clk: %d\n", ret);
20414be3200SRob Clark 
20514be3200SRob Clark 	mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1);
20614be3200SRob Clark 
20714be3200SRob Clark 	mdp4_dtv_encoder->enabled = true;
20814be3200SRob Clark }
20914be3200SRob Clark 
21014be3200SRob Clark static const struct drm_encoder_helper_funcs mdp4_dtv_encoder_helper_funcs = {
21114be3200SRob Clark 	.mode_set = mdp4_dtv_encoder_mode_set,
21214be3200SRob Clark 	.enable = mdp4_dtv_encoder_enable,
21314be3200SRob Clark 	.disable = mdp4_dtv_encoder_disable,
21414be3200SRob Clark };
21514be3200SRob Clark 
21614be3200SRob Clark long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate)
21714be3200SRob Clark {
21814be3200SRob Clark 	struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
21914be3200SRob Clark 	return clk_round_rate(mdp4_dtv_encoder->mdp_clk, rate);
22014be3200SRob Clark }
22114be3200SRob Clark 
22214be3200SRob Clark /* initialize encoder */
22314be3200SRob Clark struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev)
22414be3200SRob Clark {
22514be3200SRob Clark 	struct drm_encoder *encoder = NULL;
22614be3200SRob Clark 	struct mdp4_dtv_encoder *mdp4_dtv_encoder;
22714be3200SRob Clark 	int ret;
22814be3200SRob Clark 
22914be3200SRob Clark 	mdp4_dtv_encoder = kzalloc(sizeof(*mdp4_dtv_encoder), GFP_KERNEL);
23014be3200SRob Clark 	if (!mdp4_dtv_encoder) {
23114be3200SRob Clark 		ret = -ENOMEM;
23214be3200SRob Clark 		goto fail;
23314be3200SRob Clark 	}
23414be3200SRob Clark 
23514be3200SRob Clark 	encoder = &mdp4_dtv_encoder->base;
23614be3200SRob Clark 
23714be3200SRob Clark 	drm_encoder_init(dev, encoder, &mdp4_dtv_encoder_funcs,
23814be3200SRob Clark 			 DRM_MODE_ENCODER_TMDS, NULL);
23914be3200SRob Clark 	drm_encoder_helper_add(encoder, &mdp4_dtv_encoder_helper_funcs);
24014be3200SRob Clark 
24114be3200SRob Clark 	mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk");
24214be3200SRob Clark 	if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) {
2436a41da17SMamta Shukla 		DRM_DEV_ERROR(dev->dev, "failed to get hdmi_clk\n");
24414be3200SRob Clark 		ret = PTR_ERR(mdp4_dtv_encoder->hdmi_clk);
24514be3200SRob Clark 		goto fail;
24614be3200SRob Clark 	}
24714be3200SRob Clark 
24814be3200SRob Clark 	mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "tv_clk");
24914be3200SRob Clark 	if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) {
2506a41da17SMamta Shukla 		DRM_DEV_ERROR(dev->dev, "failed to get tv_clk\n");
25114be3200SRob Clark 		ret = PTR_ERR(mdp4_dtv_encoder->mdp_clk);
25214be3200SRob Clark 		goto fail;
25314be3200SRob Clark 	}
25414be3200SRob Clark 
25514be3200SRob Clark 	bs_init(mdp4_dtv_encoder);
25614be3200SRob Clark 
25714be3200SRob Clark 	return encoder;
25814be3200SRob Clark 
25914be3200SRob Clark fail:
26014be3200SRob Clark 	if (encoder)
26114be3200SRob Clark 		mdp4_dtv_encoder_destroy(encoder);
26214be3200SRob Clark 
26314be3200SRob Clark 	return ERR_PTR(ret);
26414be3200SRob Clark }
265