114be3200SRob Clark /* 214be3200SRob Clark * Copyright (C) 2013 Red Hat 314be3200SRob Clark * Author: Rob Clark <robdclark@gmail.com> 414be3200SRob Clark * 514be3200SRob Clark * This program is free software; you can redistribute it and/or modify it 614be3200SRob Clark * under the terms of the GNU General Public License version 2 as published by 714be3200SRob Clark * the Free Software Foundation. 814be3200SRob Clark * 914be3200SRob Clark * This program is distributed in the hope that it will be useful, but WITHOUT 1014be3200SRob Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1114be3200SRob Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1214be3200SRob Clark * more details. 1314be3200SRob Clark * 1414be3200SRob Clark * You should have received a copy of the GNU General Public License along with 1514be3200SRob Clark * this program. If not, see <http://www.gnu.org/licenses/>. 1614be3200SRob Clark */ 1714be3200SRob Clark 1814be3200SRob Clark #include <drm/drm_crtc.h> 1914be3200SRob Clark #include <drm/drm_crtc_helper.h> 2014be3200SRob Clark 2114be3200SRob Clark #include "mdp4_kms.h" 2214be3200SRob Clark 2314be3200SRob Clark struct mdp4_dtv_encoder { 2414be3200SRob Clark struct drm_encoder base; 2514be3200SRob Clark struct clk *hdmi_clk; 2614be3200SRob Clark struct clk *mdp_clk; 2714be3200SRob Clark unsigned long int pixclock; 2814be3200SRob Clark bool enabled; 2914be3200SRob Clark uint32_t bsc; 3014be3200SRob Clark }; 3114be3200SRob Clark #define to_mdp4_dtv_encoder(x) container_of(x, struct mdp4_dtv_encoder, base) 3214be3200SRob Clark 3314be3200SRob Clark static struct mdp4_kms *get_kms(struct drm_encoder *encoder) 3414be3200SRob Clark { 3514be3200SRob Clark struct msm_drm_private *priv = encoder->dev->dev_private; 3614be3200SRob Clark return to_mdp4_kms(to_mdp_kms(priv->kms)); 3714be3200SRob Clark } 3814be3200SRob Clark 3914be3200SRob Clark #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING 4014be3200SRob Clark #include <mach/board.h> 4114be3200SRob Clark /* not ironically named at all.. no, really.. */ 4214be3200SRob Clark static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) 4314be3200SRob Clark { 4414be3200SRob Clark struct drm_device *dev = mdp4_dtv_encoder->base.dev; 4514be3200SRob Clark struct lcdc_platform_data *dtv_pdata = mdp4_find_pdata("dtv.0"); 4614be3200SRob Clark 4714be3200SRob Clark if (!dtv_pdata) { 4814be3200SRob Clark dev_err(dev->dev, "could not find dtv pdata\n"); 4914be3200SRob Clark return; 5014be3200SRob Clark } 5114be3200SRob Clark 5214be3200SRob Clark if (dtv_pdata->bus_scale_table) { 5314be3200SRob Clark mdp4_dtv_encoder->bsc = msm_bus_scale_register_client( 5414be3200SRob Clark dtv_pdata->bus_scale_table); 5514be3200SRob Clark DBG("bus scale client: %08x", mdp4_dtv_encoder->bsc); 5614be3200SRob Clark DBG("lcdc_power_save: %p", dtv_pdata->lcdc_power_save); 5714be3200SRob Clark if (dtv_pdata->lcdc_power_save) 5814be3200SRob Clark dtv_pdata->lcdc_power_save(1); 5914be3200SRob Clark } 6014be3200SRob Clark } 6114be3200SRob Clark 6214be3200SRob Clark static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder) 6314be3200SRob Clark { 6414be3200SRob Clark if (mdp4_dtv_encoder->bsc) { 6514be3200SRob Clark msm_bus_scale_unregister_client(mdp4_dtv_encoder->bsc); 6614be3200SRob Clark mdp4_dtv_encoder->bsc = 0; 6714be3200SRob Clark } 6814be3200SRob Clark } 6914be3200SRob Clark 7014be3200SRob Clark static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx) 7114be3200SRob Clark { 7214be3200SRob Clark if (mdp4_dtv_encoder->bsc) { 7314be3200SRob Clark DBG("set bus scaling: %d", idx); 7414be3200SRob Clark msm_bus_scale_client_update_request(mdp4_dtv_encoder->bsc, idx); 7514be3200SRob Clark } 7614be3200SRob Clark } 7714be3200SRob Clark #else 7814be3200SRob Clark static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {} 7914be3200SRob Clark static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {} 8014be3200SRob Clark static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx) {} 8114be3200SRob Clark #endif 8214be3200SRob Clark 8314be3200SRob Clark static void mdp4_dtv_encoder_destroy(struct drm_encoder *encoder) 8414be3200SRob Clark { 8514be3200SRob Clark struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 8614be3200SRob Clark bs_fini(mdp4_dtv_encoder); 8714be3200SRob Clark drm_encoder_cleanup(encoder); 8814be3200SRob Clark kfree(mdp4_dtv_encoder); 8914be3200SRob Clark } 9014be3200SRob Clark 9114be3200SRob Clark static const struct drm_encoder_funcs mdp4_dtv_encoder_funcs = { 9214be3200SRob Clark .destroy = mdp4_dtv_encoder_destroy, 9314be3200SRob Clark }; 9414be3200SRob Clark 9514be3200SRob Clark static void mdp4_dtv_encoder_mode_set(struct drm_encoder *encoder, 9614be3200SRob Clark struct drm_display_mode *mode, 9714be3200SRob Clark struct drm_display_mode *adjusted_mode) 9814be3200SRob Clark { 9914be3200SRob Clark struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 10014be3200SRob Clark struct mdp4_kms *mdp4_kms = get_kms(encoder); 10114be3200SRob Clark uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; 10214be3200SRob Clark uint32_t display_v_start, display_v_end; 10314be3200SRob Clark uint32_t hsync_start_x, hsync_end_x; 10414be3200SRob Clark 10514be3200SRob Clark mode = adjusted_mode; 10614be3200SRob Clark 1077510a9c6SShayenne Moura DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode)); 10814be3200SRob Clark 10914be3200SRob Clark mdp4_dtv_encoder->pixclock = mode->clock * 1000; 11014be3200SRob Clark 11114be3200SRob Clark DBG("pixclock=%lu", mdp4_dtv_encoder->pixclock); 11214be3200SRob Clark 11314be3200SRob Clark ctrl_pol = 0; 11414be3200SRob Clark if (mode->flags & DRM_MODE_FLAG_NHSYNC) 11514be3200SRob Clark ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW; 11614be3200SRob Clark if (mode->flags & DRM_MODE_FLAG_NVSYNC) 11714be3200SRob Clark ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW; 11814be3200SRob Clark /* probably need to get DATA_EN polarity from panel.. */ 11914be3200SRob Clark 12014be3200SRob Clark dtv_hsync_skew = 0; /* get this from panel? */ 12114be3200SRob Clark 12214be3200SRob Clark hsync_start_x = (mode->htotal - mode->hsync_start); 12314be3200SRob Clark hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; 12414be3200SRob Clark 12514be3200SRob Clark vsync_period = mode->vtotal * mode->htotal; 12614be3200SRob Clark vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal; 12714be3200SRob Clark display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew; 12814be3200SRob Clark display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1; 12914be3200SRob Clark 13014be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, 13114be3200SRob Clark MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) | 13214be3200SRob Clark MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal)); 13314be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); 13414be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); 13514be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, 13614be3200SRob Clark MDP4_DTV_DISPLAY_HCTRL_START(hsync_start_x) | 13714be3200SRob Clark MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x)); 13814be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); 13914be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); 14014be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); 14114be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, 14214be3200SRob Clark MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY | 14314be3200SRob Clark MDP4_DTV_UNDERFLOW_CLR_COLOR(0xff)); 14414be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew); 14514be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol); 14614be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL, 14714be3200SRob Clark MDP4_DTV_ACTIVE_HCTL_START(0) | 14814be3200SRob Clark MDP4_DTV_ACTIVE_HCTL_END(0)); 14914be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0); 15014be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0); 15114be3200SRob Clark } 15214be3200SRob Clark 15314be3200SRob Clark static void mdp4_dtv_encoder_disable(struct drm_encoder *encoder) 15414be3200SRob Clark { 15514be3200SRob Clark struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 15614be3200SRob Clark struct mdp4_kms *mdp4_kms = get_kms(encoder); 15714be3200SRob Clark 15814be3200SRob Clark if (WARN_ON(!mdp4_dtv_encoder->enabled)) 15914be3200SRob Clark return; 16014be3200SRob Clark 16114be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 16214be3200SRob Clark 16314be3200SRob Clark /* 16414be3200SRob Clark * Wait for a vsync so we know the ENABLE=0 latched before 16514be3200SRob Clark * the (connector) source of the vsync's gets disabled, 16614be3200SRob Clark * otherwise we end up in a funny state if we re-enable 16714be3200SRob Clark * before the disable latches, which results that some of 16814be3200SRob Clark * the settings changes for the new modeset (like new 16914be3200SRob Clark * scanout buffer) don't latch properly.. 17014be3200SRob Clark */ 17114be3200SRob Clark mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC); 17214be3200SRob Clark 17314be3200SRob Clark clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk); 17414be3200SRob Clark clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk); 17514be3200SRob Clark 17614be3200SRob Clark bs_set(mdp4_dtv_encoder, 0); 17714be3200SRob Clark 17814be3200SRob Clark mdp4_dtv_encoder->enabled = false; 17914be3200SRob Clark } 18014be3200SRob Clark 18114be3200SRob Clark static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder) 18214be3200SRob Clark { 18314be3200SRob Clark struct drm_device *dev = encoder->dev; 18414be3200SRob Clark struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 18514be3200SRob Clark struct mdp4_kms *mdp4_kms = get_kms(encoder); 18614be3200SRob Clark unsigned long pc = mdp4_dtv_encoder->pixclock; 18714be3200SRob Clark int ret; 18814be3200SRob Clark 18914be3200SRob Clark if (WARN_ON(mdp4_dtv_encoder->enabled)) 19014be3200SRob Clark return; 19114be3200SRob Clark 19214be3200SRob Clark mdp4_crtc_set_config(encoder->crtc, 19314be3200SRob Clark MDP4_DMA_CONFIG_R_BPC(BPC8) | 19414be3200SRob Clark MDP4_DMA_CONFIG_G_BPC(BPC8) | 19514be3200SRob Clark MDP4_DMA_CONFIG_B_BPC(BPC8) | 19614be3200SRob Clark MDP4_DMA_CONFIG_PACK(0x21)); 19714be3200SRob Clark mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 1); 19814be3200SRob Clark 19914be3200SRob Clark bs_set(mdp4_dtv_encoder, 1); 20014be3200SRob Clark 20114be3200SRob Clark DBG("setting mdp_clk=%lu", pc); 20214be3200SRob Clark 20314be3200SRob Clark ret = clk_set_rate(mdp4_dtv_encoder->mdp_clk, pc); 20414be3200SRob Clark if (ret) 20514be3200SRob Clark dev_err(dev->dev, "failed to set mdp_clk to %lu: %d\n", 20614be3200SRob Clark pc, ret); 20714be3200SRob Clark 20814be3200SRob Clark ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk); 20914be3200SRob Clark if (ret) 21014be3200SRob Clark dev_err(dev->dev, "failed to enabled mdp_clk: %d\n", ret); 21114be3200SRob Clark 21214be3200SRob Clark ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk); 21314be3200SRob Clark if (ret) 21414be3200SRob Clark dev_err(dev->dev, "failed to enable hdmi_clk: %d\n", ret); 21514be3200SRob Clark 21614be3200SRob Clark mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1); 21714be3200SRob Clark 21814be3200SRob Clark mdp4_dtv_encoder->enabled = true; 21914be3200SRob Clark } 22014be3200SRob Clark 22114be3200SRob Clark static const struct drm_encoder_helper_funcs mdp4_dtv_encoder_helper_funcs = { 22214be3200SRob Clark .mode_set = mdp4_dtv_encoder_mode_set, 22314be3200SRob Clark .enable = mdp4_dtv_encoder_enable, 22414be3200SRob Clark .disable = mdp4_dtv_encoder_disable, 22514be3200SRob Clark }; 22614be3200SRob Clark 22714be3200SRob Clark long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate) 22814be3200SRob Clark { 22914be3200SRob Clark struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); 23014be3200SRob Clark return clk_round_rate(mdp4_dtv_encoder->mdp_clk, rate); 23114be3200SRob Clark } 23214be3200SRob Clark 23314be3200SRob Clark /* initialize encoder */ 23414be3200SRob Clark struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev) 23514be3200SRob Clark { 23614be3200SRob Clark struct drm_encoder *encoder = NULL; 23714be3200SRob Clark struct mdp4_dtv_encoder *mdp4_dtv_encoder; 23814be3200SRob Clark int ret; 23914be3200SRob Clark 24014be3200SRob Clark mdp4_dtv_encoder = kzalloc(sizeof(*mdp4_dtv_encoder), GFP_KERNEL); 24114be3200SRob Clark if (!mdp4_dtv_encoder) { 24214be3200SRob Clark ret = -ENOMEM; 24314be3200SRob Clark goto fail; 24414be3200SRob Clark } 24514be3200SRob Clark 24614be3200SRob Clark encoder = &mdp4_dtv_encoder->base; 24714be3200SRob Clark 24814be3200SRob Clark drm_encoder_init(dev, encoder, &mdp4_dtv_encoder_funcs, 24914be3200SRob Clark DRM_MODE_ENCODER_TMDS, NULL); 25014be3200SRob Clark drm_encoder_helper_add(encoder, &mdp4_dtv_encoder_helper_funcs); 25114be3200SRob Clark 25214be3200SRob Clark mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk"); 25314be3200SRob Clark if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) { 25414be3200SRob Clark dev_err(dev->dev, "failed to get hdmi_clk\n"); 25514be3200SRob Clark ret = PTR_ERR(mdp4_dtv_encoder->hdmi_clk); 25614be3200SRob Clark goto fail; 25714be3200SRob Clark } 25814be3200SRob Clark 25914be3200SRob Clark mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "tv_clk"); 26014be3200SRob Clark if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) { 26114be3200SRob Clark dev_err(dev->dev, "failed to get tv_clk\n"); 26214be3200SRob Clark ret = PTR_ERR(mdp4_dtv_encoder->mdp_clk); 26314be3200SRob Clark goto fail; 26414be3200SRob Clark } 26514be3200SRob Clark 26614be3200SRob Clark bs_init(mdp4_dtv_encoder); 26714be3200SRob Clark 26814be3200SRob Clark return encoder; 26914be3200SRob Clark 27014be3200SRob Clark fail: 27114be3200SRob Clark if (encoder) 27214be3200SRob Clark mdp4_dtv_encoder_destroy(encoder); 27314be3200SRob Clark 27414be3200SRob Clark return ERR_PTR(ret); 27514be3200SRob Clark } 276