1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License version 2 as published by
7  * the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17 
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_mode.h>
22 
23 #include "mdp4_kms.h"
24 
25 struct mdp4_crtc {
26 	struct drm_crtc base;
27 	char name[8];
28 	int id;
29 	int ovlp;
30 	enum mdp4_dma dma;
31 	bool enabled;
32 
33 	/* which mixer/encoder we route output to: */
34 	int mixer;
35 
36 	struct {
37 		spinlock_t lock;
38 		bool stale;
39 		uint32_t width, height;
40 		uint32_t x, y;
41 
42 		/* next cursor to scan-out: */
43 		uint32_t next_iova;
44 		struct drm_gem_object *next_bo;
45 
46 		/* current cursor being scanned out: */
47 		struct drm_gem_object *scanout_bo;
48 	} cursor;
49 
50 
51 	/* if there is a pending flip, these will be non-null: */
52 	struct drm_pending_vblank_event *event;
53 
54 	/* Bits have been flushed at the last commit,
55 	 * used to decide if a vsync has happened since last commit.
56 	 */
57 	u32 flushed_mask;
58 
59 #define PENDING_CURSOR 0x1
60 #define PENDING_FLIP   0x2
61 	atomic_t pending;
62 
63 	/* for unref'ing cursor bo's after scanout completes: */
64 	struct drm_flip_work unref_cursor_work;
65 
66 	struct mdp_irq vblank;
67 	struct mdp_irq err;
68 };
69 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
70 
71 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
72 {
73 	struct msm_drm_private *priv = crtc->dev->dev_private;
74 	return to_mdp4_kms(to_mdp_kms(priv->kms));
75 }
76 
77 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
78 {
79 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
80 
81 	atomic_or(pending, &mdp4_crtc->pending);
82 	mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
83 }
84 
85 static void crtc_flush(struct drm_crtc *crtc)
86 {
87 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
88 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
89 	struct drm_plane *plane;
90 	uint32_t flush = 0;
91 
92 	drm_atomic_crtc_for_each_plane(plane, crtc) {
93 		enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
94 		flush |= pipe2flush(pipe_id);
95 	}
96 
97 	flush |= ovlp2flush(mdp4_crtc->ovlp);
98 
99 	DBG("%s: flush=%08x", mdp4_crtc->name, flush);
100 
101 	mdp4_crtc->flushed_mask = flush;
102 
103 	mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
104 }
105 
106 /* if file!=NULL, this is preclose potential cancel-flip path */
107 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
108 {
109 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
110 	struct drm_device *dev = crtc->dev;
111 	struct drm_pending_vblank_event *event;
112 	unsigned long flags;
113 
114 	spin_lock_irqsave(&dev->event_lock, flags);
115 	event = mdp4_crtc->event;
116 	if (event) {
117 		mdp4_crtc->event = NULL;
118 		DBG("%s: send event: %p", mdp4_crtc->name, event);
119 		drm_crtc_send_vblank_event(crtc, event);
120 	}
121 	spin_unlock_irqrestore(&dev->event_lock, flags);
122 }
123 
124 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
125 {
126 	struct mdp4_crtc *mdp4_crtc =
127 		container_of(work, struct mdp4_crtc, unref_cursor_work);
128 	struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
129 	struct msm_kms *kms = &mdp4_kms->base.base;
130 
131 	msm_gem_put_iova(val, kms->aspace);
132 	drm_gem_object_put_unlocked(val);
133 }
134 
135 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
136 {
137 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
138 
139 	drm_crtc_cleanup(crtc);
140 	drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
141 
142 	kfree(mdp4_crtc);
143 }
144 
145 /* statically (for now) map planes to mixer stage (z-order): */
146 static const int idxs[] = {
147 		[VG1]  = 1,
148 		[VG2]  = 2,
149 		[RGB1] = 0,
150 		[RGB2] = 0,
151 		[RGB3] = 0,
152 		[VG3]  = 3,
153 		[VG4]  = 4,
154 
155 };
156 
157 /* setup mixer config, for which we need to consider all crtc's and
158  * the planes attached to them
159  *
160  * TODO may possibly need some extra locking here
161  */
162 static void setup_mixer(struct mdp4_kms *mdp4_kms)
163 {
164 	struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
165 	struct drm_crtc *crtc;
166 	uint32_t mixer_cfg = 0;
167 	static const enum mdp_mixer_stage_id stages[] = {
168 			STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
169 	};
170 
171 	list_for_each_entry(crtc, &config->crtc_list, head) {
172 		struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
173 		struct drm_plane *plane;
174 
175 		drm_atomic_crtc_for_each_plane(plane, crtc) {
176 			enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
177 			int idx = idxs[pipe_id];
178 			mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
179 					pipe_id, stages[idx]);
180 		}
181 	}
182 
183 	mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
184 }
185 
186 static void blend_setup(struct drm_crtc *crtc)
187 {
188 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
189 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
190 	struct drm_plane *plane;
191 	int i, ovlp = mdp4_crtc->ovlp;
192 	bool alpha[4]= { false, false, false, false };
193 
194 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
195 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
196 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
197 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
198 
199 	drm_atomic_crtc_for_each_plane(plane, crtc) {
200 		enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
201 		int idx = idxs[pipe_id];
202 		if (idx > 0) {
203 			const struct mdp_format *format =
204 					to_mdp_format(msm_framebuffer_format(plane->fb));
205 			alpha[idx-1] = format->alpha_enable;
206 		}
207 	}
208 
209 	for (i = 0; i < 4; i++) {
210 		uint32_t op;
211 
212 		if (alpha[i]) {
213 			op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
214 					MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
215 					MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
216 		} else {
217 			op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
218 					MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
219 		}
220 
221 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
222 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
223 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
224 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
225 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
226 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
227 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
228 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
229 	}
230 
231 	setup_mixer(mdp4_kms);
232 }
233 
234 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
235 {
236 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
237 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
238 	enum mdp4_dma dma = mdp4_crtc->dma;
239 	int ovlp = mdp4_crtc->ovlp;
240 	struct drm_display_mode *mode;
241 
242 	if (WARN_ON(!crtc->state))
243 		return;
244 
245 	mode = &crtc->state->adjusted_mode;
246 
247 	DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
248 			mdp4_crtc->name, mode->base.id, mode->name,
249 			mode->vrefresh, mode->clock,
250 			mode->hdisplay, mode->hsync_start,
251 			mode->hsync_end, mode->htotal,
252 			mode->vdisplay, mode->vsync_start,
253 			mode->vsync_end, mode->vtotal,
254 			mode->type, mode->flags);
255 
256 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
257 			MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
258 			MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
259 
260 	/* take data from pipe: */
261 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
262 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
263 	mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
264 			MDP4_DMA_DST_SIZE_WIDTH(0) |
265 			MDP4_DMA_DST_SIZE_HEIGHT(0));
266 
267 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
268 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
269 			MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
270 			MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
271 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
272 
273 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
274 
275 	if (dma == DMA_E) {
276 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
277 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
278 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
279 	}
280 }
281 
282 static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,
283 				     struct drm_crtc_state *old_state)
284 {
285 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
286 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
287 
288 	DBG("%s", mdp4_crtc->name);
289 
290 	if (WARN_ON(!mdp4_crtc->enabled))
291 		return;
292 
293 	/* Disable/save vblank irq handling before power is disabled */
294 	drm_crtc_vblank_off(crtc);
295 
296 	mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
297 	mdp4_disable(mdp4_kms);
298 
299 	mdp4_crtc->enabled = false;
300 }
301 
302 static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc,
303 				    struct drm_crtc_state *old_state)
304 {
305 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
306 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
307 
308 	DBG("%s", mdp4_crtc->name);
309 
310 	if (WARN_ON(mdp4_crtc->enabled))
311 		return;
312 
313 	mdp4_enable(mdp4_kms);
314 
315 	/* Restore vblank irq handling after power is enabled */
316 	drm_crtc_vblank_on(crtc);
317 
318 	mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
319 
320 	crtc_flush(crtc);
321 
322 	mdp4_crtc->enabled = true;
323 }
324 
325 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
326 		struct drm_crtc_state *state)
327 {
328 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
329 	DBG("%s: check", mdp4_crtc->name);
330 	// TODO anything else to check?
331 	return 0;
332 }
333 
334 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,
335 				   struct drm_crtc_state *old_crtc_state)
336 {
337 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
338 	DBG("%s: begin", mdp4_crtc->name);
339 }
340 
341 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
342 				   struct drm_crtc_state *old_crtc_state)
343 {
344 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
345 	struct drm_device *dev = crtc->dev;
346 	unsigned long flags;
347 
348 	DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
349 
350 	WARN_ON(mdp4_crtc->event);
351 
352 	spin_lock_irqsave(&dev->event_lock, flags);
353 	mdp4_crtc->event = crtc->state->event;
354 	crtc->state->event = NULL;
355 	spin_unlock_irqrestore(&dev->event_lock, flags);
356 
357 	blend_setup(crtc);
358 	crtc_flush(crtc);
359 	request_pending(crtc, PENDING_FLIP);
360 }
361 
362 #define CURSOR_WIDTH 64
363 #define CURSOR_HEIGHT 64
364 
365 /* called from IRQ to update cursor related registers (if needed).  The
366  * cursor registers, other than x/y position, appear not to be double
367  * buffered, and changing them other than from vblank seems to trigger
368  * underflow.
369  */
370 static void update_cursor(struct drm_crtc *crtc)
371 {
372 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
373 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
374 	struct msm_kms *kms = &mdp4_kms->base.base;
375 	enum mdp4_dma dma = mdp4_crtc->dma;
376 	unsigned long flags;
377 
378 	spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
379 	if (mdp4_crtc->cursor.stale) {
380 		struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
381 		struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
382 		uint64_t iova = mdp4_crtc->cursor.next_iova;
383 
384 		if (next_bo) {
385 			/* take a obj ref + iova ref when we start scanning out: */
386 			drm_gem_object_get(next_bo);
387 			msm_gem_get_iova(next_bo, kms->aspace, &iova);
388 
389 			/* enable cursor: */
390 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
391 					MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
392 					MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
393 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
394 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
395 					MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
396 					MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
397 		} else {
398 			/* disable cursor: */
399 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
400 					mdp4_kms->blank_cursor_iova);
401 		}
402 
403 		/* and drop the iova ref + obj rev when done scanning out: */
404 		if (prev_bo)
405 			drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
406 
407 		mdp4_crtc->cursor.scanout_bo = next_bo;
408 		mdp4_crtc->cursor.stale = false;
409 	}
410 
411 	mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
412 			MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
413 			MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
414 
415 	spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
416 }
417 
418 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
419 		struct drm_file *file_priv, uint32_t handle,
420 		uint32_t width, uint32_t height)
421 {
422 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
423 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
424 	struct msm_kms *kms = &mdp4_kms->base.base;
425 	struct drm_device *dev = crtc->dev;
426 	struct drm_gem_object *cursor_bo, *old_bo;
427 	unsigned long flags;
428 	uint64_t iova;
429 	int ret;
430 
431 	if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
432 		dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
433 		return -EINVAL;
434 	}
435 
436 	if (handle) {
437 		cursor_bo = drm_gem_object_lookup(file_priv, handle);
438 		if (!cursor_bo)
439 			return -ENOENT;
440 	} else {
441 		cursor_bo = NULL;
442 	}
443 
444 	if (cursor_bo) {
445 		ret = msm_gem_get_iova(cursor_bo, kms->aspace, &iova);
446 		if (ret)
447 			goto fail;
448 	} else {
449 		iova = 0;
450 	}
451 
452 	spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
453 	old_bo = mdp4_crtc->cursor.next_bo;
454 	mdp4_crtc->cursor.next_bo   = cursor_bo;
455 	mdp4_crtc->cursor.next_iova = iova;
456 	mdp4_crtc->cursor.width     = width;
457 	mdp4_crtc->cursor.height    = height;
458 	mdp4_crtc->cursor.stale     = true;
459 	spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
460 
461 	if (old_bo) {
462 		/* drop our previous reference: */
463 		drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
464 	}
465 
466 	request_pending(crtc, PENDING_CURSOR);
467 
468 	return 0;
469 
470 fail:
471 	drm_gem_object_put_unlocked(cursor_bo);
472 	return ret;
473 }
474 
475 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
476 {
477 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
478 	unsigned long flags;
479 
480 	spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
481 	mdp4_crtc->cursor.x = x;
482 	mdp4_crtc->cursor.y = y;
483 	spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
484 
485 	crtc_flush(crtc);
486 	request_pending(crtc, PENDING_CURSOR);
487 
488 	return 0;
489 }
490 
491 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
492 	.set_config = drm_atomic_helper_set_config,
493 	.destroy = mdp4_crtc_destroy,
494 	.page_flip = drm_atomic_helper_page_flip,
495 	.cursor_set = mdp4_crtc_cursor_set,
496 	.cursor_move = mdp4_crtc_cursor_move,
497 	.reset = drm_atomic_helper_crtc_reset,
498 	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
499 	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
500 };
501 
502 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
503 	.mode_set_nofb = mdp4_crtc_mode_set_nofb,
504 	.atomic_check = mdp4_crtc_atomic_check,
505 	.atomic_begin = mdp4_crtc_atomic_begin,
506 	.atomic_flush = mdp4_crtc_atomic_flush,
507 	.atomic_enable = mdp4_crtc_atomic_enable,
508 	.atomic_disable = mdp4_crtc_atomic_disable,
509 };
510 
511 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
512 {
513 	struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
514 	struct drm_crtc *crtc = &mdp4_crtc->base;
515 	struct msm_drm_private *priv = crtc->dev->dev_private;
516 	unsigned pending;
517 
518 	mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
519 
520 	pending = atomic_xchg(&mdp4_crtc->pending, 0);
521 
522 	if (pending & PENDING_FLIP) {
523 		complete_flip(crtc, NULL);
524 	}
525 
526 	if (pending & PENDING_CURSOR) {
527 		update_cursor(crtc);
528 		drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
529 	}
530 }
531 
532 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
533 {
534 	struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
535 	struct drm_crtc *crtc = &mdp4_crtc->base;
536 	DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
537 	crtc_flush(crtc);
538 }
539 
540 static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
541 {
542 	struct drm_device *dev = crtc->dev;
543 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
544 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
545 	int ret;
546 
547 	ret = drm_crtc_vblank_get(crtc);
548 	if (ret)
549 		return;
550 
551 	ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
552 		!(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
553 			mdp4_crtc->flushed_mask),
554 		msecs_to_jiffies(50));
555 	if (ret <= 0)
556 		dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
557 
558 	mdp4_crtc->flushed_mask = 0;
559 
560 	drm_crtc_vblank_put(crtc);
561 }
562 
563 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
564 {
565 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
566 	return mdp4_crtc->vblank.irqmask;
567 }
568 
569 /* set dma config, ie. the format the encoder wants. */
570 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
571 {
572 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
573 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
574 
575 	mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
576 }
577 
578 /* set interface for routing crtc->encoder: */
579 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
580 {
581 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
582 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
583 	uint32_t intf_sel;
584 
585 	intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
586 
587 	switch (mdp4_crtc->dma) {
588 	case DMA_P:
589 		intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
590 		intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
591 		break;
592 	case DMA_S:
593 		intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
594 		intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
595 		break;
596 	case DMA_E:
597 		intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
598 		intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
599 		break;
600 	}
601 
602 	if (intf == INTF_DSI_VIDEO) {
603 		intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
604 		intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
605 	} else if (intf == INTF_DSI_CMD) {
606 		intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
607 		intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
608 	}
609 
610 	mdp4_crtc->mixer = mixer;
611 
612 	blend_setup(crtc);
613 
614 	DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
615 
616 	mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
617 }
618 
619 void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
620 {
621 	/* wait_for_flush_done is the only case for now.
622 	 * Later we will have command mode CRTC to wait for
623 	 * other event.
624 	 */
625 	mdp4_crtc_wait_for_flush_done(crtc);
626 }
627 
628 static const char *dma_names[] = {
629 		"DMA_P", "DMA_S", "DMA_E",
630 };
631 
632 /* initialize crtc */
633 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
634 		struct drm_plane *plane, int id, int ovlp_id,
635 		enum mdp4_dma dma_id)
636 {
637 	struct drm_crtc *crtc = NULL;
638 	struct mdp4_crtc *mdp4_crtc;
639 
640 	mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
641 	if (!mdp4_crtc)
642 		return ERR_PTR(-ENOMEM);
643 
644 	crtc = &mdp4_crtc->base;
645 
646 	mdp4_crtc->id = id;
647 
648 	mdp4_crtc->ovlp = ovlp_id;
649 	mdp4_crtc->dma = dma_id;
650 
651 	mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
652 	mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
653 
654 	mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
655 	mdp4_crtc->err.irq = mdp4_crtc_err_irq;
656 
657 	snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
658 			dma_names[dma_id], ovlp_id);
659 
660 	spin_lock_init(&mdp4_crtc->cursor.lock);
661 
662 	drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
663 			"unref cursor", unref_cursor_worker);
664 
665 	drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs,
666 				  NULL);
667 	drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
668 	plane->crtc = crtc;
669 
670 	return crtc;
671 }
672