1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #include <drm/drm_crtc.h>
8 #include <drm/drm_flip_work.h>
9 #include <drm/drm_mode.h>
10 #include <drm/drm_probe_helper.h>
11 #include <drm/drm_vblank.h>
12 
13 #include "mdp4_kms.h"
14 
15 struct mdp4_crtc {
16 	struct drm_crtc base;
17 	char name[8];
18 	int id;
19 	int ovlp;
20 	enum mdp4_dma dma;
21 	bool enabled;
22 
23 	/* which mixer/encoder we route output to: */
24 	int mixer;
25 
26 	struct {
27 		spinlock_t lock;
28 		bool stale;
29 		uint32_t width, height;
30 		uint32_t x, y;
31 
32 		/* next cursor to scan-out: */
33 		uint32_t next_iova;
34 		struct drm_gem_object *next_bo;
35 
36 		/* current cursor being scanned out: */
37 		struct drm_gem_object *scanout_bo;
38 	} cursor;
39 
40 
41 	/* if there is a pending flip, these will be non-null: */
42 	struct drm_pending_vblank_event *event;
43 
44 	/* Bits have been flushed at the last commit,
45 	 * used to decide if a vsync has happened since last commit.
46 	 */
47 	u32 flushed_mask;
48 
49 #define PENDING_CURSOR 0x1
50 #define PENDING_FLIP   0x2
51 	atomic_t pending;
52 
53 	/* for unref'ing cursor bo's after scanout completes: */
54 	struct drm_flip_work unref_cursor_work;
55 
56 	struct mdp_irq vblank;
57 	struct mdp_irq err;
58 };
59 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
60 
61 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
62 {
63 	struct msm_drm_private *priv = crtc->dev->dev_private;
64 	return to_mdp4_kms(to_mdp_kms(priv->kms));
65 }
66 
67 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
68 {
69 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
70 
71 	atomic_or(pending, &mdp4_crtc->pending);
72 	mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
73 }
74 
75 static void crtc_flush(struct drm_crtc *crtc)
76 {
77 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
78 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
79 	struct drm_plane *plane;
80 	uint32_t flush = 0;
81 
82 	drm_atomic_crtc_for_each_plane(plane, crtc) {
83 		enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
84 		flush |= pipe2flush(pipe_id);
85 	}
86 
87 	flush |= ovlp2flush(mdp4_crtc->ovlp);
88 
89 	DBG("%s: flush=%08x", mdp4_crtc->name, flush);
90 
91 	mdp4_crtc->flushed_mask = flush;
92 
93 	mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
94 }
95 
96 /* if file!=NULL, this is preclose potential cancel-flip path */
97 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
98 {
99 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
100 	struct drm_device *dev = crtc->dev;
101 	struct drm_pending_vblank_event *event;
102 	unsigned long flags;
103 
104 	spin_lock_irqsave(&dev->event_lock, flags);
105 	event = mdp4_crtc->event;
106 	if (event) {
107 		mdp4_crtc->event = NULL;
108 		DBG("%s: send event: %p", mdp4_crtc->name, event);
109 		drm_crtc_send_vblank_event(crtc, event);
110 	}
111 	spin_unlock_irqrestore(&dev->event_lock, flags);
112 }
113 
114 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
115 {
116 	struct mdp4_crtc *mdp4_crtc =
117 		container_of(work, struct mdp4_crtc, unref_cursor_work);
118 	struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
119 	struct msm_kms *kms = &mdp4_kms->base.base;
120 
121 	msm_gem_unpin_iova(val, kms->aspace);
122 	drm_gem_object_put_unlocked(val);
123 }
124 
125 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
126 {
127 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
128 
129 	drm_crtc_cleanup(crtc);
130 	drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
131 
132 	kfree(mdp4_crtc);
133 }
134 
135 /* statically (for now) map planes to mixer stage (z-order): */
136 static const int idxs[] = {
137 		[VG1]  = 1,
138 		[VG2]  = 2,
139 		[RGB1] = 0,
140 		[RGB2] = 0,
141 		[RGB3] = 0,
142 		[VG3]  = 3,
143 		[VG4]  = 4,
144 
145 };
146 
147 /* setup mixer config, for which we need to consider all crtc's and
148  * the planes attached to them
149  *
150  * TODO may possibly need some extra locking here
151  */
152 static void setup_mixer(struct mdp4_kms *mdp4_kms)
153 {
154 	struct drm_mode_config *config = &mdp4_kms->dev->mode_config;
155 	struct drm_crtc *crtc;
156 	uint32_t mixer_cfg = 0;
157 	static const enum mdp_mixer_stage_id stages[] = {
158 			STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
159 	};
160 
161 	list_for_each_entry(crtc, &config->crtc_list, head) {
162 		struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
163 		struct drm_plane *plane;
164 
165 		drm_atomic_crtc_for_each_plane(plane, crtc) {
166 			enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
167 			int idx = idxs[pipe_id];
168 			mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
169 					pipe_id, stages[idx]);
170 		}
171 	}
172 
173 	mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
174 }
175 
176 static void blend_setup(struct drm_crtc *crtc)
177 {
178 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
179 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
180 	struct drm_plane *plane;
181 	int i, ovlp = mdp4_crtc->ovlp;
182 	bool alpha[4]= { false, false, false, false };
183 
184 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
185 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
186 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
187 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
188 
189 	drm_atomic_crtc_for_each_plane(plane, crtc) {
190 		enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
191 		int idx = idxs[pipe_id];
192 		if (idx > 0) {
193 			const struct mdp_format *format =
194 					to_mdp_format(msm_framebuffer_format(plane->state->fb));
195 			alpha[idx-1] = format->alpha_enable;
196 		}
197 	}
198 
199 	for (i = 0; i < 4; i++) {
200 		uint32_t op;
201 
202 		if (alpha[i]) {
203 			op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
204 					MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
205 					MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
206 		} else {
207 			op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
208 					MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
209 		}
210 
211 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
212 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
213 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
214 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
215 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
216 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
217 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
218 		mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
219 	}
220 
221 	setup_mixer(mdp4_kms);
222 }
223 
224 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc)
225 {
226 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
227 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
228 	enum mdp4_dma dma = mdp4_crtc->dma;
229 	int ovlp = mdp4_crtc->ovlp;
230 	struct drm_display_mode *mode;
231 
232 	if (WARN_ON(!crtc->state))
233 		return;
234 
235 	mode = &crtc->state->adjusted_mode;
236 
237 	DBG("%s: set mode: " DRM_MODE_FMT,
238 			mdp4_crtc->name, DRM_MODE_ARG(mode));
239 
240 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
241 			MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
242 			MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
243 
244 	/* take data from pipe: */
245 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
246 	mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0);
247 	mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
248 			MDP4_DMA_DST_SIZE_WIDTH(0) |
249 			MDP4_DMA_DST_SIZE_HEIGHT(0));
250 
251 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
252 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
253 			MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
254 			MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
255 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0);
256 
257 	mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
258 
259 	if (dma == DMA_E) {
260 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
261 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
262 		mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
263 	}
264 }
265 
266 static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,
267 				     struct drm_crtc_state *old_state)
268 {
269 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
270 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
271 
272 	DBG("%s", mdp4_crtc->name);
273 
274 	if (WARN_ON(!mdp4_crtc->enabled))
275 		return;
276 
277 	/* Disable/save vblank irq handling before power is disabled */
278 	drm_crtc_vblank_off(crtc);
279 
280 	mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
281 	mdp4_disable(mdp4_kms);
282 
283 	mdp4_crtc->enabled = false;
284 }
285 
286 static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc,
287 				    struct drm_crtc_state *old_state)
288 {
289 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
290 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
291 
292 	DBG("%s", mdp4_crtc->name);
293 
294 	if (WARN_ON(mdp4_crtc->enabled))
295 		return;
296 
297 	mdp4_enable(mdp4_kms);
298 
299 	/* Restore vblank irq handling after power is enabled */
300 	drm_crtc_vblank_on(crtc);
301 
302 	mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
303 
304 	crtc_flush(crtc);
305 
306 	mdp4_crtc->enabled = true;
307 }
308 
309 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,
310 		struct drm_crtc_state *state)
311 {
312 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
313 	DBG("%s: check", mdp4_crtc->name);
314 	// TODO anything else to check?
315 	return 0;
316 }
317 
318 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,
319 				   struct drm_crtc_state *old_crtc_state)
320 {
321 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
322 	DBG("%s: begin", mdp4_crtc->name);
323 }
324 
325 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
326 				   struct drm_crtc_state *old_crtc_state)
327 {
328 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
329 	struct drm_device *dev = crtc->dev;
330 	unsigned long flags;
331 
332 	DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event);
333 
334 	WARN_ON(mdp4_crtc->event);
335 
336 	spin_lock_irqsave(&dev->event_lock, flags);
337 	mdp4_crtc->event = crtc->state->event;
338 	crtc->state->event = NULL;
339 	spin_unlock_irqrestore(&dev->event_lock, flags);
340 
341 	blend_setup(crtc);
342 	crtc_flush(crtc);
343 	request_pending(crtc, PENDING_FLIP);
344 }
345 
346 #define CURSOR_WIDTH 64
347 #define CURSOR_HEIGHT 64
348 
349 /* called from IRQ to update cursor related registers (if needed).  The
350  * cursor registers, other than x/y position, appear not to be double
351  * buffered, and changing them other than from vblank seems to trigger
352  * underflow.
353  */
354 static void update_cursor(struct drm_crtc *crtc)
355 {
356 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
357 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
358 	struct msm_kms *kms = &mdp4_kms->base.base;
359 	enum mdp4_dma dma = mdp4_crtc->dma;
360 	unsigned long flags;
361 
362 	spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
363 	if (mdp4_crtc->cursor.stale) {
364 		struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
365 		struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
366 		uint64_t iova = mdp4_crtc->cursor.next_iova;
367 
368 		if (next_bo) {
369 			/* take a obj ref + iova ref when we start scanning out: */
370 			drm_gem_object_get(next_bo);
371 			msm_gem_get_and_pin_iova(next_bo, kms->aspace, &iova);
372 
373 			/* enable cursor: */
374 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
375 					MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
376 					MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
377 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
378 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
379 					MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
380 					MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
381 		} else {
382 			/* disable cursor: */
383 			mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
384 					mdp4_kms->blank_cursor_iova);
385 		}
386 
387 		/* and drop the iova ref + obj rev when done scanning out: */
388 		if (prev_bo)
389 			drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
390 
391 		mdp4_crtc->cursor.scanout_bo = next_bo;
392 		mdp4_crtc->cursor.stale = false;
393 	}
394 
395 	mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
396 			MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
397 			MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
398 
399 	spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
400 }
401 
402 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
403 		struct drm_file *file_priv, uint32_t handle,
404 		uint32_t width, uint32_t height)
405 {
406 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
407 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
408 	struct msm_kms *kms = &mdp4_kms->base.base;
409 	struct drm_device *dev = crtc->dev;
410 	struct drm_gem_object *cursor_bo, *old_bo;
411 	unsigned long flags;
412 	uint64_t iova;
413 	int ret;
414 
415 	if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
416 		DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height);
417 		return -EINVAL;
418 	}
419 
420 	if (handle) {
421 		cursor_bo = drm_gem_object_lookup(file_priv, handle);
422 		if (!cursor_bo)
423 			return -ENOENT;
424 	} else {
425 		cursor_bo = NULL;
426 	}
427 
428 	if (cursor_bo) {
429 		ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, &iova);
430 		if (ret)
431 			goto fail;
432 	} else {
433 		iova = 0;
434 	}
435 
436 	spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
437 	old_bo = mdp4_crtc->cursor.next_bo;
438 	mdp4_crtc->cursor.next_bo   = cursor_bo;
439 	mdp4_crtc->cursor.next_iova = iova;
440 	mdp4_crtc->cursor.width     = width;
441 	mdp4_crtc->cursor.height    = height;
442 	mdp4_crtc->cursor.stale     = true;
443 	spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
444 
445 	if (old_bo) {
446 		/* drop our previous reference: */
447 		drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
448 	}
449 
450 	request_pending(crtc, PENDING_CURSOR);
451 
452 	return 0;
453 
454 fail:
455 	drm_gem_object_put_unlocked(cursor_bo);
456 	return ret;
457 }
458 
459 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
460 {
461 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
462 	unsigned long flags;
463 
464 	spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
465 	mdp4_crtc->cursor.x = x;
466 	mdp4_crtc->cursor.y = y;
467 	spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
468 
469 	crtc_flush(crtc);
470 	request_pending(crtc, PENDING_CURSOR);
471 
472 	return 0;
473 }
474 
475 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
476 	.set_config = drm_atomic_helper_set_config,
477 	.destroy = mdp4_crtc_destroy,
478 	.page_flip = drm_atomic_helper_page_flip,
479 	.cursor_set = mdp4_crtc_cursor_set,
480 	.cursor_move = mdp4_crtc_cursor_move,
481 	.reset = drm_atomic_helper_crtc_reset,
482 	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
483 	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
484 	.enable_vblank  = msm_crtc_enable_vblank,
485 	.disable_vblank = msm_crtc_disable_vblank,
486 };
487 
488 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
489 	.mode_set_nofb = mdp4_crtc_mode_set_nofb,
490 	.atomic_check = mdp4_crtc_atomic_check,
491 	.atomic_begin = mdp4_crtc_atomic_begin,
492 	.atomic_flush = mdp4_crtc_atomic_flush,
493 	.atomic_enable = mdp4_crtc_atomic_enable,
494 	.atomic_disable = mdp4_crtc_atomic_disable,
495 };
496 
497 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
498 {
499 	struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
500 	struct drm_crtc *crtc = &mdp4_crtc->base;
501 	struct msm_drm_private *priv = crtc->dev->dev_private;
502 	unsigned pending;
503 
504 	mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
505 
506 	pending = atomic_xchg(&mdp4_crtc->pending, 0);
507 
508 	if (pending & PENDING_FLIP) {
509 		complete_flip(crtc, NULL);
510 	}
511 
512 	if (pending & PENDING_CURSOR) {
513 		update_cursor(crtc);
514 		drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
515 	}
516 }
517 
518 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
519 {
520 	struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
521 	struct drm_crtc *crtc = &mdp4_crtc->base;
522 	DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
523 	crtc_flush(crtc);
524 }
525 
526 static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc)
527 {
528 	struct drm_device *dev = crtc->dev;
529 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
530 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
531 	int ret;
532 
533 	ret = drm_crtc_vblank_get(crtc);
534 	if (ret)
535 		return;
536 
537 	ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
538 		!(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) &
539 			mdp4_crtc->flushed_mask),
540 		msecs_to_jiffies(50));
541 	if (ret <= 0)
542 		dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id);
543 
544 	mdp4_crtc->flushed_mask = 0;
545 
546 	drm_crtc_vblank_put(crtc);
547 }
548 
549 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
550 {
551 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
552 	return mdp4_crtc->vblank.irqmask;
553 }
554 
555 /* set dma config, ie. the format the encoder wants. */
556 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
557 {
558 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
559 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
560 
561 	mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
562 }
563 
564 /* set interface for routing crtc->encoder: */
565 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
566 {
567 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
568 	struct mdp4_kms *mdp4_kms = get_kms(crtc);
569 	uint32_t intf_sel;
570 
571 	intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
572 
573 	switch (mdp4_crtc->dma) {
574 	case DMA_P:
575 		intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
576 		intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
577 		break;
578 	case DMA_S:
579 		intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
580 		intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
581 		break;
582 	case DMA_E:
583 		intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
584 		intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
585 		break;
586 	}
587 
588 	if (intf == INTF_DSI_VIDEO) {
589 		intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
590 		intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
591 	} else if (intf == INTF_DSI_CMD) {
592 		intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
593 		intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
594 	}
595 
596 	mdp4_crtc->mixer = mixer;
597 
598 	blend_setup(crtc);
599 
600 	DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
601 
602 	mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
603 }
604 
605 void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc)
606 {
607 	/* wait_for_flush_done is the only case for now.
608 	 * Later we will have command mode CRTC to wait for
609 	 * other event.
610 	 */
611 	mdp4_crtc_wait_for_flush_done(crtc);
612 }
613 
614 static const char *dma_names[] = {
615 		"DMA_P", "DMA_S", "DMA_E",
616 };
617 
618 /* initialize crtc */
619 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
620 		struct drm_plane *plane, int id, int ovlp_id,
621 		enum mdp4_dma dma_id)
622 {
623 	struct drm_crtc *crtc = NULL;
624 	struct mdp4_crtc *mdp4_crtc;
625 
626 	mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
627 	if (!mdp4_crtc)
628 		return ERR_PTR(-ENOMEM);
629 
630 	crtc = &mdp4_crtc->base;
631 
632 	mdp4_crtc->id = id;
633 
634 	mdp4_crtc->ovlp = ovlp_id;
635 	mdp4_crtc->dma = dma_id;
636 
637 	mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
638 	mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
639 
640 	mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
641 	mdp4_crtc->err.irq = mdp4_crtc_err_irq;
642 
643 	snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
644 			dma_names[dma_id], ovlp_id);
645 
646 	spin_lock_init(&mdp4_crtc->cursor.lock);
647 
648 	drm_flip_work_init(&mdp4_crtc->unref_cursor_work,
649 			"unref cursor", unref_cursor_worker);
650 
651 	drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs,
652 				  NULL);
653 	drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
654 
655 	return crtc;
656 }
657