1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <drm/drm_crtc.h> 8 #include <drm/drm_flip_work.h> 9 #include <drm/drm_mode.h> 10 #include <drm/drm_probe_helper.h> 11 #include <drm/drm_vblank.h> 12 13 #include "mdp4_kms.h" 14 #include "msm_gem.h" 15 16 struct mdp4_crtc { 17 struct drm_crtc base; 18 char name[8]; 19 int id; 20 int ovlp; 21 enum mdp4_dma dma; 22 bool enabled; 23 24 /* which mixer/encoder we route output to: */ 25 int mixer; 26 27 struct { 28 spinlock_t lock; 29 bool stale; 30 uint32_t width, height; 31 uint32_t x, y; 32 33 /* next cursor to scan-out: */ 34 uint32_t next_iova; 35 struct drm_gem_object *next_bo; 36 37 /* current cursor being scanned out: */ 38 struct drm_gem_object *scanout_bo; 39 } cursor; 40 41 42 /* if there is a pending flip, these will be non-null: */ 43 struct drm_pending_vblank_event *event; 44 45 /* Bits have been flushed at the last commit, 46 * used to decide if a vsync has happened since last commit. 47 */ 48 u32 flushed_mask; 49 50 #define PENDING_CURSOR 0x1 51 #define PENDING_FLIP 0x2 52 atomic_t pending; 53 54 /* for unref'ing cursor bo's after scanout completes: */ 55 struct drm_flip_work unref_cursor_work; 56 57 struct mdp_irq vblank; 58 struct mdp_irq err; 59 }; 60 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base) 61 62 static struct mdp4_kms *get_kms(struct drm_crtc *crtc) 63 { 64 struct msm_drm_private *priv = crtc->dev->dev_private; 65 return to_mdp4_kms(to_mdp_kms(priv->kms)); 66 } 67 68 static void request_pending(struct drm_crtc *crtc, uint32_t pending) 69 { 70 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 71 72 atomic_or(pending, &mdp4_crtc->pending); 73 mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank); 74 } 75 76 static void crtc_flush(struct drm_crtc *crtc) 77 { 78 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 79 struct mdp4_kms *mdp4_kms = get_kms(crtc); 80 struct drm_plane *plane; 81 uint32_t flush = 0; 82 83 drm_atomic_crtc_for_each_plane(plane, crtc) { 84 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane); 85 flush |= pipe2flush(pipe_id); 86 } 87 88 flush |= ovlp2flush(mdp4_crtc->ovlp); 89 90 DBG("%s: flush=%08x", mdp4_crtc->name, flush); 91 92 mdp4_crtc->flushed_mask = flush; 93 94 mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); 95 } 96 97 /* if file!=NULL, this is preclose potential cancel-flip path */ 98 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) 99 { 100 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 101 struct drm_device *dev = crtc->dev; 102 struct drm_pending_vblank_event *event; 103 unsigned long flags; 104 105 spin_lock_irqsave(&dev->event_lock, flags); 106 event = mdp4_crtc->event; 107 if (event) { 108 mdp4_crtc->event = NULL; 109 DBG("%s: send event: %p", mdp4_crtc->name, event); 110 drm_crtc_send_vblank_event(crtc, event); 111 } 112 spin_unlock_irqrestore(&dev->event_lock, flags); 113 } 114 115 static void unref_cursor_worker(struct drm_flip_work *work, void *val) 116 { 117 struct mdp4_crtc *mdp4_crtc = 118 container_of(work, struct mdp4_crtc, unref_cursor_work); 119 struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); 120 struct msm_kms *kms = &mdp4_kms->base.base; 121 122 msm_gem_unpin_iova(val, kms->aspace); 123 drm_gem_object_put(val); 124 } 125 126 static void mdp4_crtc_destroy(struct drm_crtc *crtc) 127 { 128 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 129 130 drm_crtc_cleanup(crtc); 131 drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work); 132 133 kfree(mdp4_crtc); 134 } 135 136 /* statically (for now) map planes to mixer stage (z-order): */ 137 static const int idxs[] = { 138 [VG1] = 1, 139 [VG2] = 2, 140 [RGB1] = 0, 141 [RGB2] = 0, 142 [RGB3] = 0, 143 [VG3] = 3, 144 [VG4] = 4, 145 146 }; 147 148 /* setup mixer config, for which we need to consider all crtc's and 149 * the planes attached to them 150 * 151 * TODO may possibly need some extra locking here 152 */ 153 static void setup_mixer(struct mdp4_kms *mdp4_kms) 154 { 155 struct drm_mode_config *config = &mdp4_kms->dev->mode_config; 156 struct drm_crtc *crtc; 157 uint32_t mixer_cfg = 0; 158 static const enum mdp_mixer_stage_id stages[] = { 159 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3, 160 }; 161 162 list_for_each_entry(crtc, &config->crtc_list, head) { 163 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 164 struct drm_plane *plane; 165 166 drm_atomic_crtc_for_each_plane(plane, crtc) { 167 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane); 168 int idx = idxs[pipe_id]; 169 mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer, 170 pipe_id, stages[idx]); 171 } 172 } 173 174 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); 175 } 176 177 static void blend_setup(struct drm_crtc *crtc) 178 { 179 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 180 struct mdp4_kms *mdp4_kms = get_kms(crtc); 181 struct drm_plane *plane; 182 int i, ovlp = mdp4_crtc->ovlp; 183 bool alpha[4]= { false, false, false, false }; 184 185 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); 186 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0); 187 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0); 188 mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0); 189 190 drm_atomic_crtc_for_each_plane(plane, crtc) { 191 enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane); 192 int idx = idxs[pipe_id]; 193 if (idx > 0) { 194 const struct mdp_format *format = 195 to_mdp_format(msm_framebuffer_format(plane->state->fb)); 196 alpha[idx-1] = format->alpha_enable; 197 } 198 } 199 200 for (i = 0; i < 4; i++) { 201 uint32_t op; 202 203 if (alpha[i]) { 204 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) | 205 MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) | 206 MDP4_OVLP_STAGE_OP_BG_INV_ALPHA; 207 } else { 208 op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) | 209 MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST); 210 } 211 212 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff); 213 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00); 214 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op); 215 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1); 216 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0); 217 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0); 218 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0); 219 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0); 220 } 221 222 setup_mixer(mdp4_kms); 223 } 224 225 static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc) 226 { 227 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 228 struct mdp4_kms *mdp4_kms = get_kms(crtc); 229 enum mdp4_dma dma = mdp4_crtc->dma; 230 int ovlp = mdp4_crtc->ovlp; 231 struct drm_display_mode *mode; 232 233 if (WARN_ON(!crtc->state)) 234 return; 235 236 mode = &crtc->state->adjusted_mode; 237 238 DBG("%s: set mode: " DRM_MODE_FMT, 239 mdp4_crtc->name, DRM_MODE_ARG(mode)); 240 241 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma), 242 MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) | 243 MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay)); 244 245 /* take data from pipe: */ 246 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0); 247 mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), 0); 248 mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma), 249 MDP4_DMA_DST_SIZE_WIDTH(0) | 250 MDP4_DMA_DST_SIZE_HEIGHT(0)); 251 252 mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0); 253 mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp), 254 MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) | 255 MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay)); 256 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), 0); 257 258 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1); 259 260 if (dma == DMA_E) { 261 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000); 262 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000); 263 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000); 264 } 265 } 266 267 static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, 268 struct drm_atomic_state *state) 269 { 270 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 271 struct mdp4_kms *mdp4_kms = get_kms(crtc); 272 unsigned long flags; 273 274 DBG("%s", mdp4_crtc->name); 275 276 if (WARN_ON(!mdp4_crtc->enabled)) 277 return; 278 279 /* Disable/save vblank irq handling before power is disabled */ 280 drm_crtc_vblank_off(crtc); 281 282 mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err); 283 mdp4_disable(mdp4_kms); 284 285 if (crtc->state->event && !crtc->state->active) { 286 WARN_ON(mdp4_crtc->event); 287 spin_lock_irqsave(&mdp4_kms->dev->event_lock, flags); 288 drm_crtc_send_vblank_event(crtc, crtc->state->event); 289 crtc->state->event = NULL; 290 spin_unlock_irqrestore(&mdp4_kms->dev->event_lock, flags); 291 } 292 293 mdp4_crtc->enabled = false; 294 } 295 296 static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc, 297 struct drm_atomic_state *state) 298 { 299 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 300 struct mdp4_kms *mdp4_kms = get_kms(crtc); 301 302 DBG("%s", mdp4_crtc->name); 303 304 if (WARN_ON(mdp4_crtc->enabled)) 305 return; 306 307 mdp4_enable(mdp4_kms); 308 309 /* Restore vblank irq handling after power is enabled */ 310 drm_crtc_vblank_on(crtc); 311 312 mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err); 313 314 crtc_flush(crtc); 315 316 mdp4_crtc->enabled = true; 317 } 318 319 static int mdp4_crtc_atomic_check(struct drm_crtc *crtc, 320 struct drm_atomic_state *state) 321 { 322 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 323 DBG("%s: check", mdp4_crtc->name); 324 // TODO anything else to check? 325 return 0; 326 } 327 328 static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc, 329 struct drm_atomic_state *state) 330 { 331 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 332 DBG("%s: begin", mdp4_crtc->name); 333 } 334 335 static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc, 336 struct drm_atomic_state *state) 337 { 338 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 339 struct drm_device *dev = crtc->dev; 340 unsigned long flags; 341 342 DBG("%s: event: %p", mdp4_crtc->name, crtc->state->event); 343 344 WARN_ON(mdp4_crtc->event); 345 346 spin_lock_irqsave(&dev->event_lock, flags); 347 mdp4_crtc->event = crtc->state->event; 348 crtc->state->event = NULL; 349 spin_unlock_irqrestore(&dev->event_lock, flags); 350 351 blend_setup(crtc); 352 crtc_flush(crtc); 353 request_pending(crtc, PENDING_FLIP); 354 } 355 356 #define CURSOR_WIDTH 64 357 #define CURSOR_HEIGHT 64 358 359 /* called from IRQ to update cursor related registers (if needed). The 360 * cursor registers, other than x/y position, appear not to be double 361 * buffered, and changing them other than from vblank seems to trigger 362 * underflow. 363 */ 364 static void update_cursor(struct drm_crtc *crtc) 365 { 366 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 367 struct mdp4_kms *mdp4_kms = get_kms(crtc); 368 struct msm_kms *kms = &mdp4_kms->base.base; 369 enum mdp4_dma dma = mdp4_crtc->dma; 370 unsigned long flags; 371 372 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); 373 if (mdp4_crtc->cursor.stale) { 374 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo; 375 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo; 376 uint64_t iova = mdp4_crtc->cursor.next_iova; 377 378 if (next_bo) { 379 /* take a obj ref + iova ref when we start scanning out: */ 380 drm_gem_object_get(next_bo); 381 msm_gem_get_and_pin_iova(next_bo, kms->aspace, &iova); 382 383 /* enable cursor: */ 384 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma), 385 MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) | 386 MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height)); 387 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova); 388 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma), 389 MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) | 390 MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN); 391 } else { 392 /* disable cursor: */ 393 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), 394 mdp4_kms->blank_cursor_iova); 395 } 396 397 /* and drop the iova ref + obj rev when done scanning out: */ 398 if (prev_bo) 399 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo); 400 401 mdp4_crtc->cursor.scanout_bo = next_bo; 402 mdp4_crtc->cursor.stale = false; 403 } 404 405 mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma), 406 MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) | 407 MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y)); 408 409 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); 410 } 411 412 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc, 413 struct drm_file *file_priv, uint32_t handle, 414 uint32_t width, uint32_t height) 415 { 416 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 417 struct mdp4_kms *mdp4_kms = get_kms(crtc); 418 struct msm_kms *kms = &mdp4_kms->base.base; 419 struct drm_device *dev = crtc->dev; 420 struct drm_gem_object *cursor_bo, *old_bo; 421 unsigned long flags; 422 uint64_t iova; 423 int ret; 424 425 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { 426 DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height); 427 return -EINVAL; 428 } 429 430 if (handle) { 431 cursor_bo = drm_gem_object_lookup(file_priv, handle); 432 if (!cursor_bo) 433 return -ENOENT; 434 } else { 435 cursor_bo = NULL; 436 } 437 438 if (cursor_bo) { 439 ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, &iova); 440 if (ret) 441 goto fail; 442 } else { 443 iova = 0; 444 } 445 446 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); 447 old_bo = mdp4_crtc->cursor.next_bo; 448 mdp4_crtc->cursor.next_bo = cursor_bo; 449 mdp4_crtc->cursor.next_iova = iova; 450 mdp4_crtc->cursor.width = width; 451 mdp4_crtc->cursor.height = height; 452 mdp4_crtc->cursor.stale = true; 453 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); 454 455 if (old_bo) { 456 /* drop our previous reference: */ 457 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo); 458 } 459 460 request_pending(crtc, PENDING_CURSOR); 461 462 return 0; 463 464 fail: 465 drm_gem_object_put(cursor_bo); 466 return ret; 467 } 468 469 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 470 { 471 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 472 unsigned long flags; 473 474 spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); 475 mdp4_crtc->cursor.x = x; 476 mdp4_crtc->cursor.y = y; 477 spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); 478 479 crtc_flush(crtc); 480 request_pending(crtc, PENDING_CURSOR); 481 482 return 0; 483 } 484 485 static const struct drm_crtc_funcs mdp4_crtc_funcs = { 486 .set_config = drm_atomic_helper_set_config, 487 .destroy = mdp4_crtc_destroy, 488 .page_flip = drm_atomic_helper_page_flip, 489 .cursor_set = mdp4_crtc_cursor_set, 490 .cursor_move = mdp4_crtc_cursor_move, 491 .reset = drm_atomic_helper_crtc_reset, 492 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 493 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 494 .enable_vblank = msm_crtc_enable_vblank, 495 .disable_vblank = msm_crtc_disable_vblank, 496 }; 497 498 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = { 499 .mode_set_nofb = mdp4_crtc_mode_set_nofb, 500 .atomic_check = mdp4_crtc_atomic_check, 501 .atomic_begin = mdp4_crtc_atomic_begin, 502 .atomic_flush = mdp4_crtc_atomic_flush, 503 .atomic_enable = mdp4_crtc_atomic_enable, 504 .atomic_disable = mdp4_crtc_atomic_disable, 505 }; 506 507 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) 508 { 509 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank); 510 struct drm_crtc *crtc = &mdp4_crtc->base; 511 struct msm_drm_private *priv = crtc->dev->dev_private; 512 unsigned pending; 513 514 mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank); 515 516 pending = atomic_xchg(&mdp4_crtc->pending, 0); 517 518 if (pending & PENDING_FLIP) { 519 complete_flip(crtc, NULL); 520 } 521 522 if (pending & PENDING_CURSOR) { 523 update_cursor(crtc); 524 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq); 525 } 526 } 527 528 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) 529 { 530 struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err); 531 struct drm_crtc *crtc = &mdp4_crtc->base; 532 DBG("%s: error: %08x", mdp4_crtc->name, irqstatus); 533 crtc_flush(crtc); 534 } 535 536 static void mdp4_crtc_wait_for_flush_done(struct drm_crtc *crtc) 537 { 538 struct drm_device *dev = crtc->dev; 539 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 540 struct mdp4_kms *mdp4_kms = get_kms(crtc); 541 int ret; 542 543 ret = drm_crtc_vblank_get(crtc); 544 if (ret) 545 return; 546 547 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue, 548 !(mdp4_read(mdp4_kms, REG_MDP4_OVERLAY_FLUSH) & 549 mdp4_crtc->flushed_mask), 550 msecs_to_jiffies(50)); 551 if (ret <= 0) 552 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp4_crtc->id); 553 554 mdp4_crtc->flushed_mask = 0; 555 556 drm_crtc_vblank_put(crtc); 557 } 558 559 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc) 560 { 561 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 562 return mdp4_crtc->vblank.irqmask; 563 } 564 565 /* set dma config, ie. the format the encoder wants. */ 566 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config) 567 { 568 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 569 struct mdp4_kms *mdp4_kms = get_kms(crtc); 570 571 mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config); 572 } 573 574 /* set interface for routing crtc->encoder: */ 575 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer) 576 { 577 struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); 578 struct mdp4_kms *mdp4_kms = get_kms(crtc); 579 uint32_t intf_sel; 580 581 intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL); 582 583 switch (mdp4_crtc->dma) { 584 case DMA_P: 585 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK; 586 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf); 587 break; 588 case DMA_S: 589 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK; 590 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf); 591 break; 592 case DMA_E: 593 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK; 594 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf); 595 break; 596 } 597 598 if (intf == INTF_DSI_VIDEO) { 599 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD; 600 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO; 601 } else if (intf == INTF_DSI_CMD) { 602 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO; 603 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD; 604 } 605 606 mdp4_crtc->mixer = mixer; 607 608 blend_setup(crtc); 609 610 DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel); 611 612 mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel); 613 } 614 615 void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc) 616 { 617 /* wait_for_flush_done is the only case for now. 618 * Later we will have command mode CRTC to wait for 619 * other event. 620 */ 621 mdp4_crtc_wait_for_flush_done(crtc); 622 } 623 624 static const char *dma_names[] = { 625 "DMA_P", "DMA_S", "DMA_E", 626 }; 627 628 /* initialize crtc */ 629 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, 630 struct drm_plane *plane, int id, int ovlp_id, 631 enum mdp4_dma dma_id) 632 { 633 struct drm_crtc *crtc = NULL; 634 struct mdp4_crtc *mdp4_crtc; 635 636 mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL); 637 if (!mdp4_crtc) 638 return ERR_PTR(-ENOMEM); 639 640 crtc = &mdp4_crtc->base; 641 642 mdp4_crtc->id = id; 643 644 mdp4_crtc->ovlp = ovlp_id; 645 mdp4_crtc->dma = dma_id; 646 647 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma); 648 mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq; 649 650 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma); 651 mdp4_crtc->err.irq = mdp4_crtc_err_irq; 652 653 snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d", 654 dma_names[dma_id], ovlp_id); 655 656 spin_lock_init(&mdp4_crtc->cursor.lock); 657 658 drm_flip_work_init(&mdp4_crtc->unref_cursor_work, 659 "unref cursor", unref_cursor_worker); 660 661 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs, 662 NULL); 663 drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs); 664 665 return crtc; 666 } 667