1 #ifndef MDP4_XML 2 #define MDP4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) 24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) 25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) 26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) 27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) 28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) 29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) 30 31 Copyright (C) 2013-2021 by the following authors: 32 - Rob Clark <robdclark@gmail.com> (robclark) 33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 34 35 Permission is hereby granted, free of charge, to any person obtaining 36 a copy of this software and associated documentation files (the 37 "Software"), to deal in the Software without restriction, including 38 without limitation the rights to use, copy, modify, merge, publish, 39 distribute, sublicense, and/or sell copies of the Software, and to 40 permit persons to whom the Software is furnished to do so, subject to 41 the following conditions: 42 43 The above copyright notice and this permission notice (including the 44 next paragraph) shall be included in all copies or substantial 45 portions of the Software. 46 47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 54 */ 55 56 57 enum mdp4_pipe { 58 VG1 = 0, 59 VG2 = 1, 60 RGB1 = 2, 61 RGB2 = 3, 62 RGB3 = 4, 63 VG3 = 5, 64 VG4 = 6, 65 }; 66 67 enum mdp4_mixer { 68 MIXER0 = 0, 69 MIXER1 = 1, 70 MIXER2 = 2, 71 }; 72 73 enum mdp4_intf { 74 INTF_LCDC_DTV = 0, 75 INTF_DSI_VIDEO = 1, 76 INTF_DSI_CMD = 2, 77 INTF_EBI2_TV = 3, 78 }; 79 80 enum mdp4_cursor_format { 81 CURSOR_ARGB = 1, 82 CURSOR_XRGB = 2, 83 }; 84 85 enum mdp4_frame_format { 86 FRAME_LINEAR = 0, 87 FRAME_TILE_ARGB_4X4 = 1, 88 FRAME_TILE_YCBCR_420 = 2, 89 }; 90 91 enum mdp4_scale_unit { 92 SCALE_FIR = 0, 93 SCALE_MN_PHASE = 1, 94 SCALE_PIXEL_RPT = 2, 95 }; 96 97 enum mdp4_dma { 98 DMA_P = 0, 99 DMA_S = 1, 100 DMA_E = 2, 101 }; 102 103 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001 104 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002 105 #define MDP4_IRQ_DMA_S_DONE 0x00000004 106 #define MDP4_IRQ_DMA_E_DONE 0x00000008 107 #define MDP4_IRQ_DMA_P_DONE 0x00000010 108 #define MDP4_IRQ_VG1_HISTOGRAM 0x00000020 109 #define MDP4_IRQ_VG2_HISTOGRAM 0x00000040 110 #define MDP4_IRQ_PRIMARY_VSYNC 0x00000080 111 #define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100 112 #define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200 113 #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400 114 #define MDP4_IRQ_PRIMARY_RDPTR 0x00000800 115 #define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000 116 #define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000 117 #define MDP4_IRQ_OVERLAY2_DONE 0x40000000 118 #define REG_MDP4_VERSION 0x00000000 119 #define MDP4_VERSION_MINOR__MASK 0x00ff0000 120 #define MDP4_VERSION_MINOR__SHIFT 16 121 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) 122 { 123 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; 124 } 125 #define MDP4_VERSION_MAJOR__MASK 0xff000000 126 #define MDP4_VERSION_MAJOR__SHIFT 24 127 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) 128 { 129 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; 130 } 131 132 #define REG_MDP4_OVLP0_KICK 0x00000004 133 134 #define REG_MDP4_OVLP1_KICK 0x00000008 135 136 #define REG_MDP4_OVLP2_KICK 0x000000d0 137 138 #define REG_MDP4_DMA_P_KICK 0x0000000c 139 140 #define REG_MDP4_DMA_S_KICK 0x00000010 141 142 #define REG_MDP4_DMA_E_KICK 0x00000014 143 144 #define REG_MDP4_DISP_STATUS 0x00000018 145 146 #define REG_MDP4_DISP_INTF_SEL 0x00000038 147 #define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003 148 #define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0 149 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) 150 { 151 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; 152 } 153 #define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c 154 #define MDP4_DISP_INTF_SEL_SEC__SHIFT 2 155 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) 156 { 157 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; 158 } 159 #define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030 160 #define MDP4_DISP_INTF_SEL_EXT__SHIFT 4 161 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) 162 { 163 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; 164 } 165 #define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040 166 #define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080 167 168 #define REG_MDP4_RESET_STATUS 0x0000003c 169 170 #define REG_MDP4_READ_CNFG 0x0000004c 171 172 #define REG_MDP4_INTR_ENABLE 0x00000050 173 174 #define REG_MDP4_INTR_STATUS 0x00000054 175 176 #define REG_MDP4_INTR_CLEAR 0x00000058 177 178 #define REG_MDP4_EBI2_LCD0 0x00000060 179 180 #define REG_MDP4_EBI2_LCD1 0x00000064 181 182 #define REG_MDP4_PORTMAP_MODE 0x00000070 183 184 #define REG_MDP4_CS_CONTROLLER0 0x000000c0 185 186 #define REG_MDP4_CS_CONTROLLER1 0x000000c4 187 188 #define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0 189 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007 190 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0 191 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) 192 { 193 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; 194 } 195 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008 196 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070 197 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4 198 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) 199 { 200 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; 201 } 202 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080 203 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700 204 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8 205 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) 206 { 207 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; 208 } 209 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800 210 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000 211 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12 212 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) 213 { 214 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; 215 } 216 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000 217 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000 218 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16 219 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) 220 { 221 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; 222 } 223 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000 224 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000 225 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20 226 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) 227 { 228 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; 229 } 230 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000 231 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000 232 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24 233 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) 234 { 235 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; 236 } 237 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000 238 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000 239 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28 240 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) 241 { 242 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; 243 } 244 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000 245 246 #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc 247 248 #define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100 249 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007 250 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0 251 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) 252 { 253 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; 254 } 255 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008 256 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070 257 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4 258 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) 259 { 260 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; 261 } 262 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080 263 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700 264 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8 265 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) 266 { 267 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; 268 } 269 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800 270 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000 271 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12 272 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) 273 { 274 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; 275 } 276 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000 277 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000 278 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16 279 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) 280 { 281 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; 282 } 283 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000 284 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000 285 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20 286 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) 287 { 288 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; 289 } 290 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000 291 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000 292 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24 293 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) 294 { 295 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; 296 } 297 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000 298 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000 299 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28 300 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) 301 { 302 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; 303 } 304 #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000 305 306 #define REG_MDP4_VG2_SRC_FORMAT 0x00030050 307 308 #define REG_MDP4_VG2_CONST_COLOR 0x00031008 309 310 #define REG_MDP4_OVERLAY_FLUSH 0x00018000 311 #define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001 312 #define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002 313 #define MDP4_OVERLAY_FLUSH_VG1 0x00000004 314 #define MDP4_OVERLAY_FLUSH_VG2 0x00000008 315 #define MDP4_OVERLAY_FLUSH_RGB1 0x00000010 316 #define MDP4_OVERLAY_FLUSH_RGB2 0x00000020 317 318 static inline uint32_t __offset_OVLP(uint32_t idx) 319 { 320 switch (idx) { 321 case 0: return 0x00010000; 322 case 1: return 0x00018000; 323 case 2: return 0x00088000; 324 default: return INVALID_IDX(idx); 325 } 326 } 327 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } 328 329 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } 330 331 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } 332 #define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000 333 #define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16 334 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) 335 { 336 return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK; 337 } 338 #define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff 339 #define MDP4_OVLP_SIZE_WIDTH__SHIFT 0 340 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) 341 { 342 return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK; 343 } 344 345 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } 346 347 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } 348 349 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } 350 351 static inline uint32_t __offset_STAGE(uint32_t idx) 352 { 353 switch (idx) { 354 case 0: return 0x00000104; 355 case 1: return 0x00000124; 356 case 2: return 0x00000144; 357 case 3: return 0x00000160; 358 default: return INVALID_IDX(idx); 359 } 360 } 361 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } 362 363 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } 364 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003 365 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0 366 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) 367 { 368 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; 369 } 370 #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004 371 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008 372 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030 373 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4 374 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) 375 { 376 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; 377 } 378 #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040 379 #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080 380 #define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100 381 #define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200 382 383 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } 384 385 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } 386 387 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } 388 389 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } 390 391 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } 392 393 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } 394 395 static inline uint32_t __offset_STAGE_CO3(uint32_t idx) 396 { 397 switch (idx) { 398 case 0: return 0x00001004; 399 case 1: return 0x00001404; 400 case 2: return 0x00001804; 401 case 3: return 0x00001b84; 402 default: return INVALID_IDX(idx); 403 } 404 } 405 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } 406 407 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } 408 #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001 409 410 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); } 411 412 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); } 413 414 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); } 415 416 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); } 417 418 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); } 419 420 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } 421 422 423 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } 424 425 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } 426 427 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } 428 429 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } 430 431 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } 432 433 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } 434 435 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } 436 437 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } 438 439 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } 440 441 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } 442 443 #define REG_MDP4_DMA_P_OP_MODE 0x00090070 444 445 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } 446 447 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } 448 449 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } 450 451 #define REG_MDP4_DMA_S_OP_MODE 0x000a0028 452 453 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } 454 455 static inline uint32_t __offset_DMA(enum mdp4_dma idx) 456 { 457 switch (idx) { 458 case DMA_P: return 0x00090000; 459 case DMA_S: return 0x000a0000; 460 case DMA_E: return 0x000b0000; 461 default: return INVALID_IDX(idx); 462 } 463 } 464 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } 465 466 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } 467 #define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003 468 #define MDP4_DMA_CONFIG_G_BPC__SHIFT 0 469 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) 470 { 471 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; 472 } 473 #define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c 474 #define MDP4_DMA_CONFIG_B_BPC__SHIFT 2 475 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) 476 { 477 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; 478 } 479 #define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030 480 #define MDP4_DMA_CONFIG_R_BPC__SHIFT 4 481 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) 482 { 483 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; 484 } 485 #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080 486 #define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00 487 #define MDP4_DMA_CONFIG_PACK__SHIFT 8 488 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) 489 { 490 return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK; 491 } 492 #define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000 493 #define MDP4_DMA_CONFIG_DITHER_EN 0x01000000 494 495 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } 496 #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000 497 #define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16 498 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) 499 { 500 return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK; 501 } 502 #define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff 503 #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0 504 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) 505 { 506 return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK; 507 } 508 509 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } 510 511 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } 512 513 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } 514 #define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000 515 #define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16 516 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) 517 { 518 return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK; 519 } 520 #define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff 521 #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0 522 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) 523 { 524 return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK; 525 } 526 527 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } 528 #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f 529 #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0 530 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) 531 { 532 return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK; 533 } 534 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000 535 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16 536 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) 537 { 538 return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK; 539 } 540 541 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); } 542 543 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); } 544 #define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff 545 #define MDP4_DMA_CURSOR_POS_X__SHIFT 0 546 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) 547 { 548 return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK; 549 } 550 #define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000 551 #define MDP4_DMA_CURSOR_POS_Y__SHIFT 16 552 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) 553 { 554 return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK; 555 } 556 557 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); } 558 #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001 559 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006 560 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1 561 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) 562 { 563 return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK; 564 } 565 #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008 566 567 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); } 568 569 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); } 570 571 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); } 572 573 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); } 574 575 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } 576 577 578 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } 579 580 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } 581 582 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } 583 584 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } 585 586 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } 587 588 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } 589 590 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } 591 592 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } 593 594 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } 595 596 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } 597 598 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } 599 600 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } 601 #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000 602 #define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16 603 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) 604 { 605 return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK; 606 } 607 #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff 608 #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0 609 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) 610 { 611 return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK; 612 } 613 614 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } 615 #define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000 616 #define MDP4_PIPE_SRC_XY_Y__SHIFT 16 617 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) 618 { 619 return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK; 620 } 621 #define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff 622 #define MDP4_PIPE_SRC_XY_X__SHIFT 0 623 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) 624 { 625 return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK; 626 } 627 628 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } 629 #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000 630 #define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16 631 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) 632 { 633 return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK; 634 } 635 #define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff 636 #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0 637 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) 638 { 639 return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK; 640 } 641 642 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } 643 #define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000 644 #define MDP4_PIPE_DST_XY_Y__SHIFT 16 645 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) 646 { 647 return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK; 648 } 649 #define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff 650 #define MDP4_PIPE_DST_XY_X__SHIFT 0 651 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) 652 { 653 return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK; 654 } 655 656 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; } 657 658 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; } 659 660 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; } 661 662 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; } 663 664 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } 665 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff 666 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0 667 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) 668 { 669 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK; 670 } 671 #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000 672 #define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16 673 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) 674 { 675 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK; 676 } 677 678 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } 679 #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff 680 #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0 681 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) 682 { 683 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK; 684 } 685 #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000 686 #define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16 687 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) 688 { 689 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; 690 } 691 692 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } 693 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000 694 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16 695 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) 696 { 697 return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK; 698 } 699 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff 700 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0 701 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) 702 { 703 return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK; 704 } 705 706 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } 707 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 708 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 709 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) 710 { 711 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; 712 } 713 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c 714 #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2 715 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) 716 { 717 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; 718 } 719 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030 720 #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4 721 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) 722 { 723 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; 724 } 725 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0 726 #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6 727 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) 728 { 729 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; 730 } 731 #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100 732 #define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600 733 #define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9 734 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) 735 { 736 return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK; 737 } 738 #define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000 739 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000 740 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13 741 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) 742 { 743 return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; 744 } 745 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000 746 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 747 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000 748 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19 749 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) 750 { 751 return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK; 752 } 753 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000 754 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000 755 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26 756 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) 757 { 758 return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; 759 } 760 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000 761 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29 762 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) 763 { 764 return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK; 765 } 766 767 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; } 768 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff 769 #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0 770 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) 771 { 772 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK; 773 } 774 #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00 775 #define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8 776 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) 777 { 778 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK; 779 } 780 #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000 781 #define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16 782 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) 783 { 784 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK; 785 } 786 #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000 787 #define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24 788 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) 789 { 790 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK; 791 } 792 793 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } 794 #define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001 795 #define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002 796 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c 797 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2 798 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) 799 { 800 return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK; 801 } 802 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030 803 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4 804 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) 805 { 806 return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK; 807 } 808 #define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200 809 #define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400 810 #define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800 811 #define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000 812 #define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000 813 #define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000 814 #define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000 815 #define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000 816 #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000 817 818 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } 819 820 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } 821 822 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } 823 824 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } 825 826 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } 827 828 829 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 830 831 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 832 833 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 834 835 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 836 837 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 838 839 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 840 841 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 842 843 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 844 845 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 846 847 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 848 849 #define REG_MDP4_LCDC 0x000c0000 850 851 #define REG_MDP4_LCDC_ENABLE 0x000c0000 852 853 #define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004 854 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 855 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0 856 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) 857 { 858 return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK; 859 } 860 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000 861 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16 862 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) 863 { 864 return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK; 865 } 866 867 #define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008 868 869 #define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c 870 871 #define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010 872 #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff 873 #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0 874 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) 875 { 876 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK; 877 } 878 #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000 879 #define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16 880 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) 881 { 882 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK; 883 } 884 885 #define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014 886 887 #define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018 888 889 #define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c 890 #define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff 891 #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0 892 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) 893 { 894 return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK; 895 } 896 #define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000 897 #define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16 898 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) 899 { 900 return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK; 901 } 902 #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 903 904 #define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020 905 906 #define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024 907 908 #define REG_MDP4_LCDC_BORDER_CLR 0x000c0028 909 910 #define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c 911 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 912 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0 913 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) 914 { 915 return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK; 916 } 917 #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 918 919 #define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030 920 921 #define REG_MDP4_LCDC_TEST_CNTL 0x000c0034 922 923 #define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038 924 #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001 925 #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002 926 #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004 927 928 #define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000 929 #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004 930 #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008 931 #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010 932 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020 933 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040 934 #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080 935 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100 936 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200 937 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400 938 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800 939 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000 940 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000 941 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000 942 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000 943 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000 944 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000 945 946 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } 947 948 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; } 949 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff 950 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0 951 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) 952 { 953 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK; 954 } 955 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00 956 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8 957 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) 958 { 959 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK; 960 } 961 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000 962 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16 963 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) 964 { 965 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK; 966 } 967 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000 968 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24 969 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) 970 { 971 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK; 972 } 973 974 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; } 975 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff 976 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0 977 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) 978 { 979 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK; 980 } 981 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00 982 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8 983 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) 984 { 985 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK; 986 } 987 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000 988 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16 989 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) 990 { 991 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK; 992 } 993 994 #define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034 995 996 #define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000 997 998 #define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004 999 1000 #define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008 1001 1002 #define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c 1003 1004 #define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014 1005 1006 #define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018 1007 1008 #define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c 1009 1010 #define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020 1011 1012 #define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024 1013 1014 #define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080 1015 1016 #define REG_MDP4_LVDS_PHY_CFG2 0x000c3108 1017 1018 #define REG_MDP4_LVDS_PHY_CFG0 0x000c3100 1019 #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010 1020 #define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040 1021 #define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080 1022 1023 #define REG_MDP4_DTV 0x000d0000 1024 1025 #define REG_MDP4_DTV_ENABLE 0x000d0000 1026 1027 #define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004 1028 #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 1029 #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0 1030 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) 1031 { 1032 return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK; 1033 } 1034 #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000 1035 #define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16 1036 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) 1037 { 1038 return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK; 1039 } 1040 1041 #define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008 1042 1043 #define REG_MDP4_DTV_VSYNC_LEN 0x000d000c 1044 1045 #define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018 1046 #define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff 1047 #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0 1048 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) 1049 { 1050 return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK; 1051 } 1052 #define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000 1053 #define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16 1054 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) 1055 { 1056 return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK; 1057 } 1058 1059 #define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c 1060 1061 #define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020 1062 1063 #define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c 1064 #define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff 1065 #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0 1066 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) 1067 { 1068 return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK; 1069 } 1070 #define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000 1071 #define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16 1072 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) 1073 { 1074 return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK; 1075 } 1076 #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 1077 1078 #define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030 1079 1080 #define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038 1081 1082 #define REG_MDP4_DTV_BORDER_CLR 0x000d0040 1083 1084 #define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044 1085 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 1086 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0 1087 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) 1088 { 1089 return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK; 1090 } 1091 #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 1092 1093 #define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048 1094 1095 #define REG_MDP4_DTV_TEST_CNTL 0x000d004c 1096 1097 #define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050 1098 #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001 1099 #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002 1100 #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004 1101 1102 #define REG_MDP4_DSI 0x000e0000 1103 1104 #define REG_MDP4_DSI_ENABLE 0x000e0000 1105 1106 #define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004 1107 #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 1108 #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0 1109 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) 1110 { 1111 return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK; 1112 } 1113 #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000 1114 #define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16 1115 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) 1116 { 1117 return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK; 1118 } 1119 1120 #define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008 1121 1122 #define REG_MDP4_DSI_VSYNC_LEN 0x000e000c 1123 1124 #define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010 1125 #define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff 1126 #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0 1127 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) 1128 { 1129 return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK; 1130 } 1131 #define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000 1132 #define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16 1133 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) 1134 { 1135 return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK; 1136 } 1137 1138 #define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014 1139 1140 #define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018 1141 1142 #define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c 1143 #define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff 1144 #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0 1145 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) 1146 { 1147 return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK; 1148 } 1149 #define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000 1150 #define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16 1151 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) 1152 { 1153 return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK; 1154 } 1155 #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 1156 1157 #define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020 1158 1159 #define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024 1160 1161 #define REG_MDP4_DSI_BORDER_CLR 0x000e0028 1162 1163 #define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c 1164 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 1165 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0 1166 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) 1167 { 1168 return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK; 1169 } 1170 #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 1171 1172 #define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030 1173 1174 #define REG_MDP4_DSI_TEST_CNTL 0x000e0034 1175 1176 #define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038 1177 #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001 1178 #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002 1179 #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004 1180 1181 1182 #endif /* MDP4_XML */ 1183