1 #ifndef MDP4_XML 2 #define MDP4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-03-03 01:18:13) 12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) 13 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-01-30 18:25:22) 14 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-01-30 18:25:22) 15 - /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-01-30 18:25:22) 16 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml ( 17560 bytes, from 2021-09-16 22:37:02) 17 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-07-22 15:21:56) 18 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-07-22 15:21:56) 19 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-07-22 15:21:56) 20 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-07-22 15:21:56) 21 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-07-22 15:21:56) 22 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-07-22 15:21:56) 23 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-03 01:18:13) 24 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-01-30 18:25:22) 25 - /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-01-30 18:25:22) 26 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-01-30 18:25:22) 27 - /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-01-30 18:25:22) 28 - /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-01-30 18:25:22) 29 30 Copyright (C) 2013-2021 by the following authors: 31 - Rob Clark <robdclark@gmail.com> (robclark) 32 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 33 34 Permission is hereby granted, free of charge, to any person obtaining 35 a copy of this software and associated documentation files (the 36 "Software"), to deal in the Software without restriction, including 37 without limitation the rights to use, copy, modify, merge, publish, 38 distribute, sublicense, and/or sell copies of the Software, and to 39 permit persons to whom the Software is furnished to do so, subject to 40 the following conditions: 41 42 The above copyright notice and this permission notice (including the 43 next paragraph) shall be included in all copies or substantial 44 portions of the Software. 45 46 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 47 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 48 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 49 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 50 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 51 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 52 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 53 */ 54 55 56 enum mdp4_pipe { 57 VG1 = 0, 58 VG2 = 1, 59 RGB1 = 2, 60 RGB2 = 3, 61 RGB3 = 4, 62 VG3 = 5, 63 VG4 = 6, 64 }; 65 66 enum mdp4_mixer { 67 MIXER0 = 0, 68 MIXER1 = 1, 69 MIXER2 = 2, 70 }; 71 72 enum mdp4_intf { 73 INTF_LCDC_DTV = 0, 74 INTF_DSI_VIDEO = 1, 75 INTF_DSI_CMD = 2, 76 INTF_EBI2_TV = 3, 77 }; 78 79 enum mdp4_cursor_format { 80 CURSOR_ARGB = 1, 81 CURSOR_XRGB = 2, 82 }; 83 84 enum mdp4_frame_format { 85 FRAME_LINEAR = 0, 86 FRAME_TILE_ARGB_4X4 = 1, 87 FRAME_TILE_YCBCR_420 = 2, 88 }; 89 90 enum mdp4_scale_unit { 91 SCALE_FIR = 0, 92 SCALE_MN_PHASE = 1, 93 SCALE_PIXEL_RPT = 2, 94 }; 95 96 enum mdp4_dma { 97 DMA_P = 0, 98 DMA_S = 1, 99 DMA_E = 2, 100 }; 101 102 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001 103 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002 104 #define MDP4_IRQ_DMA_S_DONE 0x00000004 105 #define MDP4_IRQ_DMA_E_DONE 0x00000008 106 #define MDP4_IRQ_DMA_P_DONE 0x00000010 107 #define MDP4_IRQ_VG1_HISTOGRAM 0x00000020 108 #define MDP4_IRQ_VG2_HISTOGRAM 0x00000040 109 #define MDP4_IRQ_PRIMARY_VSYNC 0x00000080 110 #define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100 111 #define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200 112 #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400 113 #define MDP4_IRQ_PRIMARY_RDPTR 0x00000800 114 #define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000 115 #define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000 116 #define MDP4_IRQ_OVERLAY2_DONE 0x40000000 117 #define REG_MDP4_VERSION 0x00000000 118 #define MDP4_VERSION_MINOR__MASK 0x00ff0000 119 #define MDP4_VERSION_MINOR__SHIFT 16 120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) 121 { 122 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; 123 } 124 #define MDP4_VERSION_MAJOR__MASK 0xff000000 125 #define MDP4_VERSION_MAJOR__SHIFT 24 126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) 127 { 128 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; 129 } 130 131 #define REG_MDP4_OVLP0_KICK 0x00000004 132 133 #define REG_MDP4_OVLP1_KICK 0x00000008 134 135 #define REG_MDP4_OVLP2_KICK 0x000000d0 136 137 #define REG_MDP4_DMA_P_KICK 0x0000000c 138 139 #define REG_MDP4_DMA_S_KICK 0x00000010 140 141 #define REG_MDP4_DMA_E_KICK 0x00000014 142 143 #define REG_MDP4_DISP_STATUS 0x00000018 144 145 #define REG_MDP4_DISP_INTF_SEL 0x00000038 146 #define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003 147 #define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0 148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) 149 { 150 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; 151 } 152 #define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c 153 #define MDP4_DISP_INTF_SEL_SEC__SHIFT 2 154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) 155 { 156 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; 157 } 158 #define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030 159 #define MDP4_DISP_INTF_SEL_EXT__SHIFT 4 160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) 161 { 162 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; 163 } 164 #define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040 165 #define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080 166 167 #define REG_MDP4_RESET_STATUS 0x0000003c 168 169 #define REG_MDP4_READ_CNFG 0x0000004c 170 171 #define REG_MDP4_INTR_ENABLE 0x00000050 172 173 #define REG_MDP4_INTR_STATUS 0x00000054 174 175 #define REG_MDP4_INTR_CLEAR 0x00000058 176 177 #define REG_MDP4_EBI2_LCD0 0x00000060 178 179 #define REG_MDP4_EBI2_LCD1 0x00000064 180 181 #define REG_MDP4_PORTMAP_MODE 0x00000070 182 183 #define REG_MDP4_CS_CONTROLLER0 0x000000c0 184 185 #define REG_MDP4_CS_CONTROLLER1 0x000000c4 186 187 #define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0 188 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007 189 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0 190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) 191 { 192 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; 193 } 194 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008 195 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070 196 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4 197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) 198 { 199 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; 200 } 201 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080 202 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700 203 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8 204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) 205 { 206 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; 207 } 208 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800 209 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000 210 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12 211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) 212 { 213 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; 214 } 215 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000 216 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000 217 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16 218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) 219 { 220 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; 221 } 222 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000 223 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000 224 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20 225 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) 226 { 227 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; 228 } 229 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000 230 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000 231 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24 232 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) 233 { 234 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; 235 } 236 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000 237 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000 238 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28 239 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) 240 { 241 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; 242 } 243 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000 244 245 #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc 246 247 #define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100 248 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007 249 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0 250 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) 251 { 252 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; 253 } 254 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008 255 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070 256 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4 257 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) 258 { 259 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; 260 } 261 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080 262 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700 263 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8 264 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) 265 { 266 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; 267 } 268 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800 269 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000 270 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12 271 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) 272 { 273 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; 274 } 275 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000 276 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000 277 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16 278 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) 279 { 280 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; 281 } 282 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000 283 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000 284 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20 285 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) 286 { 287 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; 288 } 289 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000 290 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000 291 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24 292 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) 293 { 294 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; 295 } 296 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000 297 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000 298 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28 299 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) 300 { 301 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; 302 } 303 #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000 304 305 #define REG_MDP4_VG2_SRC_FORMAT 0x00030050 306 307 #define REG_MDP4_VG2_CONST_COLOR 0x00031008 308 309 #define REG_MDP4_OVERLAY_FLUSH 0x00018000 310 #define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001 311 #define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002 312 #define MDP4_OVERLAY_FLUSH_VG1 0x00000004 313 #define MDP4_OVERLAY_FLUSH_VG2 0x00000008 314 #define MDP4_OVERLAY_FLUSH_RGB1 0x00000010 315 #define MDP4_OVERLAY_FLUSH_RGB2 0x00000020 316 317 static inline uint32_t __offset_OVLP(uint32_t idx) 318 { 319 switch (idx) { 320 case 0: return 0x00010000; 321 case 1: return 0x00018000; 322 case 2: return 0x00088000; 323 default: return INVALID_IDX(idx); 324 } 325 } 326 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } 327 328 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } 329 330 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } 331 #define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000 332 #define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16 333 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) 334 { 335 return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK; 336 } 337 #define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff 338 #define MDP4_OVLP_SIZE_WIDTH__SHIFT 0 339 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) 340 { 341 return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK; 342 } 343 344 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } 345 346 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } 347 348 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } 349 350 static inline uint32_t __offset_STAGE(uint32_t idx) 351 { 352 switch (idx) { 353 case 0: return 0x00000104; 354 case 1: return 0x00000124; 355 case 2: return 0x00000144; 356 case 3: return 0x00000160; 357 default: return INVALID_IDX(idx); 358 } 359 } 360 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } 361 362 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } 363 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003 364 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0 365 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) 366 { 367 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; 368 } 369 #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004 370 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008 371 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030 372 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4 373 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) 374 { 375 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; 376 } 377 #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040 378 #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080 379 #define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100 380 #define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200 381 382 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } 383 384 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } 385 386 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } 387 388 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } 389 390 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } 391 392 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } 393 394 static inline uint32_t __offset_STAGE_CO3(uint32_t idx) 395 { 396 switch (idx) { 397 case 0: return 0x00001004; 398 case 1: return 0x00001404; 399 case 2: return 0x00001804; 400 case 3: return 0x00001b84; 401 default: return INVALID_IDX(idx); 402 } 403 } 404 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } 405 406 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } 407 #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001 408 409 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); } 410 411 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); } 412 413 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); } 414 415 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); } 416 417 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); } 418 419 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } 420 421 422 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } 423 424 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } 425 426 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } 427 428 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } 429 430 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } 431 432 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } 433 434 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } 435 436 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } 437 438 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } 439 440 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } 441 442 #define REG_MDP4_DMA_P_OP_MODE 0x00090070 443 444 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } 445 446 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } 447 448 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } 449 450 #define REG_MDP4_DMA_S_OP_MODE 0x000a0028 451 452 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } 453 454 static inline uint32_t __offset_DMA(enum mdp4_dma idx) 455 { 456 switch (idx) { 457 case DMA_P: return 0x00090000; 458 case DMA_S: return 0x000a0000; 459 case DMA_E: return 0x000b0000; 460 default: return INVALID_IDX(idx); 461 } 462 } 463 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } 464 465 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } 466 #define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003 467 #define MDP4_DMA_CONFIG_G_BPC__SHIFT 0 468 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) 469 { 470 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; 471 } 472 #define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c 473 #define MDP4_DMA_CONFIG_B_BPC__SHIFT 2 474 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) 475 { 476 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; 477 } 478 #define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030 479 #define MDP4_DMA_CONFIG_R_BPC__SHIFT 4 480 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) 481 { 482 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; 483 } 484 #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080 485 #define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00 486 #define MDP4_DMA_CONFIG_PACK__SHIFT 8 487 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) 488 { 489 return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK; 490 } 491 #define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000 492 #define MDP4_DMA_CONFIG_DITHER_EN 0x01000000 493 494 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } 495 #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000 496 #define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16 497 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) 498 { 499 return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK; 500 } 501 #define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff 502 #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0 503 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) 504 { 505 return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK; 506 } 507 508 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } 509 510 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } 511 512 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } 513 #define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000 514 #define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16 515 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) 516 { 517 return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK; 518 } 519 #define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff 520 #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0 521 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) 522 { 523 return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK; 524 } 525 526 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } 527 #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f 528 #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0 529 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) 530 { 531 return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK; 532 } 533 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000 534 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16 535 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) 536 { 537 return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK; 538 } 539 540 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); } 541 542 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); } 543 #define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff 544 #define MDP4_DMA_CURSOR_POS_X__SHIFT 0 545 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) 546 { 547 return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK; 548 } 549 #define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000 550 #define MDP4_DMA_CURSOR_POS_Y__SHIFT 16 551 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) 552 { 553 return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK; 554 } 555 556 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); } 557 #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001 558 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006 559 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1 560 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) 561 { 562 return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK; 563 } 564 #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008 565 566 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); } 567 568 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); } 569 570 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); } 571 572 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); } 573 574 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } 575 576 577 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } 578 579 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } 580 581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } 582 583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } 584 585 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } 586 587 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } 588 589 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } 590 591 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } 592 593 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } 594 595 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } 596 597 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } 598 599 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } 600 #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000 601 #define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16 602 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) 603 { 604 return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK; 605 } 606 #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff 607 #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0 608 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) 609 { 610 return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK; 611 } 612 613 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } 614 #define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000 615 #define MDP4_PIPE_SRC_XY_Y__SHIFT 16 616 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) 617 { 618 return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK; 619 } 620 #define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff 621 #define MDP4_PIPE_SRC_XY_X__SHIFT 0 622 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) 623 { 624 return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK; 625 } 626 627 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } 628 #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000 629 #define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16 630 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) 631 { 632 return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK; 633 } 634 #define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff 635 #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0 636 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) 637 { 638 return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK; 639 } 640 641 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } 642 #define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000 643 #define MDP4_PIPE_DST_XY_Y__SHIFT 16 644 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) 645 { 646 return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK; 647 } 648 #define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff 649 #define MDP4_PIPE_DST_XY_X__SHIFT 0 650 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) 651 { 652 return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK; 653 } 654 655 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; } 656 657 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; } 658 659 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; } 660 661 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; } 662 663 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } 664 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff 665 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0 666 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) 667 { 668 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK; 669 } 670 #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000 671 #define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16 672 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) 673 { 674 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK; 675 } 676 677 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } 678 #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff 679 #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0 680 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) 681 { 682 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK; 683 } 684 #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000 685 #define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16 686 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) 687 { 688 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK; 689 } 690 691 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } 692 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000 693 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16 694 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) 695 { 696 return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK; 697 } 698 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff 699 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0 700 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) 701 { 702 return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK; 703 } 704 705 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } 706 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 707 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 708 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) 709 { 710 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; 711 } 712 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c 713 #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2 714 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) 715 { 716 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; 717 } 718 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030 719 #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4 720 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) 721 { 722 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; 723 } 724 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0 725 #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6 726 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) 727 { 728 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; 729 } 730 #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100 731 #define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600 732 #define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9 733 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) 734 { 735 return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK; 736 } 737 #define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000 738 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000 739 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13 740 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) 741 { 742 return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; 743 } 744 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000 745 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 746 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000 747 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19 748 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) 749 { 750 return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK; 751 } 752 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000 753 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000 754 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26 755 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) 756 { 757 return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; 758 } 759 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000 760 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29 761 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) 762 { 763 return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK; 764 } 765 766 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; } 767 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff 768 #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0 769 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) 770 { 771 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK; 772 } 773 #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00 774 #define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8 775 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) 776 { 777 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK; 778 } 779 #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000 780 #define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16 781 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) 782 { 783 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK; 784 } 785 #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000 786 #define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24 787 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) 788 { 789 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK; 790 } 791 792 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } 793 #define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001 794 #define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002 795 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c 796 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2 797 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) 798 { 799 return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK; 800 } 801 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030 802 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4 803 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) 804 { 805 return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK; 806 } 807 #define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200 808 #define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400 809 #define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800 810 #define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000 811 #define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000 812 #define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000 813 #define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000 814 #define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000 815 #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000 816 817 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } 818 819 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } 820 821 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } 822 823 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } 824 825 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } 826 827 828 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 829 830 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } 831 832 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 833 834 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } 835 836 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 837 838 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } 839 840 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 841 842 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } 843 844 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 845 846 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } 847 848 #define REG_MDP4_LCDC 0x000c0000 849 850 #define REG_MDP4_LCDC_ENABLE 0x000c0000 851 852 #define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004 853 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 854 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0 855 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) 856 { 857 return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK; 858 } 859 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000 860 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16 861 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) 862 { 863 return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK; 864 } 865 866 #define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008 867 868 #define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c 869 870 #define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010 871 #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff 872 #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0 873 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) 874 { 875 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK; 876 } 877 #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000 878 #define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16 879 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) 880 { 881 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK; 882 } 883 884 #define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014 885 886 #define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018 887 888 #define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c 889 #define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff 890 #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0 891 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) 892 { 893 return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK; 894 } 895 #define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000 896 #define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16 897 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) 898 { 899 return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK; 900 } 901 #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 902 903 #define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020 904 905 #define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024 906 907 #define REG_MDP4_LCDC_BORDER_CLR 0x000c0028 908 909 #define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c 910 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 911 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0 912 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) 913 { 914 return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK; 915 } 916 #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 917 918 #define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030 919 920 #define REG_MDP4_LCDC_TEST_CNTL 0x000c0034 921 922 #define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038 923 #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001 924 #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002 925 #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004 926 927 #define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000 928 #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004 929 #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008 930 #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010 931 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020 932 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040 933 #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080 934 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100 935 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200 936 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400 937 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800 938 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000 939 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000 940 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000 941 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000 942 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000 943 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000 944 945 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } 946 947 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; } 948 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff 949 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0 950 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) 951 { 952 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK; 953 } 954 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00 955 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8 956 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) 957 { 958 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK; 959 } 960 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000 961 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16 962 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) 963 { 964 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK; 965 } 966 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000 967 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24 968 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) 969 { 970 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK; 971 } 972 973 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; } 974 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff 975 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0 976 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) 977 { 978 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK; 979 } 980 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00 981 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8 982 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) 983 { 984 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK; 985 } 986 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000 987 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16 988 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) 989 { 990 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK; 991 } 992 993 #define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034 994 995 #define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000 996 997 #define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004 998 999 #define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008 1000 1001 #define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c 1002 1003 #define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014 1004 1005 #define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018 1006 1007 #define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c 1008 1009 #define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020 1010 1011 #define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024 1012 1013 #define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080 1014 1015 #define REG_MDP4_LVDS_PHY_CFG2 0x000c3108 1016 1017 #define REG_MDP4_LVDS_PHY_CFG0 0x000c3100 1018 #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010 1019 #define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040 1020 #define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080 1021 1022 #define REG_MDP4_DTV 0x000d0000 1023 1024 #define REG_MDP4_DTV_ENABLE 0x000d0000 1025 1026 #define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004 1027 #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 1028 #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0 1029 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) 1030 { 1031 return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK; 1032 } 1033 #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000 1034 #define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16 1035 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) 1036 { 1037 return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK; 1038 } 1039 1040 #define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008 1041 1042 #define REG_MDP4_DTV_VSYNC_LEN 0x000d000c 1043 1044 #define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018 1045 #define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff 1046 #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0 1047 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) 1048 { 1049 return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK; 1050 } 1051 #define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000 1052 #define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16 1053 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) 1054 { 1055 return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK; 1056 } 1057 1058 #define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c 1059 1060 #define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020 1061 1062 #define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c 1063 #define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff 1064 #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0 1065 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) 1066 { 1067 return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK; 1068 } 1069 #define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000 1070 #define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16 1071 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) 1072 { 1073 return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK; 1074 } 1075 #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 1076 1077 #define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030 1078 1079 #define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038 1080 1081 #define REG_MDP4_DTV_BORDER_CLR 0x000d0040 1082 1083 #define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044 1084 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 1085 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0 1086 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) 1087 { 1088 return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK; 1089 } 1090 #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 1091 1092 #define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048 1093 1094 #define REG_MDP4_DTV_TEST_CNTL 0x000d004c 1095 1096 #define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050 1097 #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001 1098 #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002 1099 #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004 1100 1101 #define REG_MDP4_DSI 0x000e0000 1102 1103 #define REG_MDP4_DSI_ENABLE 0x000e0000 1104 1105 #define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004 1106 #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff 1107 #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0 1108 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) 1109 { 1110 return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK; 1111 } 1112 #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000 1113 #define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16 1114 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) 1115 { 1116 return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK; 1117 } 1118 1119 #define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008 1120 1121 #define REG_MDP4_DSI_VSYNC_LEN 0x000e000c 1122 1123 #define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010 1124 #define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff 1125 #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0 1126 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) 1127 { 1128 return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK; 1129 } 1130 #define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000 1131 #define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16 1132 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) 1133 { 1134 return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK; 1135 } 1136 1137 #define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014 1138 1139 #define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018 1140 1141 #define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c 1142 #define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff 1143 #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0 1144 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) 1145 { 1146 return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK; 1147 } 1148 #define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000 1149 #define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16 1150 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) 1151 { 1152 return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK; 1153 } 1154 #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000 1155 1156 #define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020 1157 1158 #define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024 1159 1160 #define REG_MDP4_DSI_BORDER_CLR 0x000e0028 1161 1162 #define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c 1163 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff 1164 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0 1165 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) 1166 { 1167 return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK; 1168 } 1169 #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000 1170 1171 #define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030 1172 1173 #define REG_MDP4_DSI_TEST_CNTL 0x000e0034 1174 1175 #define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038 1176 #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001 1177 #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002 1178 #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004 1179 1180 1181 #endif /* MDP4_XML */ 1182