114be3200SRob Clark #ifndef MDP4_XML
214be3200SRob Clark #define MDP4_XML
314be3200SRob Clark
414be3200SRob Clark /* Autogenerated file, DO NOT EDIT manually!
514be3200SRob Clark
614be3200SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository:
714be3200SRob Clark http://github.com/freedreno/envytools/
814be3200SRob Clark git clone https://github.com/freedreno/envytools.git
914be3200SRob Clark
1014be3200SRob Clark The rules-ng-ng source files this header was generated from are:
11*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
2914be3200SRob Clark
30*f73343faSRob Clark Copyright (C) 2013-2022 by the following authors:
3114be3200SRob Clark - Rob Clark <robdclark@gmail.com> (robclark)
3214be3200SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
3314be3200SRob Clark
3414be3200SRob Clark Permission is hereby granted, free of charge, to any person obtaining
3514be3200SRob Clark a copy of this software and associated documentation files (the
3614be3200SRob Clark "Software"), to deal in the Software without restriction, including
3714be3200SRob Clark without limitation the rights to use, copy, modify, merge, publish,
3814be3200SRob Clark distribute, sublicense, and/or sell copies of the Software, and to
3914be3200SRob Clark permit persons to whom the Software is furnished to do so, subject to
4014be3200SRob Clark the following conditions:
4114be3200SRob Clark
4214be3200SRob Clark The above copyright notice and this permission notice (including the
4314be3200SRob Clark next paragraph) shall be included in all copies or substantial
4414be3200SRob Clark portions of the Software.
4514be3200SRob Clark
4614be3200SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4714be3200SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
4814be3200SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
4914be3200SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
5014be3200SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
5114be3200SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
5214be3200SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
5314be3200SRob Clark */
5414be3200SRob Clark
5514be3200SRob Clark
5614be3200SRob Clark enum mdp4_pipe {
5714be3200SRob Clark VG1 = 0,
5814be3200SRob Clark VG2 = 1,
5914be3200SRob Clark RGB1 = 2,
6014be3200SRob Clark RGB2 = 3,
6114be3200SRob Clark RGB3 = 4,
6214be3200SRob Clark VG3 = 5,
6314be3200SRob Clark VG4 = 6,
6414be3200SRob Clark };
6514be3200SRob Clark
6614be3200SRob Clark enum mdp4_mixer {
6714be3200SRob Clark MIXER0 = 0,
6814be3200SRob Clark MIXER1 = 1,
6914be3200SRob Clark MIXER2 = 2,
7014be3200SRob Clark };
7114be3200SRob Clark
7214be3200SRob Clark enum mdp4_intf {
7314be3200SRob Clark INTF_LCDC_DTV = 0,
7414be3200SRob Clark INTF_DSI_VIDEO = 1,
7514be3200SRob Clark INTF_DSI_CMD = 2,
7614be3200SRob Clark INTF_EBI2_TV = 3,
7714be3200SRob Clark };
7814be3200SRob Clark
7914be3200SRob Clark enum mdp4_cursor_format {
8014be3200SRob Clark CURSOR_ARGB = 1,
8114be3200SRob Clark CURSOR_XRGB = 2,
8214be3200SRob Clark };
8314be3200SRob Clark
8414be3200SRob Clark enum mdp4_frame_format {
8514be3200SRob Clark FRAME_LINEAR = 0,
8614be3200SRob Clark FRAME_TILE_ARGB_4X4 = 1,
8714be3200SRob Clark FRAME_TILE_YCBCR_420 = 2,
8814be3200SRob Clark };
8914be3200SRob Clark
9014be3200SRob Clark enum mdp4_scale_unit {
9114be3200SRob Clark SCALE_FIR = 0,
9214be3200SRob Clark SCALE_MN_PHASE = 1,
9314be3200SRob Clark SCALE_PIXEL_RPT = 2,
9414be3200SRob Clark };
9514be3200SRob Clark
9614be3200SRob Clark enum mdp4_dma {
9714be3200SRob Clark DMA_P = 0,
9814be3200SRob Clark DMA_S = 1,
9914be3200SRob Clark DMA_E = 2,
10014be3200SRob Clark };
10114be3200SRob Clark
10214be3200SRob Clark #define MDP4_IRQ_OVERLAY0_DONE 0x00000001
10314be3200SRob Clark #define MDP4_IRQ_OVERLAY1_DONE 0x00000002
10414be3200SRob Clark #define MDP4_IRQ_DMA_S_DONE 0x00000004
10514be3200SRob Clark #define MDP4_IRQ_DMA_E_DONE 0x00000008
10614be3200SRob Clark #define MDP4_IRQ_DMA_P_DONE 0x00000010
10714be3200SRob Clark #define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
10814be3200SRob Clark #define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
10914be3200SRob Clark #define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
11014be3200SRob Clark #define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
11114be3200SRob Clark #define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
11214be3200SRob Clark #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
11314be3200SRob Clark #define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
11414be3200SRob Clark #define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
11514be3200SRob Clark #define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
11614be3200SRob Clark #define MDP4_IRQ_OVERLAY2_DONE 0x40000000
11714be3200SRob Clark #define REG_MDP4_VERSION 0x00000000
11814be3200SRob Clark #define MDP4_VERSION_MINOR__MASK 0x00ff0000
11914be3200SRob Clark #define MDP4_VERSION_MINOR__SHIFT 16
MDP4_VERSION_MINOR(uint32_t val)12014be3200SRob Clark static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
12114be3200SRob Clark {
12214be3200SRob Clark return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
12314be3200SRob Clark }
12414be3200SRob Clark #define MDP4_VERSION_MAJOR__MASK 0xff000000
12514be3200SRob Clark #define MDP4_VERSION_MAJOR__SHIFT 24
MDP4_VERSION_MAJOR(uint32_t val)12614be3200SRob Clark static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
12714be3200SRob Clark {
12814be3200SRob Clark return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
12914be3200SRob Clark }
13014be3200SRob Clark
13114be3200SRob Clark #define REG_MDP4_OVLP0_KICK 0x00000004
13214be3200SRob Clark
13314be3200SRob Clark #define REG_MDP4_OVLP1_KICK 0x00000008
13414be3200SRob Clark
13514be3200SRob Clark #define REG_MDP4_OVLP2_KICK 0x000000d0
13614be3200SRob Clark
13714be3200SRob Clark #define REG_MDP4_DMA_P_KICK 0x0000000c
13814be3200SRob Clark
13914be3200SRob Clark #define REG_MDP4_DMA_S_KICK 0x00000010
14014be3200SRob Clark
14114be3200SRob Clark #define REG_MDP4_DMA_E_KICK 0x00000014
14214be3200SRob Clark
14314be3200SRob Clark #define REG_MDP4_DISP_STATUS 0x00000018
14414be3200SRob Clark
14514be3200SRob Clark #define REG_MDP4_DISP_INTF_SEL 0x00000038
14614be3200SRob Clark #define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
14714be3200SRob Clark #define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)14814be3200SRob Clark static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
14914be3200SRob Clark {
15014be3200SRob Clark return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
15114be3200SRob Clark }
15214be3200SRob Clark #define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
15314be3200SRob Clark #define MDP4_DISP_INTF_SEL_SEC__SHIFT 2
MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)15414be3200SRob Clark static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
15514be3200SRob Clark {
15614be3200SRob Clark return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
15714be3200SRob Clark }
15814be3200SRob Clark #define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
15914be3200SRob Clark #define MDP4_DISP_INTF_SEL_EXT__SHIFT 4
MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)16014be3200SRob Clark static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
16114be3200SRob Clark {
16214be3200SRob Clark return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
16314be3200SRob Clark }
16414be3200SRob Clark #define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
16514be3200SRob Clark #define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
16614be3200SRob Clark
16714be3200SRob Clark #define REG_MDP4_RESET_STATUS 0x0000003c
16814be3200SRob Clark
16914be3200SRob Clark #define REG_MDP4_READ_CNFG 0x0000004c
17014be3200SRob Clark
17114be3200SRob Clark #define REG_MDP4_INTR_ENABLE 0x00000050
17214be3200SRob Clark
17314be3200SRob Clark #define REG_MDP4_INTR_STATUS 0x00000054
17414be3200SRob Clark
17514be3200SRob Clark #define REG_MDP4_INTR_CLEAR 0x00000058
17614be3200SRob Clark
17714be3200SRob Clark #define REG_MDP4_EBI2_LCD0 0x00000060
17814be3200SRob Clark
17914be3200SRob Clark #define REG_MDP4_EBI2_LCD1 0x00000064
18014be3200SRob Clark
18114be3200SRob Clark #define REG_MDP4_PORTMAP_MODE 0x00000070
18214be3200SRob Clark
18314be3200SRob Clark #define REG_MDP4_CS_CONTROLLER0 0x000000c0
18414be3200SRob Clark
18514be3200SRob Clark #define REG_MDP4_CS_CONTROLLER1 0x000000c4
18614be3200SRob Clark
18714be3200SRob Clark #define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
18814be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
18914be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)19014be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
19114be3200SRob Clark {
19214be3200SRob Clark return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
19314be3200SRob Clark }
19414be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
19514be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
19614be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)19714be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
19814be3200SRob Clark {
19914be3200SRob Clark return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
20014be3200SRob Clark }
20114be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
20214be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
20314be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)20414be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
20514be3200SRob Clark {
20614be3200SRob Clark return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
20714be3200SRob Clark }
20814be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
20914be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
21014be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)21114be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
21214be3200SRob Clark {
21314be3200SRob Clark return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
21414be3200SRob Clark }
21514be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
21614be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
21714be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)21814be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
21914be3200SRob Clark {
22014be3200SRob Clark return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
22114be3200SRob Clark }
22214be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
22314be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
22414be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)22514be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
22614be3200SRob Clark {
22714be3200SRob Clark return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
22814be3200SRob Clark }
22914be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
23014be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
23114be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)23214be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
23314be3200SRob Clark {
23414be3200SRob Clark return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
23514be3200SRob Clark }
23614be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
23714be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
23814be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)23914be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
24014be3200SRob Clark {
24114be3200SRob Clark return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
24214be3200SRob Clark }
24314be3200SRob Clark #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
24414be3200SRob Clark
24514be3200SRob Clark #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
24614be3200SRob Clark
24714be3200SRob Clark #define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
24814be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
24914be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)25014be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
25114be3200SRob Clark {
25214be3200SRob Clark return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
25314be3200SRob Clark }
25414be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
25514be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
25614be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)25714be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
25814be3200SRob Clark {
25914be3200SRob Clark return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
26014be3200SRob Clark }
26114be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
26214be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
26314be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)26414be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
26514be3200SRob Clark {
26614be3200SRob Clark return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
26714be3200SRob Clark }
26814be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
26914be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
27014be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)27114be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
27214be3200SRob Clark {
27314be3200SRob Clark return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
27414be3200SRob Clark }
27514be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
27614be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
27714be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)27814be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
27914be3200SRob Clark {
28014be3200SRob Clark return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
28114be3200SRob Clark }
28214be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
28314be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
28414be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)28514be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
28614be3200SRob Clark {
28714be3200SRob Clark return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
28814be3200SRob Clark }
28914be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
29014be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
29114be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)29214be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
29314be3200SRob Clark {
29414be3200SRob Clark return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
29514be3200SRob Clark }
29614be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
29714be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
29814be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)29914be3200SRob Clark static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
30014be3200SRob Clark {
30114be3200SRob Clark return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
30214be3200SRob Clark }
30314be3200SRob Clark #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
30414be3200SRob Clark
30514be3200SRob Clark #define REG_MDP4_VG2_SRC_FORMAT 0x00030050
30614be3200SRob Clark
30714be3200SRob Clark #define REG_MDP4_VG2_CONST_COLOR 0x00031008
30814be3200SRob Clark
30914be3200SRob Clark #define REG_MDP4_OVERLAY_FLUSH 0x00018000
31014be3200SRob Clark #define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
31114be3200SRob Clark #define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
31214be3200SRob Clark #define MDP4_OVERLAY_FLUSH_VG1 0x00000004
31314be3200SRob Clark #define MDP4_OVERLAY_FLUSH_VG2 0x00000008
31414be3200SRob Clark #define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
31514be3200SRob Clark #define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
31614be3200SRob Clark
__offset_OVLP(uint32_t idx)31714be3200SRob Clark static inline uint32_t __offset_OVLP(uint32_t idx)
31814be3200SRob Clark {
31914be3200SRob Clark switch (idx) {
32014be3200SRob Clark case 0: return 0x00010000;
32114be3200SRob Clark case 1: return 0x00018000;
32214be3200SRob Clark case 2: return 0x00088000;
32314be3200SRob Clark default: return INVALID_IDX(idx);
32414be3200SRob Clark }
32514be3200SRob Clark }
REG_MDP4_OVLP(uint32_t i0)32614be3200SRob Clark static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
32714be3200SRob Clark
REG_MDP4_OVLP_CFG(uint32_t i0)32814be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
32914be3200SRob Clark
REG_MDP4_OVLP_SIZE(uint32_t i0)33014be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
33114be3200SRob Clark #define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
33214be3200SRob Clark #define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16
MDP4_OVLP_SIZE_HEIGHT(uint32_t val)33314be3200SRob Clark static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
33414be3200SRob Clark {
33514be3200SRob Clark return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
33614be3200SRob Clark }
33714be3200SRob Clark #define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
33814be3200SRob Clark #define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
MDP4_OVLP_SIZE_WIDTH(uint32_t val)33914be3200SRob Clark static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
34014be3200SRob Clark {
34114be3200SRob Clark return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
34214be3200SRob Clark }
34314be3200SRob Clark
REG_MDP4_OVLP_BASE(uint32_t i0)34414be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
34514be3200SRob Clark
REG_MDP4_OVLP_STRIDE(uint32_t i0)34614be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
34714be3200SRob Clark
REG_MDP4_OVLP_OPMODE(uint32_t i0)34814be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
34914be3200SRob Clark
__offset_STAGE(uint32_t idx)35014be3200SRob Clark static inline uint32_t __offset_STAGE(uint32_t idx)
35114be3200SRob Clark {
35214be3200SRob Clark switch (idx) {
35314be3200SRob Clark case 0: return 0x00000104;
35414be3200SRob Clark case 1: return 0x00000124;
35514be3200SRob Clark case 2: return 0x00000144;
35614be3200SRob Clark case 3: return 0x00000160;
35714be3200SRob Clark default: return INVALID_IDX(idx);
35814be3200SRob Clark }
35914be3200SRob Clark }
REG_MDP4_OVLP_STAGE(uint32_t i0,uint32_t i1)36014be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
36114be3200SRob Clark
REG_MDP4_OVLP_STAGE_OP(uint32_t i0,uint32_t i1)36214be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
36314be3200SRob Clark #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
36414be3200SRob Clark #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)36514be3200SRob Clark static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
36614be3200SRob Clark {
36714be3200SRob Clark return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
36814be3200SRob Clark }
36914be3200SRob Clark #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
37014be3200SRob Clark #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
37114be3200SRob Clark #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
37214be3200SRob Clark #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)37314be3200SRob Clark static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
37414be3200SRob Clark {
37514be3200SRob Clark return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
37614be3200SRob Clark }
37714be3200SRob Clark #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
37814be3200SRob Clark #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
37914be3200SRob Clark #define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
38014be3200SRob Clark #define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
38114be3200SRob Clark
REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0,uint32_t i1)38214be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
38314be3200SRob Clark
REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0,uint32_t i1)38414be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
38514be3200SRob Clark
REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0,uint32_t i1)38614be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
38714be3200SRob Clark
REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0,uint32_t i1)38814be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
38914be3200SRob Clark
REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0,uint32_t i1)39014be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
39114be3200SRob Clark
REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0,uint32_t i1)39214be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
39314be3200SRob Clark
__offset_STAGE_CO3(uint32_t idx)39414be3200SRob Clark static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
39514be3200SRob Clark {
39614be3200SRob Clark switch (idx) {
39714be3200SRob Clark case 0: return 0x00001004;
39814be3200SRob Clark case 1: return 0x00001404;
39914be3200SRob Clark case 2: return 0x00001804;
40014be3200SRob Clark case 3: return 0x00001b84;
40114be3200SRob Clark default: return INVALID_IDX(idx);
40214be3200SRob Clark }
40314be3200SRob Clark }
REG_MDP4_OVLP_STAGE_CO3(uint32_t i0,uint32_t i1)40414be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
40514be3200SRob Clark
REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0,uint32_t i1)40614be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
40714be3200SRob Clark #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
40814be3200SRob Clark
REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0)40914be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
41014be3200SRob Clark
REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0)41114be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
41214be3200SRob Clark
REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0)41314be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
41414be3200SRob Clark
REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0)41514be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
41614be3200SRob Clark
REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0)41714be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
41814be3200SRob Clark
REG_MDP4_OVLP_CSC(uint32_t i0)41914be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
42014be3200SRob Clark
42114be3200SRob Clark
REG_MDP4_OVLP_CSC_MV(uint32_t i0,uint32_t i1)42214be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
42314be3200SRob Clark
REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0,uint32_t i1)42414be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
42514be3200SRob Clark
REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0,uint32_t i1)42614be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
42714be3200SRob Clark
REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0,uint32_t i1)42814be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
42914be3200SRob Clark
REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0,uint32_t i1)43014be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
43114be3200SRob Clark
REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0,uint32_t i1)43214be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
43314be3200SRob Clark
REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0,uint32_t i1)43414be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
43514be3200SRob Clark
REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0,uint32_t i1)43614be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
43714be3200SRob Clark
REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0,uint32_t i1)43814be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
43914be3200SRob Clark
REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0,uint32_t i1)44014be3200SRob Clark static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
44114be3200SRob Clark
44214be3200SRob Clark #define REG_MDP4_DMA_P_OP_MODE 0x00090070
44314be3200SRob Clark
REG_MDP4_LUTN(uint32_t i0)44414be3200SRob Clark static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
44514be3200SRob Clark
REG_MDP4_LUTN_LUT(uint32_t i0,uint32_t i1)44614be3200SRob Clark static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
44714be3200SRob Clark
REG_MDP4_LUTN_LUT_VAL(uint32_t i0,uint32_t i1)44814be3200SRob Clark static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
44914be3200SRob Clark
45014be3200SRob Clark #define REG_MDP4_DMA_S_OP_MODE 0x000a0028
45114be3200SRob Clark
REG_MDP4_DMA_E_QUANT(uint32_t i0)45214be3200SRob Clark static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
45314be3200SRob Clark
__offset_DMA(enum mdp4_dma idx)45414be3200SRob Clark static inline uint32_t __offset_DMA(enum mdp4_dma idx)
45514be3200SRob Clark {
45614be3200SRob Clark switch (idx) {
45714be3200SRob Clark case DMA_P: return 0x00090000;
45814be3200SRob Clark case DMA_S: return 0x000a0000;
45914be3200SRob Clark case DMA_E: return 0x000b0000;
46014be3200SRob Clark default: return INVALID_IDX(idx);
46114be3200SRob Clark }
46214be3200SRob Clark }
REG_MDP4_DMA(enum mdp4_dma i0)46314be3200SRob Clark static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
46414be3200SRob Clark
REG_MDP4_DMA_CONFIG(enum mdp4_dma i0)46514be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
46614be3200SRob Clark #define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
46714be3200SRob Clark #define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)46814be3200SRob Clark static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
46914be3200SRob Clark {
47014be3200SRob Clark return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
47114be3200SRob Clark }
47214be3200SRob Clark #define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
47314be3200SRob Clark #define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)47414be3200SRob Clark static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
47514be3200SRob Clark {
47614be3200SRob Clark return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
47714be3200SRob Clark }
47814be3200SRob Clark #define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
47914be3200SRob Clark #define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)48014be3200SRob Clark static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
48114be3200SRob Clark {
48214be3200SRob Clark return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
48314be3200SRob Clark }
48414be3200SRob Clark #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
48514be3200SRob Clark #define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
48614be3200SRob Clark #define MDP4_DMA_CONFIG_PACK__SHIFT 8
MDP4_DMA_CONFIG_PACK(uint32_t val)48714be3200SRob Clark static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
48814be3200SRob Clark {
48914be3200SRob Clark return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
49014be3200SRob Clark }
49114be3200SRob Clark #define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
49214be3200SRob Clark #define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
49314be3200SRob Clark
REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0)49414be3200SRob Clark static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
49514be3200SRob Clark #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
49614be3200SRob Clark #define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16
MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)49714be3200SRob Clark static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
49814be3200SRob Clark {
49914be3200SRob Clark return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
50014be3200SRob Clark }
50114be3200SRob Clark #define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
50214be3200SRob Clark #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)50314be3200SRob Clark static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
50414be3200SRob Clark {
50514be3200SRob Clark return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
50614be3200SRob Clark }
50714be3200SRob Clark
REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0)50814be3200SRob Clark static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
50914be3200SRob Clark
REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0)51014be3200SRob Clark static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
51114be3200SRob Clark
REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0)51214be3200SRob Clark static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
51314be3200SRob Clark #define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
51414be3200SRob Clark #define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16
MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)51514be3200SRob Clark static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
51614be3200SRob Clark {
51714be3200SRob Clark return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
51814be3200SRob Clark }
51914be3200SRob Clark #define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
52014be3200SRob Clark #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)52114be3200SRob Clark static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
52214be3200SRob Clark {
52314be3200SRob Clark return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
52414be3200SRob Clark }
52514be3200SRob Clark
REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0)52614be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
52714be3200SRob Clark #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
52814be3200SRob Clark #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)52914be3200SRob Clark static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
53014be3200SRob Clark {
53114be3200SRob Clark return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
53214be3200SRob Clark }
53314be3200SRob Clark #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
53414be3200SRob Clark #define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16
MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)53514be3200SRob Clark static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
53614be3200SRob Clark {
53714be3200SRob Clark return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
53814be3200SRob Clark }
53914be3200SRob Clark
REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0)54014be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
54114be3200SRob Clark
REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0)54214be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
54314be3200SRob Clark #define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
54414be3200SRob Clark #define MDP4_DMA_CURSOR_POS_X__SHIFT 0
MDP4_DMA_CURSOR_POS_X(uint32_t val)54514be3200SRob Clark static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
54614be3200SRob Clark {
54714be3200SRob Clark return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
54814be3200SRob Clark }
54914be3200SRob Clark #define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
55014be3200SRob Clark #define MDP4_DMA_CURSOR_POS_Y__SHIFT 16
MDP4_DMA_CURSOR_POS_Y(uint32_t val)55114be3200SRob Clark static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
55214be3200SRob Clark {
55314be3200SRob Clark return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
55414be3200SRob Clark }
55514be3200SRob Clark
REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0)55614be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
55714be3200SRob Clark #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
55814be3200SRob Clark #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
55914be3200SRob Clark #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1
MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)56014be3200SRob Clark static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
56114be3200SRob Clark {
56214be3200SRob Clark return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
56314be3200SRob Clark }
56414be3200SRob Clark #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
56514be3200SRob Clark
REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0)56614be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
56714be3200SRob Clark
REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0)56814be3200SRob Clark static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
56914be3200SRob Clark
REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0)57014be3200SRob Clark static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
57114be3200SRob Clark
REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0)57214be3200SRob Clark static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
57314be3200SRob Clark
REG_MDP4_DMA_CSC(enum mdp4_dma i0)57414be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
57514be3200SRob Clark
57614be3200SRob Clark
REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0,uint32_t i1)57714be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
57814be3200SRob Clark
REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0,uint32_t i1)57914be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
58014be3200SRob Clark
REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0,uint32_t i1)58114be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
58214be3200SRob Clark
REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0,uint32_t i1)58314be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
58414be3200SRob Clark
REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0,uint32_t i1)58514be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
58614be3200SRob Clark
REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0,uint32_t i1)58714be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
58814be3200SRob Clark
REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0,uint32_t i1)58914be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
59014be3200SRob Clark
REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0,uint32_t i1)59114be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
59214be3200SRob Clark
REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0,uint32_t i1)59314be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
59414be3200SRob Clark
REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0,uint32_t i1)59514be3200SRob Clark static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
59614be3200SRob Clark
REG_MDP4_PIPE(enum mdp4_pipe i0)59714be3200SRob Clark static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
59814be3200SRob Clark
REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0)59914be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
60014be3200SRob Clark #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
60114be3200SRob Clark #define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)60214be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
60314be3200SRob Clark {
60414be3200SRob Clark return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
60514be3200SRob Clark }
60614be3200SRob Clark #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
60714be3200SRob Clark #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)60814be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
60914be3200SRob Clark {
61014be3200SRob Clark return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
61114be3200SRob Clark }
61214be3200SRob Clark
REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0)61314be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
61414be3200SRob Clark #define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
61514be3200SRob Clark #define MDP4_PIPE_SRC_XY_Y__SHIFT 16
MDP4_PIPE_SRC_XY_Y(uint32_t val)61614be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
61714be3200SRob Clark {
61814be3200SRob Clark return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
61914be3200SRob Clark }
62014be3200SRob Clark #define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
62114be3200SRob Clark #define MDP4_PIPE_SRC_XY_X__SHIFT 0
MDP4_PIPE_SRC_XY_X(uint32_t val)62214be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
62314be3200SRob Clark {
62414be3200SRob Clark return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
62514be3200SRob Clark }
62614be3200SRob Clark
REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0)62714be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
62814be3200SRob Clark #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
62914be3200SRob Clark #define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)63014be3200SRob Clark static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
63114be3200SRob Clark {
63214be3200SRob Clark return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
63314be3200SRob Clark }
63414be3200SRob Clark #define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
63514be3200SRob Clark #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)63614be3200SRob Clark static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
63714be3200SRob Clark {
63814be3200SRob Clark return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
63914be3200SRob Clark }
64014be3200SRob Clark
REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0)64114be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
64214be3200SRob Clark #define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
64314be3200SRob Clark #define MDP4_PIPE_DST_XY_Y__SHIFT 16
MDP4_PIPE_DST_XY_Y(uint32_t val)64414be3200SRob Clark static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
64514be3200SRob Clark {
64614be3200SRob Clark return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
64714be3200SRob Clark }
64814be3200SRob Clark #define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
64914be3200SRob Clark #define MDP4_PIPE_DST_XY_X__SHIFT 0
MDP4_PIPE_DST_XY_X(uint32_t val)65014be3200SRob Clark static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
65114be3200SRob Clark {
65214be3200SRob Clark return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
65314be3200SRob Clark }
65414be3200SRob Clark
REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0)65514be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
65614be3200SRob Clark
REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0)65714be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
65814be3200SRob Clark
REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0)65914be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
66014be3200SRob Clark
REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0)66114be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
66214be3200SRob Clark
REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0)66314be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
66414be3200SRob Clark #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
66514be3200SRob Clark #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)66614be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
66714be3200SRob Clark {
66814be3200SRob Clark return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
66914be3200SRob Clark }
67014be3200SRob Clark #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
67114be3200SRob Clark #define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16
MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)67214be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
67314be3200SRob Clark {
67414be3200SRob Clark return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
67514be3200SRob Clark }
67614be3200SRob Clark
REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0)67714be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
67814be3200SRob Clark #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
67914be3200SRob Clark #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)68014be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
68114be3200SRob Clark {
68214be3200SRob Clark return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
68314be3200SRob Clark }
68414be3200SRob Clark #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
68514be3200SRob Clark #define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16
MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)68614be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
68714be3200SRob Clark {
68814be3200SRob Clark return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
68914be3200SRob Clark }
69014be3200SRob Clark
REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0)69114be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
69214be3200SRob Clark #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
69314be3200SRob Clark #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16
MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)69414be3200SRob Clark static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
69514be3200SRob Clark {
69614be3200SRob Clark return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
69714be3200SRob Clark }
69814be3200SRob Clark #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
69914be3200SRob Clark #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)70014be3200SRob Clark static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
70114be3200SRob Clark {
70214be3200SRob Clark return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
70314be3200SRob Clark }
70414be3200SRob Clark
REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0)70514be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
70614be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
70714be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)70814be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
70914be3200SRob Clark {
71014be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
71114be3200SRob Clark }
71214be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
71314be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)71414be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
71514be3200SRob Clark {
71614be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
71714be3200SRob Clark }
71814be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
71914be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)72014be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
72114be3200SRob Clark {
72214be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
72314be3200SRob Clark }
72414be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
72514be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)72614be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
72714be3200SRob Clark {
72814be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
72914be3200SRob Clark }
73014be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
73114be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
73214be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9
MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)73314be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
73414be3200SRob Clark {
73514be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
73614be3200SRob Clark }
73714be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
73814be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
73914be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)74014be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
74114be3200SRob Clark {
74214be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
74314be3200SRob Clark }
74414be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
74514be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
74614be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
74714be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)74814be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
74914be3200SRob Clark {
75014be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
75114be3200SRob Clark }
75214be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
75314be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
75414be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)75514be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
75614be3200SRob Clark {
75714be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
75814be3200SRob Clark }
75914be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
76014be3200SRob Clark #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29
MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)76114be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
76214be3200SRob Clark {
76314be3200SRob Clark return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
76414be3200SRob Clark }
76514be3200SRob Clark
REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0)76614be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
76714be3200SRob Clark #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
76814be3200SRob Clark #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)76914be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
77014be3200SRob Clark {
77114be3200SRob Clark return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
77214be3200SRob Clark }
77314be3200SRob Clark #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
77414be3200SRob Clark #define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)77514be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
77614be3200SRob Clark {
77714be3200SRob Clark return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
77814be3200SRob Clark }
77914be3200SRob Clark #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
78014be3200SRob Clark #define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)78114be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
78214be3200SRob Clark {
78314be3200SRob Clark return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
78414be3200SRob Clark }
78514be3200SRob Clark #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
78614be3200SRob Clark #define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)78714be3200SRob Clark static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
78814be3200SRob Clark {
78914be3200SRob Clark return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
79014be3200SRob Clark }
79114be3200SRob Clark
REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0)79214be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
79314be3200SRob Clark #define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
79414be3200SRob Clark #define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
79514be3200SRob Clark #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
79614be3200SRob Clark #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2
MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)79714be3200SRob Clark static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
79814be3200SRob Clark {
79914be3200SRob Clark return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
80014be3200SRob Clark }
80114be3200SRob Clark #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
80214be3200SRob Clark #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4
MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)80314be3200SRob Clark static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
80414be3200SRob Clark {
80514be3200SRob Clark return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
80614be3200SRob Clark }
80714be3200SRob Clark #define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
80814be3200SRob Clark #define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
80914be3200SRob Clark #define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
81014be3200SRob Clark #define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
81114be3200SRob Clark #define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
81214be3200SRob Clark #define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
81314be3200SRob Clark #define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
81414be3200SRob Clark #define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
81514be3200SRob Clark #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
81614be3200SRob Clark
REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0)81714be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
81814be3200SRob Clark
REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0)81914be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
82014be3200SRob Clark
REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0)82114be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
82214be3200SRob Clark
REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0)82314be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
82414be3200SRob Clark
REG_MDP4_PIPE_CSC(enum mdp4_pipe i0)82514be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
82614be3200SRob Clark
82714be3200SRob Clark
REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0,uint32_t i1)82814be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
82914be3200SRob Clark
REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0,uint32_t i1)83014be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
83114be3200SRob Clark
REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0,uint32_t i1)83214be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
83314be3200SRob Clark
REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0,uint32_t i1)83414be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
83514be3200SRob Clark
REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0,uint32_t i1)83614be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
83714be3200SRob Clark
REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0,uint32_t i1)83814be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
83914be3200SRob Clark
REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0,uint32_t i1)84014be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
84114be3200SRob Clark
REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0,uint32_t i1)84214be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
84314be3200SRob Clark
REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0,uint32_t i1)84414be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
84514be3200SRob Clark
REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0,uint32_t i1)84614be3200SRob Clark static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
84714be3200SRob Clark
84814be3200SRob Clark #define REG_MDP4_LCDC 0x000c0000
84914be3200SRob Clark
85014be3200SRob Clark #define REG_MDP4_LCDC_ENABLE 0x000c0000
85114be3200SRob Clark
85214be3200SRob Clark #define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
85314be3200SRob Clark #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
85414be3200SRob Clark #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)85514be3200SRob Clark static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
85614be3200SRob Clark {
85714be3200SRob Clark return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
85814be3200SRob Clark }
85914be3200SRob Clark #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
86014be3200SRob Clark #define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16
MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)86114be3200SRob Clark static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
86214be3200SRob Clark {
86314be3200SRob Clark return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
86414be3200SRob Clark }
86514be3200SRob Clark
86614be3200SRob Clark #define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
86714be3200SRob Clark
86814be3200SRob Clark #define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
86914be3200SRob Clark
87014be3200SRob Clark #define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
87114be3200SRob Clark #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
87214be3200SRob Clark #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)87314be3200SRob Clark static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
87414be3200SRob Clark {
87514be3200SRob Clark return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
87614be3200SRob Clark }
87714be3200SRob Clark #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
87814be3200SRob Clark #define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16
MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)87914be3200SRob Clark static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
88014be3200SRob Clark {
88114be3200SRob Clark return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
88214be3200SRob Clark }
88314be3200SRob Clark
88414be3200SRob Clark #define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
88514be3200SRob Clark
88614be3200SRob Clark #define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
88714be3200SRob Clark
88814be3200SRob Clark #define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
88914be3200SRob Clark #define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
89014be3200SRob Clark #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)89114be3200SRob Clark static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
89214be3200SRob Clark {
89314be3200SRob Clark return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
89414be3200SRob Clark }
89514be3200SRob Clark #define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
89614be3200SRob Clark #define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16
MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)89714be3200SRob Clark static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
89814be3200SRob Clark {
89914be3200SRob Clark return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
90014be3200SRob Clark }
90114be3200SRob Clark #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
90214be3200SRob Clark
90314be3200SRob Clark #define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
90414be3200SRob Clark
90514be3200SRob Clark #define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
90614be3200SRob Clark
90714be3200SRob Clark #define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
90814be3200SRob Clark
90914be3200SRob Clark #define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
91014be3200SRob Clark #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
91114be3200SRob Clark #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)91214be3200SRob Clark static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
91314be3200SRob Clark {
91414be3200SRob Clark return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
91514be3200SRob Clark }
91614be3200SRob Clark #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
91714be3200SRob Clark
91814be3200SRob Clark #define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
91914be3200SRob Clark
92014be3200SRob Clark #define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
92114be3200SRob Clark
92214be3200SRob Clark #define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
92314be3200SRob Clark #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
92414be3200SRob Clark #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
92514be3200SRob Clark #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
92614be3200SRob Clark
92714be3200SRob Clark #define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
92814be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
92914be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
93014be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
93114be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
93214be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
93314be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
93414be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
93514be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
93614be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
93714be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
93814be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
93914be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
94014be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
94114be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
94214be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
94314be3200SRob Clark #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
94414be3200SRob Clark
REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0)94514be3200SRob Clark static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
94614be3200SRob Clark
REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0)94714be3200SRob Clark static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
94814be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
94914be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)95014be3200SRob Clark static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)
95114be3200SRob Clark {
95214be3200SRob Clark return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK;
95314be3200SRob Clark }
95414be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
95514be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8
MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)95614be3200SRob Clark static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)
95714be3200SRob Clark {
95814be3200SRob Clark return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK;
95914be3200SRob Clark }
96014be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
96114be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16
MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)96214be3200SRob Clark static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)
96314be3200SRob Clark {
96414be3200SRob Clark return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK;
96514be3200SRob Clark }
96614be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
96714be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24
MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)96814be3200SRob Clark static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)
96914be3200SRob Clark {
97014be3200SRob Clark return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK;
97114be3200SRob Clark }
97214be3200SRob Clark
REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0)97314be3200SRob Clark static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; }
97414be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
97514be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)97614be3200SRob Clark static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)
97714be3200SRob Clark {
97814be3200SRob Clark return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK;
97914be3200SRob Clark }
98014be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
98114be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8
MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)98214be3200SRob Clark static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)
98314be3200SRob Clark {
98414be3200SRob Clark return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK;
98514be3200SRob Clark }
98614be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
98714be3200SRob Clark #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16
MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)98814be3200SRob Clark static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)
98914be3200SRob Clark {
99014be3200SRob Clark return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK;
99114be3200SRob Clark }
99214be3200SRob Clark
99314be3200SRob Clark #define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
99414be3200SRob Clark
99514be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
99614be3200SRob Clark
99714be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
99814be3200SRob Clark
99914be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
100014be3200SRob Clark
100114be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
100214be3200SRob Clark
100314be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
100414be3200SRob Clark
100514be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
100614be3200SRob Clark
100714be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
100814be3200SRob Clark
100914be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
101014be3200SRob Clark
101114be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
101214be3200SRob Clark
101314be3200SRob Clark #define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
101414be3200SRob Clark
101514be3200SRob Clark #define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
101614be3200SRob Clark
101714be3200SRob Clark #define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
101814be3200SRob Clark #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
101914be3200SRob Clark #define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
102014be3200SRob Clark #define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
102114be3200SRob Clark
102214be3200SRob Clark #define REG_MDP4_DTV 0x000d0000
102314be3200SRob Clark
102414be3200SRob Clark #define REG_MDP4_DTV_ENABLE 0x000d0000
102514be3200SRob Clark
102614be3200SRob Clark #define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
102714be3200SRob Clark #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
102814be3200SRob Clark #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)102914be3200SRob Clark static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
103014be3200SRob Clark {
103114be3200SRob Clark return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
103214be3200SRob Clark }
103314be3200SRob Clark #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
103414be3200SRob Clark #define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16
MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)103514be3200SRob Clark static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
103614be3200SRob Clark {
103714be3200SRob Clark return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
103814be3200SRob Clark }
103914be3200SRob Clark
104014be3200SRob Clark #define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
104114be3200SRob Clark
104214be3200SRob Clark #define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
104314be3200SRob Clark
104414be3200SRob Clark #define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
104514be3200SRob Clark #define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
104614be3200SRob Clark #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)104714be3200SRob Clark static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
104814be3200SRob Clark {
104914be3200SRob Clark return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
105014be3200SRob Clark }
105114be3200SRob Clark #define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
105214be3200SRob Clark #define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16
MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)105314be3200SRob Clark static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
105414be3200SRob Clark {
105514be3200SRob Clark return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
105614be3200SRob Clark }
105714be3200SRob Clark
105814be3200SRob Clark #define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
105914be3200SRob Clark
106014be3200SRob Clark #define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
106114be3200SRob Clark
106214be3200SRob Clark #define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
106314be3200SRob Clark #define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
106414be3200SRob Clark #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)106514be3200SRob Clark static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
106614be3200SRob Clark {
106714be3200SRob Clark return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
106814be3200SRob Clark }
106914be3200SRob Clark #define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
107014be3200SRob Clark #define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16
MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)107114be3200SRob Clark static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
107214be3200SRob Clark {
107314be3200SRob Clark return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
107414be3200SRob Clark }
107514be3200SRob Clark #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
107614be3200SRob Clark
107714be3200SRob Clark #define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
107814be3200SRob Clark
107914be3200SRob Clark #define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
108014be3200SRob Clark
108114be3200SRob Clark #define REG_MDP4_DTV_BORDER_CLR 0x000d0040
108214be3200SRob Clark
108314be3200SRob Clark #define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
108414be3200SRob Clark #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
108514be3200SRob Clark #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)108614be3200SRob Clark static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
108714be3200SRob Clark {
108814be3200SRob Clark return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
108914be3200SRob Clark }
109014be3200SRob Clark #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
109114be3200SRob Clark
109214be3200SRob Clark #define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
109314be3200SRob Clark
109414be3200SRob Clark #define REG_MDP4_DTV_TEST_CNTL 0x000d004c
109514be3200SRob Clark
109614be3200SRob Clark #define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
109714be3200SRob Clark #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
109814be3200SRob Clark #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
109914be3200SRob Clark #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
110014be3200SRob Clark
110114be3200SRob Clark #define REG_MDP4_DSI 0x000e0000
110214be3200SRob Clark
110314be3200SRob Clark #define REG_MDP4_DSI_ENABLE 0x000e0000
110414be3200SRob Clark
110514be3200SRob Clark #define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
110614be3200SRob Clark #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
110714be3200SRob Clark #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)110814be3200SRob Clark static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
110914be3200SRob Clark {
111014be3200SRob Clark return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
111114be3200SRob Clark }
111214be3200SRob Clark #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
111314be3200SRob Clark #define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16
MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)111414be3200SRob Clark static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
111514be3200SRob Clark {
111614be3200SRob Clark return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
111714be3200SRob Clark }
111814be3200SRob Clark
111914be3200SRob Clark #define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
112014be3200SRob Clark
112114be3200SRob Clark #define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
112214be3200SRob Clark
112314be3200SRob Clark #define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
112414be3200SRob Clark #define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
112514be3200SRob Clark #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)112614be3200SRob Clark static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
112714be3200SRob Clark {
112814be3200SRob Clark return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
112914be3200SRob Clark }
113014be3200SRob Clark #define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
113114be3200SRob Clark #define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16
MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)113214be3200SRob Clark static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
113314be3200SRob Clark {
113414be3200SRob Clark return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
113514be3200SRob Clark }
113614be3200SRob Clark
113714be3200SRob Clark #define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
113814be3200SRob Clark
113914be3200SRob Clark #define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
114014be3200SRob Clark
114114be3200SRob Clark #define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
114214be3200SRob Clark #define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
114314be3200SRob Clark #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)114414be3200SRob Clark static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
114514be3200SRob Clark {
114614be3200SRob Clark return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
114714be3200SRob Clark }
114814be3200SRob Clark #define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
114914be3200SRob Clark #define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16
MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)115014be3200SRob Clark static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
115114be3200SRob Clark {
115214be3200SRob Clark return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
115314be3200SRob Clark }
115414be3200SRob Clark #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
115514be3200SRob Clark
115614be3200SRob Clark #define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
115714be3200SRob Clark
115814be3200SRob Clark #define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
115914be3200SRob Clark
116014be3200SRob Clark #define REG_MDP4_DSI_BORDER_CLR 0x000e0028
116114be3200SRob Clark
116214be3200SRob Clark #define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
116314be3200SRob Clark #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
116414be3200SRob Clark #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)116514be3200SRob Clark static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
116614be3200SRob Clark {
116714be3200SRob Clark return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
116814be3200SRob Clark }
116914be3200SRob Clark #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
117014be3200SRob Clark
117114be3200SRob Clark #define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
117214be3200SRob Clark
117314be3200SRob Clark #define REG_MDP4_DSI_TEST_CNTL 0x000e0034
117414be3200SRob Clark
117514be3200SRob Clark #define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
117614be3200SRob Clark #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
117714be3200SRob Clark #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
117814be3200SRob Clark #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004
117914be3200SRob Clark
118014be3200SRob Clark
118114be3200SRob Clark #endif /* MDP4_XML */
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