1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) 6 #define _DPU_TRACE_H_ 7 8 #include <linux/stringify.h> 9 #include <linux/types.h> 10 #include <linux/tracepoint.h> 11 12 #include <drm/drm_rect.h> 13 #include "dpu_crtc.h" 14 #include "dpu_encoder_phys.h" 15 #include "dpu_hw_mdss.h" 16 #include "dpu_hw_vbif.h" 17 #include "dpu_plane.h" 18 19 #undef TRACE_SYSTEM 20 #define TRACE_SYSTEM dpu 21 #undef TRACE_INCLUDE_FILE 22 #define TRACE_INCLUDE_FILE dpu_trace 23 24 TRACE_EVENT(dpu_perf_set_qos_luts, 25 TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl, 26 u32 lut, u32 lut_usage), 27 TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage), 28 TP_STRUCT__entry( 29 __field(u32, pnum) 30 __field(u32, fmt) 31 __field(bool, rt) 32 __field(u32, fl) 33 __field(u64, lut) 34 __field(u32, lut_usage) 35 ), 36 TP_fast_assign( 37 __entry->pnum = pnum; 38 __entry->fmt = fmt; 39 __entry->rt = rt; 40 __entry->fl = fl; 41 __entry->lut = lut; 42 __entry->lut_usage = lut_usage; 43 ), 44 TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d", 45 __entry->pnum, __entry->fmt, 46 __entry->rt, __entry->fl, 47 __entry->lut, __entry->lut_usage) 48 ); 49 50 TRACE_EVENT(dpu_perf_set_danger_luts, 51 TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut, 52 u32 safe_lut), 53 TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut), 54 TP_STRUCT__entry( 55 __field(u32, pnum) 56 __field(u32, fmt) 57 __field(u32, mode) 58 __field(u32, danger_lut) 59 __field(u32, safe_lut) 60 ), 61 TP_fast_assign( 62 __entry->pnum = pnum; 63 __entry->fmt = fmt; 64 __entry->mode = mode; 65 __entry->danger_lut = danger_lut; 66 __entry->safe_lut = safe_lut; 67 ), 68 TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]", 69 __entry->pnum, __entry->fmt, 70 __entry->mode, __entry->danger_lut, 71 __entry->safe_lut) 72 ); 73 74 TRACE_EVENT(dpu_perf_set_ot, 75 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx), 76 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx), 77 TP_STRUCT__entry( 78 __field(u32, pnum) 79 __field(u32, xin_id) 80 __field(u32, rd_lim) 81 __field(u32, vbif_idx) 82 ), 83 TP_fast_assign( 84 __entry->pnum = pnum; 85 __entry->xin_id = xin_id; 86 __entry->rd_lim = rd_lim; 87 __entry->vbif_idx = vbif_idx; 88 ), 89 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d", 90 __entry->pnum, __entry->xin_id, __entry->rd_lim, 91 __entry->vbif_idx) 92 ) 93 94 TRACE_EVENT(dpu_cmd_release_bw, 95 TP_PROTO(u32 crtc_id), 96 TP_ARGS(crtc_id), 97 TP_STRUCT__entry( 98 __field(u32, crtc_id) 99 ), 100 TP_fast_assign( 101 __entry->crtc_id = crtc_id; 102 ), 103 TP_printk("crtc:%d", __entry->crtc_id) 104 ); 105 106 TRACE_EVENT(tracing_mark_write, 107 TP_PROTO(int pid, const char *name, bool trace_begin), 108 TP_ARGS(pid, name, trace_begin), 109 TP_STRUCT__entry( 110 __field(int, pid) 111 __string(trace_name, name) 112 __field(bool, trace_begin) 113 ), 114 TP_fast_assign( 115 __entry->pid = pid; 116 __assign_str(trace_name, name); 117 __entry->trace_begin = trace_begin; 118 ), 119 TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E", 120 __entry->pid, __get_str(trace_name)) 121 ) 122 123 TRACE_EVENT(dpu_trace_counter, 124 TP_PROTO(int pid, char *name, int value), 125 TP_ARGS(pid, name, value), 126 TP_STRUCT__entry( 127 __field(int, pid) 128 __string(counter_name, name) 129 __field(int, value) 130 ), 131 TP_fast_assign( 132 __entry->pid = current->tgid; 133 __assign_str(counter_name, name); 134 __entry->value = value; 135 ), 136 TP_printk("%d|%s|%d", __entry->pid, 137 __get_str(counter_name), __entry->value) 138 ) 139 140 TRACE_EVENT(dpu_perf_crtc_update, 141 TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate, 142 bool stop_req, bool update_bus, bool update_clk), 143 TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk), 144 TP_STRUCT__entry( 145 __field(u32, crtc) 146 __field(u64, bw_ctl) 147 __field(u32, core_clk_rate) 148 __field(bool, stop_req) 149 __field(u32, update_bus) 150 __field(u32, update_clk) 151 ), 152 TP_fast_assign( 153 __entry->crtc = crtc; 154 __entry->bw_ctl = bw_ctl; 155 __entry->core_clk_rate = core_clk_rate; 156 __entry->stop_req = stop_req; 157 __entry->update_bus = update_bus; 158 __entry->update_clk = update_clk; 159 ), 160 TP_printk( 161 "crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d", 162 __entry->crtc, 163 __entry->bw_ctl, 164 __entry->core_clk_rate, 165 __entry->stop_req, 166 __entry->update_bus, 167 __entry->update_clk) 168 ); 169 170 DECLARE_EVENT_CLASS(dpu_enc_irq_template, 171 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, 172 int irq_idx), 173 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx), 174 TP_STRUCT__entry( 175 __field( uint32_t, drm_id ) 176 __field( enum dpu_intr_idx, intr_idx ) 177 __field( int, hw_idx ) 178 __field( int, irq_idx ) 179 ), 180 TP_fast_assign( 181 __entry->drm_id = drm_id; 182 __entry->intr_idx = intr_idx; 183 __entry->hw_idx = hw_idx; 184 __entry->irq_idx = irq_idx; 185 ), 186 TP_printk("id=%u, intr=%d, hw=%d, irq=%d", 187 __entry->drm_id, __entry->intr_idx, __entry->hw_idx, 188 __entry->irq_idx) 189 ); 190 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success, 191 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, 192 int irq_idx), 193 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx) 194 ); 195 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success, 196 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, 197 int irq_idx), 198 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx) 199 ); 200 201 TRACE_EVENT(dpu_enc_irq_wait_success, 202 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, 203 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt), 204 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt), 205 TP_STRUCT__entry( 206 __field( uint32_t, drm_id ) 207 __field( enum dpu_intr_idx, intr_idx ) 208 __field( int, hw_idx ) 209 __field( int, irq_idx ) 210 __field( enum dpu_pingpong, pp_idx ) 211 __field( int, atomic_cnt ) 212 ), 213 TP_fast_assign( 214 __entry->drm_id = drm_id; 215 __entry->intr_idx = intr_idx; 216 __entry->hw_idx = hw_idx; 217 __entry->irq_idx = irq_idx; 218 __entry->pp_idx = pp_idx; 219 __entry->atomic_cnt = atomic_cnt; 220 ), 221 TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 222 __entry->drm_id, __entry->intr_idx, __entry->hw_idx, 223 __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt) 224 ); 225 226 DECLARE_EVENT_CLASS(dpu_drm_obj_template, 227 TP_PROTO(uint32_t drm_id), 228 TP_ARGS(drm_id), 229 TP_STRUCT__entry( 230 __field( uint32_t, drm_id ) 231 ), 232 TP_fast_assign( 233 __entry->drm_id = drm_id; 234 ), 235 TP_printk("id=%u", __entry->drm_id) 236 ); 237 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check, 238 TP_PROTO(uint32_t drm_id), 239 TP_ARGS(drm_id) 240 ); 241 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set, 242 TP_PROTO(uint32_t drm_id), 243 TP_ARGS(drm_id) 244 ); 245 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable, 246 TP_PROTO(uint32_t drm_id), 247 TP_ARGS(drm_id) 248 ); 249 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff, 250 TP_PROTO(uint32_t drm_id), 251 TP_ARGS(drm_id) 252 ); 253 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff, 254 TP_PROTO(uint32_t drm_id), 255 TP_ARGS(drm_id) 256 ); 257 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset, 258 TP_PROTO(uint32_t drm_id), 259 TP_ARGS(drm_id) 260 ); 261 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip, 262 TP_PROTO(uint32_t drm_id), 263 TP_ARGS(drm_id) 264 ); 265 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb, 266 TP_PROTO(uint32_t drm_id), 267 TP_ARGS(drm_id) 268 ); 269 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit, 270 TP_PROTO(uint32_t drm_id), 271 TP_ARGS(drm_id) 272 ); 273 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_enc_enable, 274 TP_PROTO(uint32_t drm_id), 275 TP_ARGS(drm_id) 276 ); 277 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit, 278 TP_PROTO(uint32_t drm_id), 279 TP_ARGS(drm_id) 280 ); 281 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done, 282 TP_PROTO(uint32_t drm_id), 283 TP_ARGS(drm_id) 284 ); 285 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume, 286 TP_PROTO(uint32_t drm_id), 287 TP_ARGS(drm_id) 288 ); 289 290 TRACE_EVENT(dpu_enc_enable, 291 TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay), 292 TP_ARGS(drm_id, hdisplay, vdisplay), 293 TP_STRUCT__entry( 294 __field( uint32_t, drm_id ) 295 __field( int, hdisplay ) 296 __field( int, vdisplay ) 297 ), 298 TP_fast_assign( 299 __entry->drm_id = drm_id; 300 __entry->hdisplay = hdisplay; 301 __entry->vdisplay = vdisplay; 302 ), 303 TP_printk("id=%u, mode=%dx%d", 304 __entry->drm_id, __entry->hdisplay, __entry->vdisplay) 305 ); 306 307 DECLARE_EVENT_CLASS(dpu_enc_keyval_template, 308 TP_PROTO(uint32_t drm_id, int val), 309 TP_ARGS(drm_id, val), 310 TP_STRUCT__entry( 311 __field( uint32_t, drm_id ) 312 __field( int, val ) 313 ), 314 TP_fast_assign( 315 __entry->drm_id = drm_id; 316 __entry->val = val; 317 ), 318 TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val) 319 ); 320 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb, 321 TP_PROTO(uint32_t drm_id, int count), 322 TP_ARGS(drm_id, count) 323 ); 324 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start, 325 TP_PROTO(uint32_t drm_id, int ctl_idx), 326 TP_ARGS(drm_id, ctl_idx) 327 ); 328 329 TRACE_EVENT(dpu_enc_atomic_check_flags, 330 TP_PROTO(uint32_t drm_id, unsigned int flags), 331 TP_ARGS(drm_id, flags), 332 TP_STRUCT__entry( 333 __field( uint32_t, drm_id ) 334 __field( unsigned int, flags ) 335 ), 336 TP_fast_assign( 337 __entry->drm_id = drm_id; 338 __entry->flags = flags; 339 ), 340 TP_printk("id=%u, flags=%u", 341 __entry->drm_id, __entry->flags) 342 ); 343 344 DECLARE_EVENT_CLASS(dpu_enc_id_enable_template, 345 TP_PROTO(uint32_t drm_id, bool enable), 346 TP_ARGS(drm_id, enable), 347 TP_STRUCT__entry( 348 __field( uint32_t, drm_id ) 349 __field( bool, enable ) 350 ), 351 TP_fast_assign( 352 __entry->drm_id = drm_id; 353 __entry->enable = enable; 354 ), 355 TP_printk("id=%u, enable=%s", 356 __entry->drm_id, __entry->enable ? "true" : "false") 357 ); 358 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper, 359 TP_PROTO(uint32_t drm_id, bool enable), 360 TP_ARGS(drm_id, enable) 361 ); 362 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb, 363 TP_PROTO(uint32_t drm_id, bool enable), 364 TP_ARGS(drm_id, enable) 365 ); 366 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb, 367 TP_PROTO(uint32_t drm_id, bool enable), 368 TP_ARGS(drm_id, enable) 369 ); 370 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te, 371 TP_PROTO(uint32_t drm_id, bool enable), 372 TP_ARGS(drm_id, enable) 373 ); 374 375 TRACE_EVENT(dpu_enc_rc, 376 TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported, 377 int rc_state, const char *stage), 378 TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage), 379 TP_STRUCT__entry( 380 __field( uint32_t, drm_id ) 381 __field( u32, sw_event ) 382 __field( bool, idle_pc_supported ) 383 __field( int, rc_state ) 384 __string( stage_str, stage ) 385 ), 386 TP_fast_assign( 387 __entry->drm_id = drm_id; 388 __entry->sw_event = sw_event; 389 __entry->idle_pc_supported = idle_pc_supported; 390 __entry->rc_state = rc_state; 391 __assign_str(stage_str, stage); 392 ), 393 TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d", 394 __get_str(stage_str), __entry->drm_id, __entry->sw_event, 395 __entry->idle_pc_supported ? "true" : "false", 396 __entry->rc_state) 397 ); 398 399 TRACE_EVENT(dpu_enc_frame_done_cb_not_busy, 400 TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx), 401 TP_ARGS(drm_id, event, intf_idx), 402 TP_STRUCT__entry( 403 __field( uint32_t, drm_id ) 404 __field( u32, event ) 405 __field( enum dpu_intf, intf_idx ) 406 ), 407 TP_fast_assign( 408 __entry->drm_id = drm_id; 409 __entry->event = event; 410 __entry->intf_idx = intf_idx; 411 ), 412 TP_printk("id=%u, event=%u, intf=%d", __entry->drm_id, __entry->event, 413 __entry->intf_idx) 414 ); 415 416 TRACE_EVENT(dpu_enc_frame_done_cb, 417 TP_PROTO(uint32_t drm_id, unsigned int idx, 418 unsigned long frame_busy_mask), 419 TP_ARGS(drm_id, idx, frame_busy_mask), 420 TP_STRUCT__entry( 421 __field( uint32_t, drm_id ) 422 __field( unsigned int, idx ) 423 __field( unsigned long, frame_busy_mask ) 424 ), 425 TP_fast_assign( 426 __entry->drm_id = drm_id; 427 __entry->idx = idx; 428 __entry->frame_busy_mask = frame_busy_mask; 429 ), 430 TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id, 431 __entry->idx, __entry->frame_busy_mask) 432 ); 433 434 TRACE_EVENT(dpu_enc_trigger_flush, 435 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, 436 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits, 437 u32 pending_flush_ret), 438 TP_ARGS(drm_id, intf_idx, pending_kickoff_cnt, ctl_idx, 439 extra_flush_bits, pending_flush_ret), 440 TP_STRUCT__entry( 441 __field( uint32_t, drm_id ) 442 __field( enum dpu_intf, intf_idx ) 443 __field( int, pending_kickoff_cnt ) 444 __field( int, ctl_idx ) 445 __field( u32, extra_flush_bits ) 446 __field( u32, pending_flush_ret ) 447 ), 448 TP_fast_assign( 449 __entry->drm_id = drm_id; 450 __entry->intf_idx = intf_idx; 451 __entry->pending_kickoff_cnt = pending_kickoff_cnt; 452 __entry->ctl_idx = ctl_idx; 453 __entry->extra_flush_bits = extra_flush_bits; 454 __entry->pending_flush_ret = pending_flush_ret; 455 ), 456 TP_printk("id=%u, intf_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d " 457 "extra_flush_bits=0x%x pending_flush_ret=0x%x", 458 __entry->drm_id, __entry->intf_idx, 459 __entry->pending_kickoff_cnt, __entry->ctl_idx, 460 __entry->extra_flush_bits, __entry->pending_flush_ret) 461 ); 462 463 DECLARE_EVENT_CLASS(dpu_enc_ktime_template, 464 TP_PROTO(uint32_t drm_id, ktime_t time), 465 TP_ARGS(drm_id, time), 466 TP_STRUCT__entry( 467 __field( uint32_t, drm_id ) 468 __field( ktime_t, time ) 469 ), 470 TP_fast_assign( 471 __entry->drm_id = drm_id; 472 __entry->time = time; 473 ), 474 TP_printk("id=%u, time=%lld", __entry->drm_id, 475 ktime_to_ms(__entry->time)) 476 ); 477 DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work, 478 TP_PROTO(uint32_t drm_id, ktime_t time), 479 TP_ARGS(drm_id, time) 480 ); 481 DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff, 482 TP_PROTO(uint32_t drm_id, ktime_t time), 483 TP_ARGS(drm_id, time) 484 ); 485 486 DECLARE_EVENT_CLASS(dpu_id_event_template, 487 TP_PROTO(uint32_t drm_id, u32 event), 488 TP_ARGS(drm_id, event), 489 TP_STRUCT__entry( 490 __field( uint32_t, drm_id ) 491 __field( u32, event ) 492 ), 493 TP_fast_assign( 494 __entry->drm_id = drm_id; 495 __entry->event = event; 496 ), 497 TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event) 498 ); 499 DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout, 500 TP_PROTO(uint32_t drm_id, u32 event), 501 TP_ARGS(drm_id, event) 502 ); 503 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb, 504 TP_PROTO(uint32_t drm_id, u32 event), 505 TP_ARGS(drm_id, event) 506 ); 507 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done, 508 TP_PROTO(uint32_t drm_id, u32 event), 509 TP_ARGS(drm_id, event) 510 ); 511 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending, 512 TP_PROTO(uint32_t drm_id, u32 event), 513 TP_ARGS(drm_id, event) 514 ); 515 516 TRACE_EVENT(dpu_enc_wait_event_timeout, 517 TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time, 518 s64 expected_time, int atomic_cnt), 519 TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt), 520 TP_STRUCT__entry( 521 __field( uint32_t, drm_id ) 522 __field( int32_t, hw_id ) 523 __field( int, rc ) 524 __field( s64, time ) 525 __field( s64, expected_time ) 526 __field( int, atomic_cnt ) 527 ), 528 TP_fast_assign( 529 __entry->drm_id = drm_id; 530 __entry->hw_id = hw_id; 531 __entry->rc = rc; 532 __entry->time = time; 533 __entry->expected_time = expected_time; 534 __entry->atomic_cnt = atomic_cnt; 535 ), 536 TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d", 537 __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time, 538 __entry->expected_time, __entry->atomic_cnt) 539 ); 540 541 TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl, 542 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable, 543 int refcnt), 544 TP_ARGS(drm_id, pp, enable, refcnt), 545 TP_STRUCT__entry( 546 __field( uint32_t, drm_id ) 547 __field( enum dpu_pingpong, pp ) 548 __field( bool, enable ) 549 __field( int, refcnt ) 550 ), 551 TP_fast_assign( 552 __entry->drm_id = drm_id; 553 __entry->pp = pp; 554 __entry->enable = enable; 555 __entry->refcnt = refcnt; 556 ), 557 TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id, 558 __entry->pp, __entry->enable ? "true" : "false", 559 __entry->refcnt) 560 ); 561 562 TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done, 563 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count, 564 u32 event), 565 TP_ARGS(drm_id, pp, new_count, event), 566 TP_STRUCT__entry( 567 __field( uint32_t, drm_id ) 568 __field( enum dpu_pingpong, pp ) 569 __field( int, new_count ) 570 __field( u32, event ) 571 ), 572 TP_fast_assign( 573 __entry->drm_id = drm_id; 574 __entry->pp = pp; 575 __entry->new_count = new_count; 576 __entry->event = event; 577 ), 578 TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id, 579 __entry->pp, __entry->new_count, __entry->event) 580 ); 581 582 TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout, 583 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count, 584 int kickoff_count, u32 event), 585 TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event), 586 TP_STRUCT__entry( 587 __field( uint32_t, drm_id ) 588 __field( enum dpu_pingpong, pp ) 589 __field( int, timeout_count ) 590 __field( int, kickoff_count ) 591 __field( u32, event ) 592 ), 593 TP_fast_assign( 594 __entry->drm_id = drm_id; 595 __entry->pp = pp; 596 __entry->timeout_count = timeout_count; 597 __entry->kickoff_count = kickoff_count; 598 __entry->event = event; 599 ), 600 TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u", 601 __entry->drm_id, __entry->pp, __entry->timeout_count, 602 __entry->kickoff_count, __entry->event) 603 ); 604 605 TRACE_EVENT(dpu_enc_phys_vid_post_kickoff, 606 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx), 607 TP_ARGS(drm_id, intf_idx), 608 TP_STRUCT__entry( 609 __field( uint32_t, drm_id ) 610 __field( enum dpu_intf, intf_idx ) 611 ), 612 TP_fast_assign( 613 __entry->drm_id = drm_id; 614 __entry->intf_idx = intf_idx; 615 ), 616 TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx) 617 ); 618 619 TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, 620 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable, 621 int refcnt), 622 TP_ARGS(drm_id, intf_idx, enable, refcnt), 623 TP_STRUCT__entry( 624 __field( uint32_t, drm_id ) 625 __field( enum dpu_intf, intf_idx ) 626 __field( bool, enable ) 627 __field( int, refcnt ) 628 ), 629 TP_fast_assign( 630 __entry->drm_id = drm_id; 631 __entry->intf_idx = intf_idx; 632 __entry->enable = enable; 633 __entry->refcnt = refcnt; 634 ), 635 TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id, 636 __entry->intf_idx, __entry->enable ? "true" : "false", 637 __entry->drm_id) 638 ); 639 640 TRACE_EVENT(dpu_crtc_setup_mixer, 641 TP_PROTO(uint32_t crtc_id, uint32_t plane_id, 642 struct drm_plane_state *state, struct dpu_plane_state *pstate, 643 uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format, 644 uint64_t modifier), 645 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp, 646 pixel_format, modifier), 647 TP_STRUCT__entry( 648 __field( uint32_t, crtc_id ) 649 __field( uint32_t, plane_id ) 650 __field( uint32_t, fb_id ) 651 __field_struct( struct drm_rect, src_rect ) 652 __field_struct( struct drm_rect, dst_rect ) 653 __field( uint32_t, stage_idx ) 654 __field( enum dpu_stage, stage ) 655 __field( enum dpu_sspp, sspp ) 656 __field( uint32_t, multirect_idx ) 657 __field( uint32_t, multirect_mode ) 658 __field( uint32_t, pixel_format ) 659 __field( uint64_t, modifier ) 660 ), 661 TP_fast_assign( 662 __entry->crtc_id = crtc_id; 663 __entry->plane_id = plane_id; 664 __entry->fb_id = state ? state->fb->base.id : 0; 665 __entry->src_rect = drm_plane_state_src(state); 666 __entry->dst_rect = drm_plane_state_dest(state); 667 __entry->stage_idx = stage_idx; 668 __entry->stage = pstate->stage; 669 __entry->sspp = sspp; 670 __entry->multirect_idx = pstate->multirect_index; 671 __entry->multirect_mode = pstate->multirect_mode; 672 __entry->pixel_format = pixel_format; 673 __entry->modifier = modifier; 674 ), 675 TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT 676 " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d " 677 "multirect_index:%d multirect_mode:%u pix_format:%u " 678 "modifier:%llu", 679 __entry->crtc_id, __entry->plane_id, __entry->fb_id, 680 DRM_RECT_FP_ARG(&__entry->src_rect), 681 DRM_RECT_ARG(&__entry->dst_rect), 682 __entry->stage_idx, __entry->stage, __entry->sspp, 683 __entry->multirect_idx, __entry->multirect_mode, 684 __entry->pixel_format, __entry->modifier) 685 ); 686 687 TRACE_EVENT(dpu_crtc_setup_lm_bounds, 688 TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds), 689 TP_ARGS(drm_id, mixer, bounds), 690 TP_STRUCT__entry( 691 __field( uint32_t, drm_id ) 692 __field( int, mixer ) 693 __field_struct( struct drm_rect, bounds ) 694 ), 695 TP_fast_assign( 696 __entry->drm_id = drm_id; 697 __entry->mixer = mixer; 698 __entry->bounds = *bounds; 699 ), 700 TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id, 701 __entry->mixer, DRM_RECT_ARG(&__entry->bounds)) 702 ); 703 704 TRACE_EVENT(dpu_crtc_vblank_enable, 705 TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable, 706 struct dpu_crtc *crtc), 707 TP_ARGS(drm_id, enc_id, enable, crtc), 708 TP_STRUCT__entry( 709 __field( uint32_t, drm_id ) 710 __field( uint32_t, enc_id ) 711 __field( bool, enable ) 712 __field( bool, enabled ) 713 ), 714 TP_fast_assign( 715 __entry->drm_id = drm_id; 716 __entry->enc_id = enc_id; 717 __entry->enable = enable; 718 __entry->enabled = crtc->enabled; 719 ), 720 TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}", 721 __entry->drm_id, __entry->enc_id, 722 __entry->enable ? "true" : "false", 723 __entry->enabled ? "true" : "false") 724 ); 725 726 DECLARE_EVENT_CLASS(dpu_crtc_enable_template, 727 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 728 TP_ARGS(drm_id, enable, crtc), 729 TP_STRUCT__entry( 730 __field( uint32_t, drm_id ) 731 __field( bool, enable ) 732 __field( bool, enabled ) 733 ), 734 TP_fast_assign( 735 __entry->drm_id = drm_id; 736 __entry->enable = enable; 737 __entry->enabled = crtc->enabled; 738 ), 739 TP_printk("id:%u enable:%s state{enabled:%s}", 740 __entry->drm_id, __entry->enable ? "true" : "false", 741 __entry->enabled ? "true" : "false") 742 ); 743 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable, 744 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 745 TP_ARGS(drm_id, enable, crtc) 746 ); 747 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable, 748 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 749 TP_ARGS(drm_id, enable, crtc) 750 ); 751 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank, 752 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 753 TP_ARGS(drm_id, enable, crtc) 754 ); 755 756 TRACE_EVENT(dpu_crtc_disable_frame_pending, 757 TP_PROTO(uint32_t drm_id, int frame_pending), 758 TP_ARGS(drm_id, frame_pending), 759 TP_STRUCT__entry( 760 __field( uint32_t, drm_id ) 761 __field( int, frame_pending ) 762 ), 763 TP_fast_assign( 764 __entry->drm_id = drm_id; 765 __entry->frame_pending = frame_pending; 766 ), 767 TP_printk("id:%u frame_pending:%d", __entry->drm_id, 768 __entry->frame_pending) 769 ); 770 771 TRACE_EVENT(dpu_plane_set_scanout, 772 TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout, 773 enum dpu_sspp_multirect_index multirect_index), 774 TP_ARGS(index, layout, multirect_index), 775 TP_STRUCT__entry( 776 __field( enum dpu_sspp, index ) 777 __field_struct( struct dpu_hw_fmt_layout, layout ) 778 __field( enum dpu_sspp_multirect_index, multirect_index) 779 ), 780 TP_fast_assign( 781 __entry->index = index; 782 __entry->layout = *layout; 783 __entry->multirect_index = multirect_index; 784 ), 785 TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} " 786 "multirect_index:%d", __entry->index, __entry->layout.width, 787 __entry->layout.height, __entry->layout.plane_addr[0], 788 __entry->layout.plane_size[0], 789 __entry->layout.plane_addr[1], 790 __entry->layout.plane_size[1], 791 __entry->layout.plane_addr[2], 792 __entry->layout.plane_size[2], 793 __entry->layout.plane_addr[3], 794 __entry->layout.plane_size[3], __entry->multirect_index) 795 ); 796 797 TRACE_EVENT(dpu_plane_disable, 798 TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode), 799 TP_ARGS(drm_id, is_virtual, multirect_mode), 800 TP_STRUCT__entry( 801 __field( uint32_t, drm_id ) 802 __field( bool, is_virtual ) 803 __field( uint32_t, multirect_mode ) 804 ), 805 TP_fast_assign( 806 __entry->drm_id = drm_id; 807 __entry->is_virtual = is_virtual; 808 __entry->multirect_mode = multirect_mode; 809 ), 810 TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id, 811 __entry->is_virtual ? "true" : "false", 812 __entry->multirect_mode) 813 ); 814 815 DECLARE_EVENT_CLASS(dpu_rm_iter_template, 816 TP_PROTO(uint32_t id, uint32_t enc_id), 817 TP_ARGS(id, enc_id), 818 TP_STRUCT__entry( 819 __field( uint32_t, id ) 820 __field( uint32_t, enc_id ) 821 ), 822 TP_fast_assign( 823 __entry->id = id; 824 __entry->enc_id = enc_id; 825 ), 826 TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id) 827 ); 828 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf, 829 TP_PROTO(uint32_t id, uint32_t enc_id), 830 TP_ARGS(id, enc_id) 831 ); 832 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls, 833 TP_PROTO(uint32_t id, uint32_t enc_id), 834 TP_ARGS(id, enc_id) 835 ); 836 837 TRACE_EVENT(dpu_rm_reserve_lms, 838 TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id), 839 TP_ARGS(id, enc_id, pp_id), 840 TP_STRUCT__entry( 841 __field( uint32_t, id ) 842 __field( uint32_t, enc_id ) 843 __field( uint32_t, pp_id ) 844 ), 845 TP_fast_assign( 846 __entry->id = id; 847 __entry->enc_id = enc_id; 848 __entry->pp_id = pp_id; 849 ), 850 TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id, 851 __entry->enc_id, __entry->pp_id) 852 ); 853 854 TRACE_EVENT(dpu_vbif_wait_xin_halt_fail, 855 TP_PROTO(enum dpu_vbif index, u32 xin_id), 856 TP_ARGS(index, xin_id), 857 TP_STRUCT__entry( 858 __field( enum dpu_vbif, index ) 859 __field( u32, xin_id ) 860 ), 861 TP_fast_assign( 862 __entry->index = index; 863 __entry->xin_id = xin_id; 864 ), 865 TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id) 866 ); 867 868 TRACE_EVENT(dpu_pp_connect_ext_te, 869 TP_PROTO(enum dpu_pingpong pp, u32 cfg), 870 TP_ARGS(pp, cfg), 871 TP_STRUCT__entry( 872 __field( enum dpu_pingpong, pp ) 873 __field( u32, cfg ) 874 ), 875 TP_fast_assign( 876 __entry->pp = pp; 877 __entry->cfg = cfg; 878 ), 879 TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg) 880 ); 881 882 DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template, 883 TP_PROTO(int irq_idx, int enable_count), 884 TP_ARGS(irq_idx, enable_count), 885 TP_STRUCT__entry( 886 __field( int, irq_idx ) 887 __field( int, enable_count ) 888 ), 889 TP_fast_assign( 890 __entry->irq_idx = irq_idx; 891 __entry->enable_count = enable_count; 892 ), 893 TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx, 894 __entry->enable_count) 895 ); 896 DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx, 897 TP_PROTO(int irq_idx, int enable_count), 898 TP_ARGS(irq_idx, enable_count) 899 ); 900 DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx, 901 TP_PROTO(int irq_idx, int enable_count), 902 TP_ARGS(irq_idx, enable_count) 903 ); 904 905 DECLARE_EVENT_CLASS(dpu_core_irq_callback_template, 906 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 907 TP_ARGS(irq_idx, callback), 908 TP_STRUCT__entry( 909 __field( int, irq_idx ) 910 __field( struct dpu_irq_callback *, callback) 911 ), 912 TP_fast_assign( 913 __entry->irq_idx = irq_idx; 914 __entry->callback = callback; 915 ), 916 TP_printk("irq_idx:%d callback:%pK", __entry->irq_idx, 917 __entry->callback) 918 ); 919 DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_register_callback, 920 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 921 TP_ARGS(irq_idx, callback) 922 ); 923 DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_unregister_callback, 924 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 925 TP_ARGS(irq_idx, callback) 926 ); 927 928 TRACE_EVENT(dpu_core_perf_update_clk, 929 TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate), 930 TP_ARGS(dev, stop_req, clk_rate), 931 TP_STRUCT__entry( 932 __string( dev_name, dev->unique ) 933 __field( bool, stop_req ) 934 __field( u64, clk_rate ) 935 ), 936 TP_fast_assign( 937 __assign_str(dev_name, dev->unique); 938 __entry->stop_req = stop_req; 939 __entry->clk_rate = clk_rate; 940 ), 941 TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name), 942 __entry->stop_req ? "true" : "false", __entry->clk_rate) 943 ); 944 945 TRACE_EVENT(dpu_hw_ctl_update_pending_flush, 946 TP_PROTO(u32 new_bits, u32 pending_mask), 947 TP_ARGS(new_bits, pending_mask), 948 TP_STRUCT__entry( 949 __field( u32, new_bits ) 950 __field( u32, pending_mask ) 951 ), 952 TP_fast_assign( 953 __entry->new_bits = new_bits; 954 __entry->pending_mask = pending_mask; 955 ), 956 TP_printk("new=%x existing=%x", __entry->new_bits, 957 __entry->pending_mask) 958 ); 959 960 DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template, 961 TP_PROTO(u32 pending_mask, u32 ctl_flush), 962 TP_ARGS(pending_mask, ctl_flush), 963 TP_STRUCT__entry( 964 __field( u32, pending_mask ) 965 __field( u32, ctl_flush ) 966 ), 967 TP_fast_assign( 968 __entry->pending_mask = pending_mask; 969 __entry->ctl_flush = ctl_flush; 970 ), 971 TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask, 972 __entry->ctl_flush) 973 ); 974 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush, 975 TP_PROTO(u32 pending_mask, u32 ctl_flush), 976 TP_ARGS(pending_mask, ctl_flush) 977 ); 978 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, 979 dpu_hw_ctl_trigger_pending_flush, 980 TP_PROTO(u32 pending_mask, u32 ctl_flush), 981 TP_ARGS(pending_mask, ctl_flush) 982 ); 983 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare, 984 TP_PROTO(u32 pending_mask, u32 ctl_flush), 985 TP_ARGS(pending_mask, ctl_flush) 986 ); 987 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start, 988 TP_PROTO(u32 pending_mask, u32 ctl_flush), 989 TP_ARGS(pending_mask, ctl_flush) 990 ); 991 992 #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0) 993 #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1) 994 #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__) 995 996 #define DPU_ATRACE_INT(name, value) \ 997 trace_dpu_trace_counter(current->tgid, name, value) 998 999 #endif /* _DPU_TRACE_H_ */ 1000 1001 /* This part must be outside protection */ 1002 #undef TRACE_INCLUDE_PATH 1003 #define TRACE_INCLUDE_PATH . 1004 #include <trace/define_trace.h> 1005