1 /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) 14 #define _DPU_TRACE_H_ 15 16 #include <linux/stringify.h> 17 #include <linux/types.h> 18 #include <linux/tracepoint.h> 19 20 #include <drm/drm_rect.h> 21 #include "dpu_crtc.h" 22 #include "dpu_encoder_phys.h" 23 #include "dpu_hw_mdss.h" 24 #include "dpu_hw_vbif.h" 25 #include "dpu_plane.h" 26 27 #undef TRACE_SYSTEM 28 #define TRACE_SYSTEM dpu 29 #undef TRACE_INCLUDE_FILE 30 #define TRACE_INCLUDE_FILE dpu_trace 31 32 TRACE_EVENT(dpu_perf_set_qos_luts, 33 TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl, 34 u32 lut, u32 lut_usage), 35 TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage), 36 TP_STRUCT__entry( 37 __field(u32, pnum) 38 __field(u32, fmt) 39 __field(bool, rt) 40 __field(u32, fl) 41 __field(u64, lut) 42 __field(u32, lut_usage) 43 ), 44 TP_fast_assign( 45 __entry->pnum = pnum; 46 __entry->fmt = fmt; 47 __entry->rt = rt; 48 __entry->fl = fl; 49 __entry->lut = lut; 50 __entry->lut_usage = lut_usage; 51 ), 52 TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d", 53 __entry->pnum, __entry->fmt, 54 __entry->rt, __entry->fl, 55 __entry->lut, __entry->lut_usage) 56 ); 57 58 TRACE_EVENT(dpu_perf_set_danger_luts, 59 TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut, 60 u32 safe_lut), 61 TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut), 62 TP_STRUCT__entry( 63 __field(u32, pnum) 64 __field(u32, fmt) 65 __field(u32, mode) 66 __field(u32, danger_lut) 67 __field(u32, safe_lut) 68 ), 69 TP_fast_assign( 70 __entry->pnum = pnum; 71 __entry->fmt = fmt; 72 __entry->mode = mode; 73 __entry->danger_lut = danger_lut; 74 __entry->safe_lut = safe_lut; 75 ), 76 TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]", 77 __entry->pnum, __entry->fmt, 78 __entry->mode, __entry->danger_lut, 79 __entry->safe_lut) 80 ); 81 82 TRACE_EVENT(dpu_perf_set_ot, 83 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx), 84 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx), 85 TP_STRUCT__entry( 86 __field(u32, pnum) 87 __field(u32, xin_id) 88 __field(u32, rd_lim) 89 __field(u32, vbif_idx) 90 ), 91 TP_fast_assign( 92 __entry->pnum = pnum; 93 __entry->xin_id = xin_id; 94 __entry->rd_lim = rd_lim; 95 __entry->vbif_idx = vbif_idx; 96 ), 97 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d", 98 __entry->pnum, __entry->xin_id, __entry->rd_lim, 99 __entry->vbif_idx) 100 ) 101 102 TRACE_EVENT(dpu_cmd_release_bw, 103 TP_PROTO(u32 crtc_id), 104 TP_ARGS(crtc_id), 105 TP_STRUCT__entry( 106 __field(u32, crtc_id) 107 ), 108 TP_fast_assign( 109 __entry->crtc_id = crtc_id; 110 ), 111 TP_printk("crtc:%d", __entry->crtc_id) 112 ); 113 114 TRACE_EVENT(tracing_mark_write, 115 TP_PROTO(int pid, const char *name, bool trace_begin), 116 TP_ARGS(pid, name, trace_begin), 117 TP_STRUCT__entry( 118 __field(int, pid) 119 __string(trace_name, name) 120 __field(bool, trace_begin) 121 ), 122 TP_fast_assign( 123 __entry->pid = pid; 124 __assign_str(trace_name, name); 125 __entry->trace_begin = trace_begin; 126 ), 127 TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E", 128 __entry->pid, __get_str(trace_name)) 129 ) 130 131 TRACE_EVENT(dpu_trace_counter, 132 TP_PROTO(int pid, char *name, int value), 133 TP_ARGS(pid, name, value), 134 TP_STRUCT__entry( 135 __field(int, pid) 136 __string(counter_name, name) 137 __field(int, value) 138 ), 139 TP_fast_assign( 140 __entry->pid = current->tgid; 141 __assign_str(counter_name, name); 142 __entry->value = value; 143 ), 144 TP_printk("%d|%s|%d", __entry->pid, 145 __get_str(counter_name), __entry->value) 146 ) 147 148 TRACE_EVENT(dpu_perf_crtc_update, 149 TP_PROTO(u32 crtc, u64 bw_ctl_mnoc, u64 bw_ctl_llcc, 150 u64 bw_ctl_ebi, u32 core_clk_rate, 151 bool stop_req, u32 update_bus, u32 update_clk), 152 TP_ARGS(crtc, bw_ctl_mnoc, bw_ctl_llcc, bw_ctl_ebi, core_clk_rate, 153 stop_req, update_bus, update_clk), 154 TP_STRUCT__entry( 155 __field(u32, crtc) 156 __field(u64, bw_ctl_mnoc) 157 __field(u64, bw_ctl_llcc) 158 __field(u64, bw_ctl_ebi) 159 __field(u32, core_clk_rate) 160 __field(bool, stop_req) 161 __field(u32, update_bus) 162 __field(u32, update_clk) 163 ), 164 TP_fast_assign( 165 __entry->crtc = crtc; 166 __entry->bw_ctl_mnoc = bw_ctl_mnoc; 167 __entry->bw_ctl_llcc = bw_ctl_llcc; 168 __entry->bw_ctl_ebi = bw_ctl_ebi; 169 __entry->core_clk_rate = core_clk_rate; 170 __entry->stop_req = stop_req; 171 __entry->update_bus = update_bus; 172 __entry->update_clk = update_clk; 173 ), 174 TP_printk( 175 "crtc=%d bw_mnoc=%llu bw_llcc=%llu bw_ebi=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d", 176 __entry->crtc, 177 __entry->bw_ctl_mnoc, 178 __entry->bw_ctl_llcc, 179 __entry->bw_ctl_ebi, 180 __entry->core_clk_rate, 181 __entry->stop_req, 182 __entry->update_bus, 183 __entry->update_clk) 184 ); 185 186 DECLARE_EVENT_CLASS(dpu_enc_irq_template, 187 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, 188 int irq_idx), 189 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx), 190 TP_STRUCT__entry( 191 __field( uint32_t, drm_id ) 192 __field( enum dpu_intr_idx, intr_idx ) 193 __field( int, hw_idx ) 194 __field( int, irq_idx ) 195 ), 196 TP_fast_assign( 197 __entry->drm_id = drm_id; 198 __entry->intr_idx = intr_idx; 199 __entry->hw_idx = hw_idx; 200 __entry->irq_idx = irq_idx; 201 ), 202 TP_printk("id=%u, intr=%d, hw=%d, irq=%d", 203 __entry->drm_id, __entry->intr_idx, __entry->hw_idx, 204 __entry->irq_idx) 205 ); 206 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success, 207 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, 208 int irq_idx), 209 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx) 210 ); 211 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success, 212 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, 213 int irq_idx), 214 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx) 215 ); 216 217 TRACE_EVENT(dpu_enc_irq_wait_success, 218 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, 219 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt), 220 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt), 221 TP_STRUCT__entry( 222 __field( uint32_t, drm_id ) 223 __field( enum dpu_intr_idx, intr_idx ) 224 __field( int, hw_idx ) 225 __field( int, irq_idx ) 226 __field( enum dpu_pingpong, pp_idx ) 227 __field( int, atomic_cnt ) 228 ), 229 TP_fast_assign( 230 __entry->drm_id = drm_id; 231 __entry->intr_idx = intr_idx; 232 __entry->hw_idx = hw_idx; 233 __entry->irq_idx = irq_idx; 234 __entry->pp_idx = pp_idx; 235 __entry->atomic_cnt = atomic_cnt; 236 ), 237 TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 238 __entry->drm_id, __entry->intr_idx, __entry->hw_idx, 239 __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt) 240 ); 241 242 DECLARE_EVENT_CLASS(dpu_drm_obj_template, 243 TP_PROTO(uint32_t drm_id), 244 TP_ARGS(drm_id), 245 TP_STRUCT__entry( 246 __field( uint32_t, drm_id ) 247 ), 248 TP_fast_assign( 249 __entry->drm_id = drm_id; 250 ), 251 TP_printk("id=%u", __entry->drm_id) 252 ); 253 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check, 254 TP_PROTO(uint32_t drm_id), 255 TP_ARGS(drm_id) 256 ); 257 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set, 258 TP_PROTO(uint32_t drm_id), 259 TP_ARGS(drm_id) 260 ); 261 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable, 262 TP_PROTO(uint32_t drm_id), 263 TP_ARGS(drm_id) 264 ); 265 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff, 266 TP_PROTO(uint32_t drm_id), 267 TP_ARGS(drm_id) 268 ); 269 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff, 270 TP_PROTO(uint32_t drm_id), 271 TP_ARGS(drm_id) 272 ); 273 DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset, 274 TP_PROTO(uint32_t drm_id), 275 TP_ARGS(drm_id) 276 ); 277 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip, 278 TP_PROTO(uint32_t drm_id), 279 TP_ARGS(drm_id) 280 ); 281 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb, 282 TP_PROTO(uint32_t drm_id), 283 TP_ARGS(drm_id) 284 ); 285 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit, 286 TP_PROTO(uint32_t drm_id), 287 TP_ARGS(drm_id) 288 ); 289 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_enc_enable, 290 TP_PROTO(uint32_t drm_id), 291 TP_ARGS(drm_id) 292 ); 293 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit, 294 TP_PROTO(uint32_t drm_id), 295 TP_ARGS(drm_id) 296 ); 297 DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done, 298 TP_PROTO(uint32_t drm_id), 299 TP_ARGS(drm_id) 300 ); 301 DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume, 302 TP_PROTO(uint32_t drm_id), 303 TP_ARGS(drm_id) 304 ); 305 306 TRACE_EVENT(dpu_enc_enable, 307 TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay), 308 TP_ARGS(drm_id, hdisplay, vdisplay), 309 TP_STRUCT__entry( 310 __field( uint32_t, drm_id ) 311 __field( int, hdisplay ) 312 __field( int, vdisplay ) 313 ), 314 TP_fast_assign( 315 __entry->drm_id = drm_id; 316 __entry->hdisplay = hdisplay; 317 __entry->vdisplay = vdisplay; 318 ), 319 TP_printk("id=%u, mode=%dx%d", 320 __entry->drm_id, __entry->hdisplay, __entry->vdisplay) 321 ); 322 323 DECLARE_EVENT_CLASS(dpu_enc_keyval_template, 324 TP_PROTO(uint32_t drm_id, int val), 325 TP_ARGS(drm_id, val), 326 TP_STRUCT__entry( 327 __field( uint32_t, drm_id ) 328 __field( int, val ) 329 ), 330 TP_fast_assign( 331 __entry->drm_id = drm_id; 332 __entry->val = val; 333 ), 334 TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val) 335 ); 336 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb, 337 TP_PROTO(uint32_t drm_id, int count), 338 TP_ARGS(drm_id, count) 339 ); 340 DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start, 341 TP_PROTO(uint32_t drm_id, int ctl_idx), 342 TP_ARGS(drm_id, ctl_idx) 343 ); 344 345 TRACE_EVENT(dpu_enc_atomic_check_flags, 346 TP_PROTO(uint32_t drm_id, unsigned int flags, int private_flags), 347 TP_ARGS(drm_id, flags, private_flags), 348 TP_STRUCT__entry( 349 __field( uint32_t, drm_id ) 350 __field( unsigned int, flags ) 351 __field( int, private_flags ) 352 ), 353 TP_fast_assign( 354 __entry->drm_id = drm_id; 355 __entry->flags = flags; 356 __entry->private_flags = private_flags; 357 ), 358 TP_printk("id=%u, flags=%u, private_flags=%d", 359 __entry->drm_id, __entry->flags, __entry->private_flags) 360 ); 361 362 DECLARE_EVENT_CLASS(dpu_enc_id_enable_template, 363 TP_PROTO(uint32_t drm_id, bool enable), 364 TP_ARGS(drm_id, enable), 365 TP_STRUCT__entry( 366 __field( uint32_t, drm_id ) 367 __field( bool, enable ) 368 ), 369 TP_fast_assign( 370 __entry->drm_id = drm_id; 371 __entry->enable = enable; 372 ), 373 TP_printk("id=%u, enable=%s", 374 __entry->drm_id, __entry->enable ? "true" : "false") 375 ); 376 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper, 377 TP_PROTO(uint32_t drm_id, bool enable), 378 TP_ARGS(drm_id, enable) 379 ); 380 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb, 381 TP_PROTO(uint32_t drm_id, bool enable), 382 TP_ARGS(drm_id, enable) 383 ); 384 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb, 385 TP_PROTO(uint32_t drm_id, bool enable), 386 TP_ARGS(drm_id, enable) 387 ); 388 DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te, 389 TP_PROTO(uint32_t drm_id, bool enable), 390 TP_ARGS(drm_id, enable) 391 ); 392 393 TRACE_EVENT(dpu_enc_rc, 394 TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported, 395 int rc_state, const char *stage), 396 TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage), 397 TP_STRUCT__entry( 398 __field( uint32_t, drm_id ) 399 __field( u32, sw_event ) 400 __field( bool, idle_pc_supported ) 401 __field( int, rc_state ) 402 __string( stage_str, stage ) 403 ), 404 TP_fast_assign( 405 __entry->drm_id = drm_id; 406 __entry->sw_event = sw_event; 407 __entry->idle_pc_supported = idle_pc_supported; 408 __entry->rc_state = rc_state; 409 __assign_str(stage_str, stage); 410 ), 411 TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d\n", 412 __get_str(stage_str), __entry->drm_id, __entry->sw_event, 413 __entry->idle_pc_supported ? "true" : "false", 414 __entry->rc_state) 415 ); 416 417 TRACE_EVENT(dpu_enc_frame_done_cb_not_busy, 418 TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx), 419 TP_ARGS(drm_id, event, intf_idx), 420 TP_STRUCT__entry( 421 __field( uint32_t, drm_id ) 422 __field( u32, event ) 423 __field( enum dpu_intf, intf_idx ) 424 ), 425 TP_fast_assign( 426 __entry->drm_id = drm_id; 427 __entry->event = event; 428 __entry->intf_idx = intf_idx; 429 ), 430 TP_printk("id=%u, event=%u, intf=%d", __entry->drm_id, __entry->event, 431 __entry->intf_idx) 432 ); 433 434 TRACE_EVENT(dpu_enc_frame_done_cb, 435 TP_PROTO(uint32_t drm_id, unsigned int idx, 436 unsigned long frame_busy_mask), 437 TP_ARGS(drm_id, idx, frame_busy_mask), 438 TP_STRUCT__entry( 439 __field( uint32_t, drm_id ) 440 __field( unsigned int, idx ) 441 __field( unsigned long, frame_busy_mask ) 442 ), 443 TP_fast_assign( 444 __entry->drm_id = drm_id; 445 __entry->idx = idx; 446 __entry->frame_busy_mask = frame_busy_mask; 447 ), 448 TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id, 449 __entry->idx, __entry->frame_busy_mask) 450 ); 451 452 TRACE_EVENT(dpu_enc_trigger_flush, 453 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, 454 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits, 455 u32 pending_flush_ret), 456 TP_ARGS(drm_id, intf_idx, pending_kickoff_cnt, ctl_idx, 457 extra_flush_bits, pending_flush_ret), 458 TP_STRUCT__entry( 459 __field( uint32_t, drm_id ) 460 __field( enum dpu_intf, intf_idx ) 461 __field( int, pending_kickoff_cnt ) 462 __field( int, ctl_idx ) 463 __field( u32, extra_flush_bits ) 464 __field( u32, pending_flush_ret ) 465 ), 466 TP_fast_assign( 467 __entry->drm_id = drm_id; 468 __entry->intf_idx = intf_idx; 469 __entry->pending_kickoff_cnt = pending_kickoff_cnt; 470 __entry->ctl_idx = ctl_idx; 471 __entry->extra_flush_bits = extra_flush_bits; 472 __entry->pending_flush_ret = pending_flush_ret; 473 ), 474 TP_printk("id=%u, intf_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d " 475 "extra_flush_bits=0x%x pending_flush_ret=0x%x", 476 __entry->drm_id, __entry->intf_idx, 477 __entry->pending_kickoff_cnt, __entry->ctl_idx, 478 __entry->extra_flush_bits, __entry->pending_flush_ret) 479 ); 480 481 DECLARE_EVENT_CLASS(dpu_enc_ktime_template, 482 TP_PROTO(uint32_t drm_id, ktime_t time), 483 TP_ARGS(drm_id, time), 484 TP_STRUCT__entry( 485 __field( uint32_t, drm_id ) 486 __field( ktime_t, time ) 487 ), 488 TP_fast_assign( 489 __entry->drm_id = drm_id; 490 __entry->time = time; 491 ), 492 TP_printk("id=%u, time=%lld", __entry->drm_id, 493 ktime_to_ms(__entry->time)) 494 ); 495 DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work, 496 TP_PROTO(uint32_t drm_id, ktime_t time), 497 TP_ARGS(drm_id, time) 498 ); 499 DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff, 500 TP_PROTO(uint32_t drm_id, ktime_t time), 501 TP_ARGS(drm_id, time) 502 ); 503 504 DECLARE_EVENT_CLASS(dpu_id_event_template, 505 TP_PROTO(uint32_t drm_id, u32 event), 506 TP_ARGS(drm_id, event), 507 TP_STRUCT__entry( 508 __field( uint32_t, drm_id ) 509 __field( u32, event ) 510 ), 511 TP_fast_assign( 512 __entry->drm_id = drm_id; 513 __entry->event = event; 514 ), 515 TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event) 516 ); 517 DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout, 518 TP_PROTO(uint32_t drm_id, u32 event), 519 TP_ARGS(drm_id, event) 520 ); 521 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb, 522 TP_PROTO(uint32_t drm_id, u32 event), 523 TP_ARGS(drm_id, event) 524 ); 525 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done, 526 TP_PROTO(uint32_t drm_id, u32 event), 527 TP_ARGS(drm_id, event) 528 ); 529 DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending, 530 TP_PROTO(uint32_t drm_id, u32 event), 531 TP_ARGS(drm_id, event) 532 ); 533 534 TRACE_EVENT(dpu_enc_wait_event_timeout, 535 TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time, 536 s64 expected_time, int atomic_cnt), 537 TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt), 538 TP_STRUCT__entry( 539 __field( uint32_t, drm_id ) 540 __field( int32_t, hw_id ) 541 __field( int, rc ) 542 __field( s64, time ) 543 __field( s64, expected_time ) 544 __field( int, atomic_cnt ) 545 ), 546 TP_fast_assign( 547 __entry->drm_id = drm_id; 548 __entry->hw_id = hw_id; 549 __entry->rc = rc; 550 __entry->time = time; 551 __entry->expected_time = expected_time; 552 __entry->atomic_cnt = atomic_cnt; 553 ), 554 TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d", 555 __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time, 556 __entry->expected_time, __entry->atomic_cnt) 557 ); 558 559 TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl, 560 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable, 561 int refcnt), 562 TP_ARGS(drm_id, pp, enable, refcnt), 563 TP_STRUCT__entry( 564 __field( uint32_t, drm_id ) 565 __field( enum dpu_pingpong, pp ) 566 __field( bool, enable ) 567 __field( int, refcnt ) 568 ), 569 TP_fast_assign( 570 __entry->drm_id = drm_id; 571 __entry->pp = pp; 572 __entry->enable = enable; 573 __entry->refcnt = refcnt; 574 ), 575 TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id, 576 __entry->pp, __entry->enable ? "true" : "false", 577 __entry->refcnt) 578 ); 579 580 TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done, 581 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count, 582 u32 event), 583 TP_ARGS(drm_id, pp, new_count, event), 584 TP_STRUCT__entry( 585 __field( uint32_t, drm_id ) 586 __field( enum dpu_pingpong, pp ) 587 __field( int, new_count ) 588 __field( u32, event ) 589 ), 590 TP_fast_assign( 591 __entry->drm_id = drm_id; 592 __entry->pp = pp; 593 __entry->new_count = new_count; 594 __entry->event = event; 595 ), 596 TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id, 597 __entry->pp, __entry->new_count, __entry->event) 598 ); 599 600 TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout, 601 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count, 602 int kickoff_count, u32 event), 603 TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event), 604 TP_STRUCT__entry( 605 __field( uint32_t, drm_id ) 606 __field( enum dpu_pingpong, pp ) 607 __field( int, timeout_count ) 608 __field( int, kickoff_count ) 609 __field( u32, event ) 610 ), 611 TP_fast_assign( 612 __entry->drm_id = drm_id; 613 __entry->pp = pp; 614 __entry->timeout_count = timeout_count; 615 __entry->kickoff_count = kickoff_count; 616 __entry->event = event; 617 ), 618 TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u", 619 __entry->drm_id, __entry->pp, __entry->timeout_count, 620 __entry->kickoff_count, __entry->event) 621 ); 622 623 TRACE_EVENT(dpu_enc_phys_vid_post_kickoff, 624 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx), 625 TP_ARGS(drm_id, intf_idx), 626 TP_STRUCT__entry( 627 __field( uint32_t, drm_id ) 628 __field( enum dpu_intf, intf_idx ) 629 ), 630 TP_fast_assign( 631 __entry->drm_id = drm_id; 632 __entry->intf_idx = intf_idx; 633 ), 634 TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx) 635 ); 636 637 TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, 638 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable, 639 int refcnt), 640 TP_ARGS(drm_id, intf_idx, enable, refcnt), 641 TP_STRUCT__entry( 642 __field( uint32_t, drm_id ) 643 __field( enum dpu_intf, intf_idx ) 644 __field( bool, enable ) 645 __field( int, refcnt ) 646 ), 647 TP_fast_assign( 648 __entry->drm_id = drm_id; 649 __entry->intf_idx = intf_idx; 650 __entry->enable = enable; 651 __entry->refcnt = refcnt; 652 ), 653 TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id, 654 __entry->intf_idx, __entry->enable ? "true" : "false", 655 __entry->drm_id) 656 ); 657 658 TRACE_EVENT(dpu_crtc_setup_mixer, 659 TP_PROTO(uint32_t crtc_id, uint32_t plane_id, 660 struct drm_plane_state *state, struct dpu_plane_state *pstate, 661 uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format, 662 uint64_t modifier), 663 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp, 664 pixel_format, modifier), 665 TP_STRUCT__entry( 666 __field( uint32_t, crtc_id ) 667 __field( uint32_t, plane_id ) 668 __field( uint32_t, fb_id ) 669 __field_struct( struct drm_rect, src_rect ) 670 __field_struct( struct drm_rect, dst_rect ) 671 __field( uint32_t, stage_idx ) 672 __field( enum dpu_stage, stage ) 673 __field( enum dpu_sspp, sspp ) 674 __field( uint32_t, multirect_idx ) 675 __field( uint32_t, multirect_mode ) 676 __field( uint32_t, pixel_format ) 677 __field( uint64_t, modifier ) 678 ), 679 TP_fast_assign( 680 __entry->crtc_id = crtc_id; 681 __entry->plane_id = plane_id; 682 __entry->fb_id = state ? state->fb->base.id : 0; 683 __entry->src_rect = drm_plane_state_src(state); 684 __entry->dst_rect = drm_plane_state_dest(state); 685 __entry->stage_idx = stage_idx; 686 __entry->stage = pstate->stage; 687 __entry->sspp = sspp; 688 __entry->multirect_idx = pstate->multirect_index; 689 __entry->multirect_mode = pstate->multirect_mode; 690 __entry->pixel_format = pixel_format; 691 __entry->modifier = modifier; 692 ), 693 TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT 694 " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d " 695 "multirect_index:%d multirect_mode:%u pix_format:%u " 696 "modifier:%llu", 697 __entry->crtc_id, __entry->plane_id, __entry->fb_id, 698 DRM_RECT_FP_ARG(&__entry->src_rect), 699 DRM_RECT_ARG(&__entry->dst_rect), 700 __entry->stage_idx, __entry->stage, __entry->sspp, 701 __entry->multirect_idx, __entry->multirect_mode, 702 __entry->pixel_format, __entry->modifier) 703 ); 704 705 TRACE_EVENT(dpu_crtc_setup_lm_bounds, 706 TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds), 707 TP_ARGS(drm_id, mixer, bounds), 708 TP_STRUCT__entry( 709 __field( uint32_t, drm_id ) 710 __field( int, mixer ) 711 __field_struct( struct drm_rect, bounds ) 712 ), 713 TP_fast_assign( 714 __entry->drm_id = drm_id; 715 __entry->mixer = mixer; 716 __entry->bounds = *bounds; 717 ), 718 TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id, 719 __entry->mixer, DRM_RECT_ARG(&__entry->bounds)) 720 ); 721 722 TRACE_EVENT(dpu_crtc_vblank_enable, 723 TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable, 724 struct dpu_crtc *crtc), 725 TP_ARGS(drm_id, enc_id, enable, crtc), 726 TP_STRUCT__entry( 727 __field( uint32_t, drm_id ) 728 __field( uint32_t, enc_id ) 729 __field( bool, enable ) 730 __field( bool, enabled ) 731 ), 732 TP_fast_assign( 733 __entry->drm_id = drm_id; 734 __entry->enc_id = enc_id; 735 __entry->enable = enable; 736 __entry->enabled = crtc->enabled; 737 ), 738 TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}", 739 __entry->drm_id, __entry->enc_id, 740 __entry->enable ? "true" : "false", 741 __entry->enabled ? "true" : "false") 742 ); 743 744 DECLARE_EVENT_CLASS(dpu_crtc_enable_template, 745 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 746 TP_ARGS(drm_id, enable, crtc), 747 TP_STRUCT__entry( 748 __field( uint32_t, drm_id ) 749 __field( bool, enable ) 750 __field( bool, enabled ) 751 ), 752 TP_fast_assign( 753 __entry->drm_id = drm_id; 754 __entry->enable = enable; 755 __entry->enabled = crtc->enabled; 756 ), 757 TP_printk("id:%u enable:%s state{enabled:%s}", 758 __entry->drm_id, __entry->enable ? "true" : "false", 759 __entry->enabled ? "true" : "false") 760 ); 761 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable, 762 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 763 TP_ARGS(drm_id, enable, crtc) 764 ); 765 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable, 766 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 767 TP_ARGS(drm_id, enable, crtc) 768 ); 769 DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank, 770 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 771 TP_ARGS(drm_id, enable, crtc) 772 ); 773 774 TRACE_EVENT(dpu_crtc_disable_frame_pending, 775 TP_PROTO(uint32_t drm_id, int frame_pending), 776 TP_ARGS(drm_id, frame_pending), 777 TP_STRUCT__entry( 778 __field( uint32_t, drm_id ) 779 __field( int, frame_pending ) 780 ), 781 TP_fast_assign( 782 __entry->drm_id = drm_id; 783 __entry->frame_pending = frame_pending; 784 ), 785 TP_printk("id:%u frame_pending:%d", __entry->drm_id, 786 __entry->frame_pending) 787 ); 788 789 TRACE_EVENT(dpu_plane_set_scanout, 790 TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout, 791 enum dpu_sspp_multirect_index multirect_index), 792 TP_ARGS(index, layout, multirect_index), 793 TP_STRUCT__entry( 794 __field( enum dpu_sspp, index ) 795 __field_struct( struct dpu_hw_fmt_layout, layout ) 796 __field( enum dpu_sspp_multirect_index, multirect_index) 797 ), 798 TP_fast_assign( 799 __entry->index = index; 800 __entry->layout = *layout; 801 __entry->multirect_index = multirect_index; 802 ), 803 TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} " 804 "multirect_index:%d", __entry->index, __entry->layout.width, 805 __entry->layout.height, __entry->layout.plane_addr[0], 806 __entry->layout.plane_size[0], 807 __entry->layout.plane_addr[1], 808 __entry->layout.plane_size[1], 809 __entry->layout.plane_addr[2], 810 __entry->layout.plane_size[2], 811 __entry->layout.plane_addr[3], 812 __entry->layout.plane_size[3], __entry->multirect_index) 813 ); 814 815 TRACE_EVENT(dpu_plane_disable, 816 TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode), 817 TP_ARGS(drm_id, is_virtual, multirect_mode), 818 TP_STRUCT__entry( 819 __field( uint32_t, drm_id ) 820 __field( bool, is_virtual ) 821 __field( uint32_t, multirect_mode ) 822 ), 823 TP_fast_assign( 824 __entry->drm_id = drm_id; 825 __entry->is_virtual = is_virtual; 826 __entry->multirect_mode = multirect_mode; 827 ), 828 TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id, 829 __entry->is_virtual ? "true" : "false", 830 __entry->multirect_mode) 831 ); 832 833 DECLARE_EVENT_CLASS(dpu_rm_iter_template, 834 TP_PROTO(uint32_t id, uint32_t enc_id), 835 TP_ARGS(id, enc_id), 836 TP_STRUCT__entry( 837 __field( uint32_t, id ) 838 __field( uint32_t, enc_id ) 839 ), 840 TP_fast_assign( 841 __entry->id = id; 842 __entry->enc_id = enc_id; 843 ), 844 TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id) 845 ); 846 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf, 847 TP_PROTO(uint32_t id, uint32_t enc_id), 848 TP_ARGS(id, enc_id) 849 ); 850 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls, 851 TP_PROTO(uint32_t id, uint32_t enc_id), 852 TP_ARGS(id, enc_id) 853 ); 854 855 TRACE_EVENT(dpu_rm_reserve_lms, 856 TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id), 857 TP_ARGS(id, enc_id, pp_id), 858 TP_STRUCT__entry( 859 __field( uint32_t, id ) 860 __field( uint32_t, enc_id ) 861 __field( uint32_t, pp_id ) 862 ), 863 TP_fast_assign( 864 __entry->id = id; 865 __entry->enc_id = enc_id; 866 __entry->pp_id = pp_id; 867 ), 868 TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id, 869 __entry->enc_id, __entry->pp_id) 870 ); 871 872 TRACE_EVENT(dpu_vbif_wait_xin_halt_fail, 873 TP_PROTO(enum dpu_vbif index, u32 xin_id), 874 TP_ARGS(index, xin_id), 875 TP_STRUCT__entry( 876 __field( enum dpu_vbif, index ) 877 __field( u32, xin_id ) 878 ), 879 TP_fast_assign( 880 __entry->index = index; 881 __entry->xin_id = xin_id; 882 ), 883 TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id) 884 ); 885 886 TRACE_EVENT(dpu_pp_connect_ext_te, 887 TP_PROTO(enum dpu_pingpong pp, u32 cfg), 888 TP_ARGS(pp, cfg), 889 TP_STRUCT__entry( 890 __field( enum dpu_pingpong, pp ) 891 __field( u32, cfg ) 892 ), 893 TP_fast_assign( 894 __entry->pp = pp; 895 __entry->cfg = cfg; 896 ), 897 TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg) 898 ); 899 900 DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template, 901 TP_PROTO(int irq_idx, int enable_count), 902 TP_ARGS(irq_idx, enable_count), 903 TP_STRUCT__entry( 904 __field( int, irq_idx ) 905 __field( int, enable_count ) 906 ), 907 TP_fast_assign( 908 __entry->irq_idx = irq_idx; 909 __entry->enable_count = enable_count; 910 ), 911 TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx, 912 __entry->enable_count) 913 ); 914 DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx, 915 TP_PROTO(int irq_idx, int enable_count), 916 TP_ARGS(irq_idx, enable_count) 917 ); 918 DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx, 919 TP_PROTO(int irq_idx, int enable_count), 920 TP_ARGS(irq_idx, enable_count) 921 ); 922 923 DECLARE_EVENT_CLASS(dpu_core_irq_callback_template, 924 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 925 TP_ARGS(irq_idx, callback), 926 TP_STRUCT__entry( 927 __field( int, irq_idx ) 928 __field( struct dpu_irq_callback *, callback) 929 ), 930 TP_fast_assign( 931 __entry->irq_idx = irq_idx; 932 __entry->callback = callback; 933 ), 934 TP_printk("irq_idx:%d callback:%pK", __entry->irq_idx, 935 __entry->callback) 936 ); 937 DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_register_callback, 938 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 939 TP_ARGS(irq_idx, callback) 940 ); 941 DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_unregister_callback, 942 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), 943 TP_ARGS(irq_idx, callback) 944 ); 945 946 TRACE_EVENT(dpu_core_perf_update_clk, 947 TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate), 948 TP_ARGS(dev, stop_req, clk_rate), 949 TP_STRUCT__entry( 950 __string( dev_name, dev->unique ) 951 __field( bool, stop_req ) 952 __field( u64, clk_rate ) 953 ), 954 TP_fast_assign( 955 __assign_str(dev_name, dev->unique); 956 __entry->stop_req = stop_req; 957 __entry->clk_rate = clk_rate; 958 ), 959 TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name), 960 __entry->stop_req ? "true" : "false", __entry->clk_rate) 961 ); 962 963 TRACE_EVENT(dpu_hw_ctl_update_pending_flush, 964 TP_PROTO(u32 new_bits, u32 pending_mask), 965 TP_ARGS(new_bits, pending_mask), 966 TP_STRUCT__entry( 967 __field( u32, new_bits ) 968 __field( u32, pending_mask ) 969 ), 970 TP_fast_assign( 971 __entry->new_bits = new_bits; 972 __entry->pending_mask = pending_mask; 973 ), 974 TP_printk("new=%x existing=%x", __entry->new_bits, 975 __entry->pending_mask) 976 ); 977 978 DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template, 979 TP_PROTO(u32 pending_mask, u32 ctl_flush), 980 TP_ARGS(pending_mask, ctl_flush), 981 TP_STRUCT__entry( 982 __field( u32, pending_mask ) 983 __field( u32, ctl_flush ) 984 ), 985 TP_fast_assign( 986 __entry->pending_mask = pending_mask; 987 __entry->ctl_flush = ctl_flush; 988 ), 989 TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask, 990 __entry->ctl_flush) 991 ); 992 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush, 993 TP_PROTO(u32 pending_mask, u32 ctl_flush), 994 TP_ARGS(pending_mask, ctl_flush) 995 ); 996 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, 997 dpu_hw_ctl_trigger_pending_flush, 998 TP_PROTO(u32 pending_mask, u32 ctl_flush), 999 TP_ARGS(pending_mask, ctl_flush) 1000 ); 1001 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare, 1002 TP_PROTO(u32 pending_mask, u32 ctl_flush), 1003 TP_ARGS(pending_mask, ctl_flush) 1004 ); 1005 DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start, 1006 TP_PROTO(u32 pending_mask, u32 ctl_flush), 1007 TP_ARGS(pending_mask, ctl_flush) 1008 ); 1009 1010 #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0) 1011 #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1) 1012 #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__) 1013 1014 #define DPU_ATRACE_INT(name, value) \ 1015 trace_dpu_trace_counter(current->tgid, name, value) 1016 1017 #endif /* _DPU_TRACE_H_ */ 1018 1019 /* This part must be outside protection */ 1020 #undef TRACE_INCLUDE_PATH 1021 #define TRACE_INCLUDE_PATH . 1022 #include <trace/define_trace.h> 1023