197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 225fdd593SJeykumar Sankaran /* 325fdd593SJeykumar Sankaran * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 425fdd593SJeykumar Sankaran */ 525fdd593SJeykumar Sankaran 625fdd593SJeykumar Sankaran #ifndef __DPU_RM_H__ 725fdd593SJeykumar Sankaran #define __DPU_RM_H__ 825fdd593SJeykumar Sankaran 925fdd593SJeykumar Sankaran #include <linux/list.h> 1025fdd593SJeykumar Sankaran 1125fdd593SJeykumar Sankaran #include "msm_kms.h" 1225fdd593SJeykumar Sankaran #include "dpu_hw_top.h" 1325fdd593SJeykumar Sankaran 14de3916c7SDrew Davenport struct dpu_global_state; 15bb00a452SDrew Davenport 1625fdd593SJeykumar Sankaran /** 1725fdd593SJeykumar Sankaran * struct dpu_rm - DPU dynamic hardware resource manager 18bb00a452SDrew Davenport * @pingpong_blks: array of pingpong hardware resources 19bb00a452SDrew Davenport * @mixer_blks: array of layer mixer hardware resources 20bb00a452SDrew Davenport * @ctl_blks: array of ctl hardware resources 21bb00a452SDrew Davenport * @intf_blks: array of intf hardware resources 22e47616dfSKalyan Thota * @dspp_blks: array of dspp hardware resources 2325fdd593SJeykumar Sankaran * @lm_max_width: cached layer mixer maximum width 2425fdd593SJeykumar Sankaran * @rm_lock: resource manager mutex 2525fdd593SJeykumar Sankaran */ 2625fdd593SJeykumar Sankaran struct dpu_rm { 27bb00a452SDrew Davenport struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; 28bb00a452SDrew Davenport struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; 29bb00a452SDrew Davenport struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; 30bb00a452SDrew Davenport struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; 31e47616dfSKalyan Thota struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; 32bb00a452SDrew Davenport 3325fdd593SJeykumar Sankaran uint32_t lm_max_width; 3425fdd593SJeykumar Sankaran }; 3525fdd593SJeykumar Sankaran 3625fdd593SJeykumar Sankaran /** 3725fdd593SJeykumar Sankaran * dpu_rm_init - Read hardware catalog and create reservation tracking objects 3825fdd593SJeykumar Sankaran * for all HW blocks. 3925fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 4025fdd593SJeykumar Sankaran * @cat: Pointer to hardware catalog 4125fdd593SJeykumar Sankaran * @mmio: mapped register io address of MDP 4225fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 4325fdd593SJeykumar Sankaran */ 4425fdd593SJeykumar Sankaran int dpu_rm_init(struct dpu_rm *rm, 4525fdd593SJeykumar Sankaran struct dpu_mdss_cfg *cat, 463763f1a5SJeykumar Sankaran void __iomem *mmio); 4725fdd593SJeykumar Sankaran 4825fdd593SJeykumar Sankaran /** 4925fdd593SJeykumar Sankaran * dpu_rm_destroy - Free all memory allocated by dpu_rm_init 5025fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 5125fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 5225fdd593SJeykumar Sankaran */ 5325fdd593SJeykumar Sankaran int dpu_rm_destroy(struct dpu_rm *rm); 5425fdd593SJeykumar Sankaran 5525fdd593SJeykumar Sankaran /** 5625fdd593SJeykumar Sankaran * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze 5725fdd593SJeykumar Sankaran * the use connections and user requirements, specified through related 5825fdd593SJeykumar Sankaran * topology control properties, and reserve hardware blocks to that 5925fdd593SJeykumar Sankaran * display chain. 6025fdd593SJeykumar Sankaran * HW blocks can then be accessed through dpu_rm_get_* functions. 6125fdd593SJeykumar Sankaran * HW Reservations should be released via dpu_rm_release_hw. 6225fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 6325fdd593SJeykumar Sankaran * @drm_enc: DRM Encoder handle 6425fdd593SJeykumar Sankaran * @crtc_state: Proposed Atomic DRM CRTC State handle 6525fdd593SJeykumar Sankaran * @topology: Pointer to topology info for the display 6625fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 6725fdd593SJeykumar Sankaran */ 6825fdd593SJeykumar Sankaran int dpu_rm_reserve(struct dpu_rm *rm, 69de3916c7SDrew Davenport struct dpu_global_state *global_state, 7025fdd593SJeykumar Sankaran struct drm_encoder *drm_enc, 7125fdd593SJeykumar Sankaran struct drm_crtc_state *crtc_state, 72de3916c7SDrew Davenport struct msm_display_topology topology); 7325fdd593SJeykumar Sankaran 7425fdd593SJeykumar Sankaran /** 7525fdd593SJeykumar Sankaran * dpu_rm_reserve - Given the encoder for the display chain, release any 7625fdd593SJeykumar Sankaran * HW blocks previously reserved for that use case. 7725fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 7825fdd593SJeykumar Sankaran * @enc: DRM Encoder handle 7925fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 8025fdd593SJeykumar Sankaran */ 81de3916c7SDrew Davenport void dpu_rm_release(struct dpu_global_state *global_state, 82de3916c7SDrew Davenport struct drm_encoder *enc); 8325fdd593SJeykumar Sankaran 8425fdd593SJeykumar Sankaran /** 85b954fa6bSDrew Davenport * Get hw resources of the given type that are assigned to this encoder. 8625fdd593SJeykumar Sankaran */ 87de3916c7SDrew Davenport int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 88de3916c7SDrew Davenport struct dpu_global_state *global_state, uint32_t enc_id, 89b954fa6bSDrew Davenport enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); 9025fdd593SJeykumar Sankaran #endif /* __DPU_RM_H__ */ 91b954fa6bSDrew Davenport 92