197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 225fdd593SJeykumar Sankaran /* 325fdd593SJeykumar Sankaran * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 425fdd593SJeykumar Sankaran */ 525fdd593SJeykumar Sankaran 625fdd593SJeykumar Sankaran #ifndef __DPU_RM_H__ 725fdd593SJeykumar Sankaran #define __DPU_RM_H__ 825fdd593SJeykumar Sankaran 925fdd593SJeykumar Sankaran #include <linux/list.h> 1025fdd593SJeykumar Sankaran 1125fdd593SJeykumar Sankaran #include "msm_kms.h" 1225fdd593SJeykumar Sankaran #include "dpu_hw_top.h" 1325fdd593SJeykumar Sankaran 14bb00a452SDrew Davenport 1525fdd593SJeykumar Sankaran /** 1625fdd593SJeykumar Sankaran * struct dpu_rm - DPU dynamic hardware resource manager 17bb00a452SDrew Davenport * @pingpong_blks: array of pingpong hardware resources 18bb00a452SDrew Davenport * @mixer_blks: array of layer mixer hardware resources 19bb00a452SDrew Davenport * @ctl_blks: array of ctl hardware resources 20bb00a452SDrew Davenport * @intf_blks: array of intf hardware resources 21bb00a452SDrew Davenport * @pingpong_to_enc_id: mapping of pingpong hardware resources to an encoder ID 22bb00a452SDrew Davenport * @mixer_to_enc_id: mapping of mixer hardware resources to an encoder ID 23bb00a452SDrew Davenport * @ctl_to_enc_id: mapping of ctl hardware resources to an encoder ID 24bb00a452SDrew Davenport * @intf_to_enc_id: mapping of intf hardware resources to an encoder ID 2525fdd593SJeykumar Sankaran * @lm_max_width: cached layer mixer maximum width 2625fdd593SJeykumar Sankaran * @rm_lock: resource manager mutex 2725fdd593SJeykumar Sankaran */ 2825fdd593SJeykumar Sankaran struct dpu_rm { 29bb00a452SDrew Davenport struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; 30bb00a452SDrew Davenport struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; 31bb00a452SDrew Davenport struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; 32bb00a452SDrew Davenport struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; 33bb00a452SDrew Davenport 34bb00a452SDrew Davenport uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; 35bb00a452SDrew Davenport uint32_t mixer_to_enc_id[LM_MAX - LM_0]; 36bb00a452SDrew Davenport uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; 37bb00a452SDrew Davenport uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; 38bb00a452SDrew Davenport 3925fdd593SJeykumar Sankaran uint32_t lm_max_width; 4025fdd593SJeykumar Sankaran struct mutex rm_lock; 4125fdd593SJeykumar Sankaran }; 4225fdd593SJeykumar Sankaran 4325fdd593SJeykumar Sankaran /** 4425fdd593SJeykumar Sankaran * dpu_rm_init - Read hardware catalog and create reservation tracking objects 4525fdd593SJeykumar Sankaran * for all HW blocks. 4625fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 4725fdd593SJeykumar Sankaran * @cat: Pointer to hardware catalog 4825fdd593SJeykumar Sankaran * @mmio: mapped register io address of MDP 4925fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 5025fdd593SJeykumar Sankaran */ 5125fdd593SJeykumar Sankaran int dpu_rm_init(struct dpu_rm *rm, 5225fdd593SJeykumar Sankaran struct dpu_mdss_cfg *cat, 533763f1a5SJeykumar Sankaran void __iomem *mmio); 5425fdd593SJeykumar Sankaran 5525fdd593SJeykumar Sankaran /** 5625fdd593SJeykumar Sankaran * dpu_rm_destroy - Free all memory allocated by dpu_rm_init 5725fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 5825fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 5925fdd593SJeykumar Sankaran */ 6025fdd593SJeykumar Sankaran int dpu_rm_destroy(struct dpu_rm *rm); 6125fdd593SJeykumar Sankaran 6225fdd593SJeykumar Sankaran /** 6325fdd593SJeykumar Sankaran * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze 6425fdd593SJeykumar Sankaran * the use connections and user requirements, specified through related 6525fdd593SJeykumar Sankaran * topology control properties, and reserve hardware blocks to that 6625fdd593SJeykumar Sankaran * display chain. 6725fdd593SJeykumar Sankaran * HW blocks can then be accessed through dpu_rm_get_* functions. 6825fdd593SJeykumar Sankaran * HW Reservations should be released via dpu_rm_release_hw. 6925fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 7025fdd593SJeykumar Sankaran * @drm_enc: DRM Encoder handle 7125fdd593SJeykumar Sankaran * @crtc_state: Proposed Atomic DRM CRTC State handle 7225fdd593SJeykumar Sankaran * @topology: Pointer to topology info for the display 7325fdd593SJeykumar Sankaran * @test_only: Atomic-Test phase, discard results (unless property overrides) 7425fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 7525fdd593SJeykumar Sankaran */ 7625fdd593SJeykumar Sankaran int dpu_rm_reserve(struct dpu_rm *rm, 7725fdd593SJeykumar Sankaran struct drm_encoder *drm_enc, 7825fdd593SJeykumar Sankaran struct drm_crtc_state *crtc_state, 7925fdd593SJeykumar Sankaran struct msm_display_topology topology, 8025fdd593SJeykumar Sankaran bool test_only); 8125fdd593SJeykumar Sankaran 8225fdd593SJeykumar Sankaran /** 8325fdd593SJeykumar Sankaran * dpu_rm_reserve - Given the encoder for the display chain, release any 8425fdd593SJeykumar Sankaran * HW blocks previously reserved for that use case. 8525fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 8625fdd593SJeykumar Sankaran * @enc: DRM Encoder handle 8725fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 8825fdd593SJeykumar Sankaran */ 8925fdd593SJeykumar Sankaran void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc); 9025fdd593SJeykumar Sankaran 9125fdd593SJeykumar Sankaran /** 92b954fa6bSDrew Davenport * Get hw resources of the given type that are assigned to this encoder. 9325fdd593SJeykumar Sankaran */ 94b954fa6bSDrew Davenport int dpu_rm_get_assigned_resources(struct dpu_rm *rm, uint32_t enc_id, 95b954fa6bSDrew Davenport enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); 9625fdd593SJeykumar Sankaran #endif /* __DPU_RM_H__ */ 97b954fa6bSDrew Davenport 98