197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 225fdd593SJeykumar Sankaran /* 325fdd593SJeykumar Sankaran * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 425fdd593SJeykumar Sankaran */ 525fdd593SJeykumar Sankaran 625fdd593SJeykumar Sankaran #ifndef __DPU_RM_H__ 725fdd593SJeykumar Sankaran #define __DPU_RM_H__ 825fdd593SJeykumar Sankaran 925fdd593SJeykumar Sankaran #include <linux/list.h> 1025fdd593SJeykumar Sankaran 1125fdd593SJeykumar Sankaran #include "msm_kms.h" 1225fdd593SJeykumar Sankaran #include "dpu_hw_top.h" 1325fdd593SJeykumar Sankaran 14de3916c7SDrew Davenport struct dpu_global_state; 15bb00a452SDrew Davenport 1625fdd593SJeykumar Sankaran /** 1725fdd593SJeykumar Sankaran * struct dpu_rm - DPU dynamic hardware resource manager 18bb00a452SDrew Davenport * @pingpong_blks: array of pingpong hardware resources 19bb00a452SDrew Davenport * @mixer_blks: array of layer mixer hardware resources 20bb00a452SDrew Davenport * @ctl_blks: array of ctl hardware resources 21ae57fdf0SDmitry Baryshkov * @hw_intf: array of intf hardware resources 2225a29653SAbhinav Kumar * @hw_wb: array of wb hardware resources 23e47616dfSKalyan Thota * @dspp_blks: array of dspp hardware resources 24*64caf60dSDmitry Baryshkov * @hw_sspp: array of sspp hardware resources 2525fdd593SJeykumar Sankaran */ 2625fdd593SJeykumar Sankaran struct dpu_rm { 27bb00a452SDrew Davenport struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; 28bb00a452SDrew Davenport struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; 29bb00a452SDrew Davenport struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; 30ae57fdf0SDmitry Baryshkov struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0]; 3125a29653SAbhinav Kumar struct dpu_hw_wb *hw_wb[WB_MAX - WB_0]; 32e47616dfSKalyan Thota struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; 334369c93cSDmitry Baryshkov struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; 34f2803ee9SVinod Koul struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; 35*64caf60dSDmitry Baryshkov struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE]; 3625fdd593SJeykumar Sankaran }; 3725fdd593SJeykumar Sankaran 3825fdd593SJeykumar Sankaran /** 3925fdd593SJeykumar Sankaran * dpu_rm_init - Read hardware catalog and create reservation tracking objects 4025fdd593SJeykumar Sankaran * for all HW blocks. 4125fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 4225fdd593SJeykumar Sankaran * @cat: Pointer to hardware catalog 4325fdd593SJeykumar Sankaran * @mmio: mapped register io address of MDP 4425fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 4525fdd593SJeykumar Sankaran */ 4625fdd593SJeykumar Sankaran int dpu_rm_init(struct dpu_rm *rm, 4732084967SDmitry Baryshkov const struct dpu_mdss_cfg *cat, 483763f1a5SJeykumar Sankaran void __iomem *mmio); 4925fdd593SJeykumar Sankaran 5025fdd593SJeykumar Sankaran /** 5125fdd593SJeykumar Sankaran * dpu_rm_destroy - Free all memory allocated by dpu_rm_init 5225fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 5325fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 5425fdd593SJeykumar Sankaran */ 5525fdd593SJeykumar Sankaran int dpu_rm_destroy(struct dpu_rm *rm); 5625fdd593SJeykumar Sankaran 5725fdd593SJeykumar Sankaran /** 5825fdd593SJeykumar Sankaran * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze 5925fdd593SJeykumar Sankaran * the use connections and user requirements, specified through related 6025fdd593SJeykumar Sankaran * topology control properties, and reserve hardware blocks to that 6125fdd593SJeykumar Sankaran * display chain. 6225fdd593SJeykumar Sankaran * HW blocks can then be accessed through dpu_rm_get_* functions. 6325fdd593SJeykumar Sankaran * HW Reservations should be released via dpu_rm_release_hw. 6425fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 6525fdd593SJeykumar Sankaran * @drm_enc: DRM Encoder handle 6625fdd593SJeykumar Sankaran * @crtc_state: Proposed Atomic DRM CRTC State handle 6725fdd593SJeykumar Sankaran * @topology: Pointer to topology info for the display 6825fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 6925fdd593SJeykumar Sankaran */ 7025fdd593SJeykumar Sankaran int dpu_rm_reserve(struct dpu_rm *rm, 71de3916c7SDrew Davenport struct dpu_global_state *global_state, 7225fdd593SJeykumar Sankaran struct drm_encoder *drm_enc, 7325fdd593SJeykumar Sankaran struct drm_crtc_state *crtc_state, 74de3916c7SDrew Davenport struct msm_display_topology topology); 7525fdd593SJeykumar Sankaran 7625fdd593SJeykumar Sankaran /** 7725fdd593SJeykumar Sankaran * dpu_rm_reserve - Given the encoder for the display chain, release any 7825fdd593SJeykumar Sankaran * HW blocks previously reserved for that use case. 7925fdd593SJeykumar Sankaran * @rm: DPU Resource Manager handle 8025fdd593SJeykumar Sankaran * @enc: DRM Encoder handle 8125fdd593SJeykumar Sankaran * @Return: 0 on Success otherwise -ERROR 8225fdd593SJeykumar Sankaran */ 83de3916c7SDrew Davenport void dpu_rm_release(struct dpu_global_state *global_state, 84de3916c7SDrew Davenport struct drm_encoder *enc); 8525fdd593SJeykumar Sankaran 8625fdd593SJeykumar Sankaran /** 87b954fa6bSDrew Davenport * Get hw resources of the given type that are assigned to this encoder. 8825fdd593SJeykumar Sankaran */ 89de3916c7SDrew Davenport int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 90de3916c7SDrew Davenport struct dpu_global_state *global_state, uint32_t enc_id, 91b954fa6bSDrew Davenport enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); 92ef58e0adSDmitry Baryshkov 93ef58e0adSDmitry Baryshkov /** 94ef58e0adSDmitry Baryshkov * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index. 95ef58e0adSDmitry Baryshkov * @rm: DPU Resource Manager handle 96ef58e0adSDmitry Baryshkov * @intf_idx: INTF's index 97ef58e0adSDmitry Baryshkov */ 98ae57fdf0SDmitry Baryshkov static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx) 99ae57fdf0SDmitry Baryshkov { 100ae57fdf0SDmitry Baryshkov return rm->hw_intf[intf_idx - INTF_0]; 101ae57fdf0SDmitry Baryshkov } 102ef58e0adSDmitry Baryshkov 10325a29653SAbhinav Kumar /** 10425a29653SAbhinav Kumar * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index. 10525a29653SAbhinav Kumar * @rm: DPU Resource Manager handle 10625a29653SAbhinav Kumar * @wb_idx: WB index 10725a29653SAbhinav Kumar */ 10825a29653SAbhinav Kumar static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx) 10925a29653SAbhinav Kumar { 11025a29653SAbhinav Kumar return rm->hw_wb[wb_idx - WB_0]; 11125a29653SAbhinav Kumar } 11225a29653SAbhinav Kumar 113*64caf60dSDmitry Baryshkov /** 114*64caf60dSDmitry Baryshkov * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index. 115*64caf60dSDmitry Baryshkov * @rm: DPU Resource Manager handle 116*64caf60dSDmitry Baryshkov * @sspp_idx: SSPP index 117*64caf60dSDmitry Baryshkov */ 118*64caf60dSDmitry Baryshkov static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx) 119*64caf60dSDmitry Baryshkov { 120*64caf60dSDmitry Baryshkov return rm->hw_sspp[sspp_idx - SSPP_NONE]; 121*64caf60dSDmitry Baryshkov } 122*64caf60dSDmitry Baryshkov 12325fdd593SJeykumar Sankaran #endif /* __DPU_RM_H__ */ 124b954fa6bSDrew Davenport 125