1 /* 2 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef _DPU_PLANE_H_ 20 #define _DPU_PLANE_H_ 21 22 #include <drm/drm_crtc.h> 23 24 #include "dpu_kms.h" 25 #include "dpu_hw_mdss.h" 26 #include "dpu_hw_sspp.h" 27 28 /** 29 * struct dpu_plane_state: Define dpu extension of drm plane state object 30 * @base: base drm plane state object 31 * @property_state: Local storage for msm_prop properties 32 * @property_values: cached plane property values 33 * @aspace: pointer to address space for input/output buffers 34 * @input_fence: dereferenced input fence pointer 35 * @stage: assigned by crtc blender 36 * @multirect_index: index of the rectangle of SSPP 37 * @multirect_mode: parallel or time multiplex multirect mode 38 * @pending: whether the current update is still pending 39 * @scaler3_cfg: configuration data for scaler3 40 * @pixel_ext: configuration data for pixel extensions 41 * @scaler_check_state: indicates status of user provided pixel extension data 42 * @cdp_cfg: CDP configuration 43 */ 44 struct dpu_plane_state { 45 struct drm_plane_state base; 46 struct msm_gem_address_space *aspace; 47 void *input_fence; 48 enum dpu_stage stage; 49 uint32_t multirect_index; 50 uint32_t multirect_mode; 51 bool pending; 52 53 /* scaler configuration */ 54 struct dpu_hw_scaler3_cfg scaler3_cfg; 55 struct dpu_hw_pixel_ext pixel_ext; 56 57 struct dpu_hw_pipe_cdp_cfg cdp_cfg; 58 }; 59 60 /** 61 * struct dpu_multirect_plane_states: Defines multirect pair of drm plane states 62 * @r0: drm plane configured on rect 0 63 * @r1: drm plane configured on rect 1 64 */ 65 struct dpu_multirect_plane_states { 66 const struct drm_plane_state *r0; 67 const struct drm_plane_state *r1; 68 }; 69 70 #define to_dpu_plane_state(x) \ 71 container_of(x, struct dpu_plane_state, base) 72 73 /** 74 * dpu_plane_pipe - return sspp identifier for the given plane 75 * @plane: Pointer to DRM plane object 76 * Returns: sspp identifier of the given plane 77 */ 78 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane); 79 80 /** 81 * is_dpu_plane_virtual - check for virtual plane 82 * @plane: Pointer to DRM plane object 83 * returns: true - if the plane is virtual 84 * false - if the plane is primary 85 */ 86 bool is_dpu_plane_virtual(struct drm_plane *plane); 87 88 /** 89 * dpu_plane_get_ctl_flush - get control flush mask 90 * @plane: Pointer to DRM plane object 91 * @ctl: Pointer to control hardware 92 * @flush_sspp: Pointer to sspp flush control word 93 */ 94 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, 95 u32 *flush_sspp); 96 97 /** 98 * dpu_plane_restore - restore hw state if previously power collapsed 99 * @plane: Pointer to drm plane structure 100 */ 101 void dpu_plane_restore(struct drm_plane *plane); 102 103 /** 104 * dpu_plane_flush - final plane operations before commit flush 105 * @plane: Pointer to drm plane structure 106 */ 107 void dpu_plane_flush(struct drm_plane *plane); 108 109 /** 110 * dpu_plane_kickoff - final plane operations before commit kickoff 111 * @plane: Pointer to drm plane structure 112 */ 113 void dpu_plane_kickoff(struct drm_plane *plane); 114 115 /** 116 * dpu_plane_set_error: enable/disable error condition 117 * @plane: pointer to drm_plane structure 118 */ 119 void dpu_plane_set_error(struct drm_plane *plane, bool error); 120 121 /** 122 * dpu_plane_init - create new dpu plane for the given pipe 123 * @dev: Pointer to DRM device 124 * @pipe: dpu hardware pipe identifier 125 * @type: Plane type - PRIMARY/OVERLAY/CURSOR 126 * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 127 * @master_plane_id: primary plane id of a multirect pipe. 0 value passed for 128 * a regular plane initialization. A non-zero primary plane 129 * id will be passed for a virtual pipe initialization. 130 * 131 */ 132 struct drm_plane *dpu_plane_init(struct drm_device *dev, 133 uint32_t pipe, enum drm_plane_type type, 134 unsigned long possible_crtcs, u32 master_plane_id); 135 136 /** 137 * dpu_plane_validate_multirecti_v2 - validate the multirect planes 138 * against hw limitations 139 * @plane: drm plate states of the multirect pair 140 */ 141 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane); 142 143 /** 144 * dpu_plane_clear_multirect - clear multirect bits for the given pipe 145 * @drm_state: Pointer to DRM plane state 146 */ 147 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state); 148 149 /** 150 * dpu_plane_wait_input_fence - wait for input fence object 151 * @plane: Pointer to DRM plane object 152 * @wait_ms: Wait timeout value 153 * Returns: Zero on success 154 */ 155 int dpu_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms); 156 157 /** 158 * dpu_plane_color_fill - enables color fill on plane 159 * @plane: Pointer to DRM plane object 160 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 161 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 162 * Returns: 0 on success 163 */ 164 int dpu_plane_color_fill(struct drm_plane *plane, 165 uint32_t color, uint32_t alpha); 166 167 /** 168 * dpu_plane_set_revalidate - sets revalidate flag which forces a full 169 * validation of the plane properties in the next atomic check 170 * @plane: Pointer to DRM plane object 171 * @enable: Boolean to set/unset the flag 172 */ 173 void dpu_plane_set_revalidate(struct drm_plane *plane, bool enable); 174 175 #endif /* _DPU_PLANE_H_ */ 176