1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include "msm_drv.h" 21 #include "dpu_kms.h" 22 #include "dpu_formats.h" 23 #include "dpu_hw_sspp.h" 24 #include "dpu_trace.h" 25 #include "dpu_crtc.h" 26 #include "dpu_vbif.h" 27 #include "dpu_plane.h" 28 29 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 30 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 31 32 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 33 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 34 35 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 36 #define PHASE_STEP_SHIFT 21 37 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 38 #define PHASE_RESIDUAL 15 39 40 #define SHARP_STRENGTH_DEFAULT 32 41 #define SHARP_EDGE_THR_DEFAULT 112 42 #define SHARP_SMOOTH_THR_DEFAULT 8 43 #define SHARP_NOISE_THR_DEFAULT 2 44 45 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 46 #define DPU_ZPOS_MAX 255 47 48 /* 49 * Default Preload Values 50 */ 51 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 52 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 53 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 54 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 55 56 #define DEFAULT_REFRESH_RATE 60 57 58 static const uint32_t qcom_compressed_supported_formats[] = { 59 DRM_FORMAT_ABGR8888, 60 DRM_FORMAT_ARGB8888, 61 DRM_FORMAT_XBGR8888, 62 DRM_FORMAT_XRGB8888, 63 DRM_FORMAT_ARGB2101010, 64 DRM_FORMAT_XRGB2101010, 65 DRM_FORMAT_BGR565, 66 67 DRM_FORMAT_NV12, 68 DRM_FORMAT_P010, 69 }; 70 71 /* 72 * struct dpu_plane - local dpu plane structure 73 * @aspace: address space pointer 74 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 75 * @catalog: Points to dpu catalog structure 76 * @revalidate: force revalidation of all the plane properties 77 */ 78 struct dpu_plane { 79 struct drm_plane base; 80 81 struct mutex lock; 82 83 enum dpu_sspp pipe; 84 85 uint32_t color_fill; 86 bool is_error; 87 bool is_rt_pipe; 88 const struct dpu_mdss_cfg *catalog; 89 }; 90 91 static const uint64_t supported_format_modifiers[] = { 92 DRM_FORMAT_MOD_QCOM_COMPRESSED, 93 DRM_FORMAT_MOD_LINEAR, 94 DRM_FORMAT_MOD_INVALID 95 }; 96 97 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 98 99 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 100 { 101 struct msm_drm_private *priv = plane->dev->dev_private; 102 103 return to_dpu_kms(priv->kms); 104 } 105 106 /** 107 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 108 * @catalog: Points to dpu catalog structure 109 * @fmt: Pointer to source buffer format 110 * @mode: Pointer to drm display mode 111 * @pipe_cfg: Pointer to pipe configuration 112 * Result: Updates calculated bandwidth in the plane state. 113 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 114 * Prefill BW Equation: line src bytes * line_time 115 */ 116 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, 117 const struct dpu_format *fmt, 118 const struct drm_display_mode *mode, 119 struct dpu_sw_pipe_cfg *pipe_cfg) 120 { 121 int src_width, src_height, dst_height, fps; 122 u64 plane_pixel_rate, plane_bit_rate; 123 u64 plane_prefill_bw; 124 u64 plane_bw; 125 u32 hw_latency_lines; 126 u64 scale_factor; 127 int vbp, vpw, vfp; 128 129 src_width = drm_rect_width(&pipe_cfg->src_rect); 130 src_height = drm_rect_height(&pipe_cfg->src_rect); 131 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 132 fps = drm_mode_vrefresh(mode); 133 vbp = mode->vtotal - mode->vsync_end; 134 vpw = mode->vsync_end - mode->vsync_start; 135 vfp = mode->vsync_start - mode->vdisplay; 136 hw_latency_lines = catalog->perf->min_prefill_lines; 137 scale_factor = src_height > dst_height ? 138 mult_frac(src_height, 1, dst_height) : 1; 139 140 plane_pixel_rate = src_width * mode->vtotal * fps; 141 plane_bit_rate = plane_pixel_rate * fmt->bpp; 142 143 plane_bw = plane_bit_rate * scale_factor; 144 145 plane_prefill_bw = plane_bw * hw_latency_lines; 146 147 if ((vbp+vpw) > hw_latency_lines) 148 do_div(plane_prefill_bw, (vbp+vpw)); 149 else if ((vbp+vpw+vfp) < hw_latency_lines) 150 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 151 else 152 do_div(plane_prefill_bw, hw_latency_lines); 153 154 155 return max(plane_bw, plane_prefill_bw); 156 } 157 158 /** 159 * _dpu_plane_calc_clk - calculate clock required for a plane 160 * @mode: Pointer to drm display mode 161 * @pipe_cfg: Pointer to pipe configuration 162 * Result: Updates calculated clock in the plane state. 163 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 164 */ 165 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, 166 struct dpu_sw_pipe_cfg *pipe_cfg) 167 { 168 int dst_width, src_height, dst_height, fps; 169 u64 plane_clk; 170 171 src_height = drm_rect_height(&pipe_cfg->src_rect); 172 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 173 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 174 fps = drm_mode_vrefresh(mode); 175 176 plane_clk = 177 dst_width * mode->vtotal * fps; 178 179 if (src_height > dst_height) { 180 plane_clk *= src_height; 181 do_div(plane_clk, dst_height); 182 } 183 184 return plane_clk; 185 } 186 187 /** 188 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 189 * @plane: Pointer to drm plane 190 * @pipe: Pointer to software pipe 191 * @lut_usage: LUT usecase 192 * @fmt: Pointer to source buffer format 193 * @src_width: width of source buffer 194 * Return: fill level corresponding to the source buffer/format or 0 if error 195 */ 196 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 197 struct dpu_sw_pipe *pipe, 198 enum dpu_qos_lut_usage lut_usage, 199 const struct dpu_format *fmt, u32 src_width) 200 { 201 struct dpu_plane *pdpu; 202 u32 fixed_buff_size; 203 u32 total_fl; 204 205 if (!fmt || !pipe || !src_width || !fmt->bpp) { 206 DPU_ERROR("invalid arguments\n"); 207 return 0; 208 } 209 210 if (lut_usage == DPU_QOS_LUT_USAGE_NRT) 211 return 0; 212 213 pdpu = to_dpu_plane(plane); 214 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 215 216 /* FIXME: in multirect case account for the src_width of all the planes */ 217 218 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 219 if (fmt->chroma_sample == DPU_CHROMA_420) { 220 /* NV12 */ 221 total_fl = (fixed_buff_size / 2) / 222 ((src_width + 32) * fmt->bpp); 223 } else { 224 /* non NV12 */ 225 total_fl = (fixed_buff_size / 2) * 2 / 226 ((src_width + 32) * fmt->bpp); 227 } 228 } else { 229 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 230 total_fl = (fixed_buff_size / 2) * 2 / 231 ((src_width + 32) * fmt->bpp); 232 } else { 233 total_fl = (fixed_buff_size) * 2 / 234 ((src_width + 32) * fmt->bpp); 235 } 236 } 237 238 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", 239 pipe->sspp->idx - SSPP_VIG0, 240 (char *)&fmt->base.pixel_format, 241 src_width, total_fl); 242 243 return total_fl; 244 } 245 246 /** 247 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 248 * @plane: Pointer to drm plane 249 * @pipe: Pointer to software pipe 250 * @fmt: Pointer to source buffer format 251 * @pipe_cfg: Pointer to pipe configuration 252 */ 253 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 254 struct dpu_sw_pipe *pipe, 255 const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) 256 { 257 struct dpu_plane *pdpu = to_dpu_plane(plane); 258 struct dpu_hw_qos_cfg cfg; 259 u32 total_fl, lut_usage; 260 261 if (!pdpu->is_rt_pipe) { 262 lut_usage = DPU_QOS_LUT_USAGE_NRT; 263 } else { 264 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 265 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 266 else 267 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 268 } 269 270 total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt, 271 drm_rect_width(&pipe_cfg->src_rect)); 272 273 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 274 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage]; 275 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage]; 276 277 if (pipe->sspp->idx != SSPP_CURSOR0 && 278 pipe->sspp->idx != SSPP_CURSOR1 && 279 pdpu->is_rt_pipe) 280 cfg.danger_safe_en = true; 281 282 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 283 pdpu->pipe - SSPP_VIG0, 284 cfg.danger_safe_en, 285 pdpu->is_rt_pipe); 286 287 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, 288 (fmt) ? fmt->base.pixel_format : 0, 289 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); 290 291 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 292 pdpu->pipe - SSPP_VIG0, 293 fmt ? (char *)&fmt->base.pixel_format : NULL, 294 pdpu->is_rt_pipe, total_fl, cfg.creq_lut); 295 296 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 297 (fmt) ? fmt->base.pixel_format : 0, 298 (fmt) ? fmt->fetch_mode : 0, 299 cfg.danger_lut, 300 cfg.safe_lut); 301 302 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 303 pdpu->pipe - SSPP_VIG0, 304 fmt ? (char *)&fmt->base.pixel_format : NULL, 305 fmt ? fmt->fetch_mode : -1, 306 cfg.danger_lut, 307 cfg.safe_lut); 308 309 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); 310 } 311 312 /** 313 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 314 * @plane: Pointer to drm plane 315 * @pipe: Pointer to software pipe 316 * @enable: true to enable QoS control 317 */ 318 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 319 struct dpu_sw_pipe *pipe, 320 bool enable) 321 { 322 struct dpu_plane *pdpu = to_dpu_plane(plane); 323 324 if (!pdpu->is_rt_pipe) 325 enable = false; 326 327 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 328 pdpu->pipe - SSPP_VIG0, 329 enable, 330 pdpu->is_rt_pipe); 331 332 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, 333 enable); 334 } 335 336 /** 337 * _dpu_plane_set_ot_limit - set OT limit for the given plane 338 * @plane: Pointer to drm plane 339 * @pipe: Pointer to software pipe 340 * @pipe_cfg: Pointer to pipe configuration 341 * @frame_rate: CRTC's frame rate 342 */ 343 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 344 struct dpu_sw_pipe *pipe, 345 struct dpu_sw_pipe_cfg *pipe_cfg, 346 int frame_rate) 347 { 348 struct dpu_plane *pdpu = to_dpu_plane(plane); 349 struct dpu_vbif_set_ot_params ot_params; 350 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 351 352 memset(&ot_params, 0, sizeof(ot_params)); 353 ot_params.xin_id = pipe->sspp->cap->xin_id; 354 ot_params.num = pipe->sspp->idx - SSPP_NONE; 355 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 356 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 357 ot_params.is_wfd = !pdpu->is_rt_pipe; 358 ot_params.frame_rate = frame_rate; 359 ot_params.vbif_idx = VBIF_RT; 360 ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; 361 ot_params.rd = true; 362 363 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 364 } 365 366 /** 367 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 368 * @plane: Pointer to drm plane 369 * @pipe: Pointer to software pipe 370 */ 371 static void _dpu_plane_set_qos_remap(struct drm_plane *plane, 372 struct dpu_sw_pipe *pipe) 373 { 374 struct dpu_plane *pdpu = to_dpu_plane(plane); 375 struct dpu_vbif_set_qos_params qos_params; 376 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 377 378 memset(&qos_params, 0, sizeof(qos_params)); 379 qos_params.vbif_idx = VBIF_RT; 380 qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; 381 qos_params.xin_id = pipe->sspp->cap->xin_id; 382 qos_params.num = pipe->sspp->idx - SSPP_VIG0; 383 qos_params.is_rt = pdpu->is_rt_pipe; 384 385 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 386 qos_params.num, 387 qos_params.vbif_idx, 388 qos_params.xin_id, qos_params.is_rt, 389 qos_params.clk_ctrl); 390 391 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 392 } 393 394 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, 395 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 396 struct dpu_hw_scaler3_cfg *scale_cfg, 397 const struct dpu_format *fmt, 398 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, 399 unsigned int rotation) 400 { 401 uint32_t i; 402 bool inline_rotation = rotation & DRM_MODE_ROTATE_90; 403 404 /* 405 * For inline rotation cases, scaler config is post-rotation, 406 * so swap the dimensions here. However, pixel extension will 407 * need pre-rotation settings. 408 */ 409 if (inline_rotation) 410 swap(src_w, src_h); 411 412 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 413 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 414 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 415 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 416 417 418 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 419 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 420 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 421 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 422 423 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 424 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 425 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 426 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 427 428 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 429 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 430 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 431 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 432 433 for (i = 0; i < DPU_MAX_PLANES; i++) { 434 scale_cfg->src_width[i] = src_w; 435 scale_cfg->src_height[i] = src_h; 436 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 437 scale_cfg->src_width[i] /= chroma_subsmpl_h; 438 scale_cfg->src_height[i] /= chroma_subsmpl_v; 439 } 440 441 if (pipe_hw->cap->features & 442 BIT(DPU_SSPP_SCALER_QSEED4)) { 443 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 444 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 445 } else { 446 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 447 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 448 } 449 } 450 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 451 && (src_w == dst_w)) 452 return; 453 454 scale_cfg->dst_width = dst_w; 455 scale_cfg->dst_height = dst_h; 456 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 457 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 458 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 459 scale_cfg->lut_flag = 0; 460 scale_cfg->blend_cfg = 1; 461 scale_cfg->enable = 1; 462 } 463 464 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 465 struct dpu_hw_pixel_ext *pixel_ext, 466 uint32_t src_w, uint32_t src_h, 467 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 468 { 469 int i; 470 471 for (i = 0; i < DPU_MAX_PLANES; i++) { 472 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 473 src_w /= chroma_subsmpl_h; 474 src_h /= chroma_subsmpl_v; 475 } 476 477 pixel_ext->num_ext_pxls_top[i] = src_h; 478 pixel_ext->num_ext_pxls_left[i] = src_w; 479 } 480 } 481 482 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 483 { 484 /* S15.16 format */ 485 0x00012A00, 0x00000000, 0x00019880, 486 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 487 0x00012A00, 0x00020480, 0x00000000, 488 }, 489 /* signed bias */ 490 { 0xfff0, 0xff80, 0xff80,}, 491 { 0x0, 0x0, 0x0,}, 492 /* unsigned clamp */ 493 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 494 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 495 }; 496 497 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 498 { 499 /* S15.16 format */ 500 0x00012A00, 0x00000000, 0x00019880, 501 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 502 0x00012A00, 0x00020480, 0x00000000, 503 }, 504 /* signed bias */ 505 { 0xffc0, 0xfe00, 0xfe00,}, 506 { 0x0, 0x0, 0x0,}, 507 /* unsigned clamp */ 508 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 509 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 510 }; 511 512 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, 513 const struct dpu_format *fmt) 514 { 515 const struct dpu_csc_cfg *csc_ptr; 516 517 if (!DPU_FORMAT_IS_YUV(fmt)) 518 return NULL; 519 520 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) 521 csc_ptr = &dpu_csc10_YUV2RGB_601L; 522 else 523 csc_ptr = &dpu_csc_YUV2RGB_601L; 524 525 return csc_ptr; 526 } 527 528 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 529 const struct dpu_format *fmt, bool color_fill, 530 struct dpu_sw_pipe_cfg *pipe_cfg, 531 unsigned int rotation) 532 { 533 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 534 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 535 struct dpu_hw_scaler3_cfg scaler3_cfg; 536 struct dpu_hw_pixel_ext pixel_ext; 537 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 538 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 539 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 540 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 541 542 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 543 memset(&pixel_ext, 0, sizeof(pixel_ext)); 544 545 /* don't chroma subsample if decimating */ 546 /* update scaler. calculate default config for QSEED3 */ 547 _dpu_plane_setup_scaler3(pipe_hw, 548 src_width, 549 src_height, 550 dst_width, 551 dst_height, 552 &scaler3_cfg, fmt, 553 info->hsub, info->vsub, 554 rotation); 555 556 /* configure pixel extension based on scalar config */ 557 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 558 src_width, src_height, info->hsub, info->vsub); 559 560 if (pipe_hw->ops.setup_pe) 561 pipe_hw->ops.setup_pe(pipe_hw, 562 &pixel_ext); 563 564 /** 565 * when programmed in multirect mode, scalar block will be 566 * bypassed. Still we need to update alpha and bitwidth 567 * ONLY for RECT0 568 */ 569 if (pipe_hw->ops.setup_scaler && 570 pipe->multirect_index != DPU_SSPP_RECT_1) 571 pipe_hw->ops.setup_scaler(pipe_hw, 572 &scaler3_cfg, 573 fmt); 574 } 575 576 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, 577 struct dpu_sw_pipe *pipe, 578 struct drm_rect *dst_rect, 579 u32 fill_color, 580 const struct dpu_format *fmt) 581 { 582 struct dpu_sw_pipe_cfg pipe_cfg; 583 584 /* update sspp */ 585 if (!pipe->sspp->ops.setup_solidfill) 586 return; 587 588 pipe->sspp->ops.setup_solidfill(pipe, fill_color); 589 590 /* override scaler/decimation if solid fill */ 591 pipe_cfg.dst_rect = *dst_rect; 592 593 pipe_cfg.src_rect.x1 = 0; 594 pipe_cfg.src_rect.y1 = 0; 595 pipe_cfg.src_rect.x2 = 596 drm_rect_width(&pipe_cfg.dst_rect); 597 pipe_cfg.src_rect.y2 = 598 drm_rect_height(&pipe_cfg.dst_rect); 599 600 if (pipe->sspp->ops.setup_format) 601 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); 602 603 if (pipe->sspp->ops.setup_rects) 604 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 605 606 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); 607 } 608 609 /** 610 * _dpu_plane_color_fill - enables color fill on plane 611 * @pdpu: Pointer to DPU plane object 612 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 613 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 614 */ 615 static void _dpu_plane_color_fill(struct dpu_plane *pdpu, 616 uint32_t color, uint32_t alpha) 617 { 618 const struct dpu_format *fmt; 619 const struct drm_plane *plane = &pdpu->base; 620 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 621 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); 622 623 DPU_DEBUG_PLANE(pdpu, "\n"); 624 625 /* 626 * select fill format to match user property expectation, 627 * h/w only supports RGB variants 628 */ 629 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 630 /* should not happen ever */ 631 if (!fmt) 632 return; 633 634 /* update sspp */ 635 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, 636 fill_color, fmt); 637 638 if (pstate->r_pipe.sspp) 639 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, 640 fill_color, fmt); 641 } 642 643 static int dpu_plane_prepare_fb(struct drm_plane *plane, 644 struct drm_plane_state *new_state) 645 { 646 struct drm_framebuffer *fb = new_state->fb; 647 struct dpu_plane *pdpu = to_dpu_plane(plane); 648 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 649 struct dpu_hw_fmt_layout layout; 650 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 651 int ret; 652 653 if (!new_state->fb) 654 return 0; 655 656 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 657 658 /* cache aspace */ 659 pstate->aspace = kms->base.aspace; 660 661 /* 662 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 663 * we can use msm_atomic_prepare_fb() instead of doing the 664 * implicit fence and fb prepare by hand here. 665 */ 666 drm_gem_plane_helper_prepare_fb(plane, new_state); 667 668 if (pstate->aspace) { 669 ret = msm_framebuffer_prepare(new_state->fb, 670 pstate->aspace, pstate->needs_dirtyfb); 671 if (ret) { 672 DPU_ERROR("failed to prepare framebuffer\n"); 673 return ret; 674 } 675 } 676 677 /* validate framebuffer layout before commit */ 678 ret = dpu_format_populate_layout(pstate->aspace, 679 new_state->fb, &layout); 680 if (ret) { 681 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 682 if (pstate->aspace) 683 msm_framebuffer_cleanup(new_state->fb, pstate->aspace, 684 pstate->needs_dirtyfb); 685 return ret; 686 } 687 688 return 0; 689 } 690 691 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 692 struct drm_plane_state *old_state) 693 { 694 struct dpu_plane *pdpu = to_dpu_plane(plane); 695 struct dpu_plane_state *old_pstate; 696 697 if (!old_state || !old_state->fb) 698 return; 699 700 old_pstate = to_dpu_plane_state(old_state); 701 702 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 703 704 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace, 705 old_pstate->needs_dirtyfb); 706 } 707 708 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 709 const struct dpu_sspp_sub_blks *sblk, 710 struct drm_rect src, const struct dpu_format *fmt) 711 { 712 size_t num_formats; 713 const u32 *supported_formats; 714 715 if (!sblk->rotation_cfg) { 716 DPU_ERROR("invalid rotation cfg\n"); 717 return -EINVAL; 718 } 719 720 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 721 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 722 src.y2, sblk->rotation_cfg->rot_maxheight); 723 return -EINVAL; 724 } 725 726 supported_formats = sblk->rotation_cfg->rot_format_list; 727 num_formats = sblk->rotation_cfg->rot_num_formats; 728 729 if (!DPU_FORMAT_IS_UBWC(fmt) || 730 !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats)) 731 return -EINVAL; 732 733 return 0; 734 } 735 736 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, 737 struct dpu_sw_pipe *pipe, 738 struct dpu_sw_pipe_cfg *pipe_cfg, 739 const struct dpu_format *fmt, 740 const struct drm_display_mode *mode) 741 { 742 uint32_t min_src_size; 743 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 744 745 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 746 747 if (DPU_FORMAT_IS_YUV(fmt) && 748 (!(pipe->sspp->cap->features & DPU_SSPP_SCALER) || 749 !(pipe->sspp->cap->features & DPU_SSPP_CSC_ANY))) { 750 DPU_DEBUG_PLANE(pdpu, 751 "plane doesn't have scaler/csc for yuv\n"); 752 return -EINVAL; 753 } 754 755 /* check src bounds */ 756 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || 757 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { 758 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 759 DRM_RECT_ARG(&pipe_cfg->src_rect)); 760 return -E2BIG; 761 } 762 763 /* valid yuv image */ 764 if (DPU_FORMAT_IS_YUV(fmt) && 765 (pipe_cfg->src_rect.x1 & 0x1 || 766 pipe_cfg->src_rect.y1 & 0x1 || 767 drm_rect_width(&pipe_cfg->src_rect) & 0x1 || 768 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { 769 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 770 DRM_RECT_ARG(&pipe_cfg->src_rect)); 771 return -EINVAL; 772 } 773 774 /* min dst support */ 775 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || 776 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { 777 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 778 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 779 return -EINVAL; 780 } 781 782 /* max clk check */ 783 if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { 784 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); 785 return -E2BIG; 786 } 787 788 return 0; 789 } 790 791 static int dpu_plane_atomic_check(struct drm_plane *plane, 792 struct drm_atomic_state *state) 793 { 794 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 795 plane); 796 int ret = 0, min_scale; 797 struct dpu_plane *pdpu = to_dpu_plane(plane); 798 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 799 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; 800 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 801 struct dpu_sw_pipe *pipe = &pstate->pipe; 802 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 803 const struct drm_crtc_state *crtc_state = NULL; 804 const struct dpu_format *fmt; 805 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 806 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 807 struct drm_rect fb_rect = { 0 }; 808 uint32_t max_linewidth; 809 unsigned int rotation; 810 uint32_t supported_rotations; 811 const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; 812 const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; 813 814 if (new_plane_state->crtc) 815 crtc_state = drm_atomic_get_new_crtc_state(state, 816 new_plane_state->crtc); 817 818 min_scale = FRAC_16_16(1, sblk->maxupscale); 819 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 820 min_scale, 821 sblk->maxdwnscale << 16, 822 true, true); 823 if (ret) { 824 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 825 return ret; 826 } 827 if (!new_plane_state->visible) 828 return 0; 829 830 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 831 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 832 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 833 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 834 r_pipe->sspp = NULL; 835 836 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; 837 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { 838 DPU_ERROR("> %d plane stages assigned\n", 839 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); 840 return -EINVAL; 841 } 842 843 pipe_cfg->src_rect = new_plane_state->src; 844 845 /* state->src is 16.16, src_rect is not */ 846 pipe_cfg->src_rect.x1 >>= 16; 847 pipe_cfg->src_rect.x2 >>= 16; 848 pipe_cfg->src_rect.y1 >>= 16; 849 pipe_cfg->src_rect.y2 >>= 16; 850 851 pipe_cfg->dst_rect = new_plane_state->dst; 852 853 fb_rect.x2 = new_plane_state->fb->width; 854 fb_rect.y2 = new_plane_state->fb->height; 855 856 /* Ensure fb size is supported */ 857 if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || 858 drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) { 859 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", 860 DRM_RECT_ARG(&fb_rect)); 861 return -E2BIG; 862 } 863 864 fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); 865 866 max_linewidth = pdpu->catalog->caps->max_linewidth; 867 868 drm_rect_rotate(&pipe_cfg->src_rect, 869 new_plane_state->fb->width, new_plane_state->fb->height, 870 new_plane_state->rotation); 871 872 if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || 873 _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { 874 /* 875 * In parallel multirect case only the half of the usual width 876 * is supported for tiled formats. If we are here, we know that 877 * full width is more than max_linewidth, thus each rect is 878 * wider than allowed. 879 */ 880 if (DPU_FORMAT_IS_UBWC(fmt) && 881 drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { 882 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", 883 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 884 return -E2BIG; 885 } 886 887 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 888 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 889 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 890 return -E2BIG; 891 } 892 893 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || 894 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || 895 (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && 896 !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || 897 DPU_FORMAT_IS_YUV(fmt)) { 898 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", 899 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 900 return -E2BIG; 901 } 902 903 /* 904 * Use multirect for wide plane. We do not support dynamic 905 * assignment of SSPPs, so we know the configuration. 906 */ 907 pipe->multirect_index = DPU_SSPP_RECT_0; 908 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 909 910 r_pipe->sspp = pipe->sspp; 911 r_pipe->multirect_index = DPU_SSPP_RECT_1; 912 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 913 914 *r_pipe_cfg = *pipe_cfg; 915 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 916 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 917 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 918 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 919 } 920 921 drm_rect_rotate_inv(&pipe_cfg->src_rect, 922 new_plane_state->fb->width, new_plane_state->fb->height, 923 new_plane_state->rotation); 924 if (r_pipe->sspp) 925 drm_rect_rotate_inv(&r_pipe_cfg->src_rect, 926 new_plane_state->fb->width, new_plane_state->fb->height, 927 new_plane_state->rotation); 928 929 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); 930 if (ret) 931 return ret; 932 933 if (r_pipe->sspp) { 934 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, 935 &crtc_state->adjusted_mode); 936 if (ret) 937 return ret; 938 } 939 940 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 941 942 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 943 supported_rotations |= DRM_MODE_ROTATE_90; 944 945 rotation = drm_rotation_simplify(new_plane_state->rotation, 946 supported_rotations); 947 948 if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 949 (rotation & DRM_MODE_ROTATE_90)) { 950 ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); 951 if (ret) 952 return ret; 953 } 954 955 pstate->rotation = rotation; 956 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 957 958 return 0; 959 } 960 961 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) 962 { 963 const struct dpu_format *format = 964 to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb)); 965 const struct dpu_csc_cfg *csc_ptr; 966 967 if (!pipe->sspp || !pipe->sspp->ops.setup_csc) 968 return; 969 970 csc_ptr = _dpu_plane_get_csc(pipe, format); 971 if (!csc_ptr) 972 return; 973 974 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 975 csc_ptr->csc_mv[0], 976 csc_ptr->csc_mv[1], 977 csc_ptr->csc_mv[2]); 978 979 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); 980 981 } 982 983 void dpu_plane_flush(struct drm_plane *plane) 984 { 985 struct dpu_plane *pdpu; 986 struct dpu_plane_state *pstate; 987 988 if (!plane || !plane->state) { 989 DPU_ERROR("invalid plane\n"); 990 return; 991 } 992 993 pdpu = to_dpu_plane(plane); 994 pstate = to_dpu_plane_state(plane->state); 995 996 /* 997 * These updates have to be done immediately before the plane flush 998 * timing, and may not be moved to the atomic_update/mode_set functions. 999 */ 1000 if (pdpu->is_error) 1001 /* force white frame with 100% alpha pipe output on error */ 1002 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 1003 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 1004 /* force 100% alpha */ 1005 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1006 else { 1007 dpu_plane_flush_csc(pdpu, &pstate->pipe); 1008 dpu_plane_flush_csc(pdpu, &pstate->r_pipe); 1009 } 1010 1011 /* flag h/w flush complete */ 1012 if (plane->state) 1013 pstate->pending = false; 1014 } 1015 1016 /** 1017 * dpu_plane_set_error: enable/disable error condition 1018 * @plane: pointer to drm_plane structure 1019 * @error: error value to set 1020 */ 1021 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1022 { 1023 struct dpu_plane *pdpu; 1024 1025 if (!plane) 1026 return; 1027 1028 pdpu = to_dpu_plane(plane); 1029 pdpu->is_error = error; 1030 } 1031 1032 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, 1033 struct dpu_sw_pipe *pipe, 1034 struct dpu_sw_pipe_cfg *pipe_cfg, 1035 const struct dpu_format *fmt, 1036 int frame_rate, 1037 struct dpu_hw_fmt_layout *layout) 1038 { 1039 uint32_t src_flags; 1040 struct dpu_plane *pdpu = to_dpu_plane(plane); 1041 struct drm_plane_state *state = plane->state; 1042 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1043 1044 if (layout && pipe->sspp->ops.setup_sourceaddress) { 1045 trace_dpu_plane_set_scanout(pipe, layout); 1046 pipe->sspp->ops.setup_sourceaddress(pipe, layout); 1047 } 1048 1049 /* override for color fill */ 1050 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1051 _dpu_plane_set_qos_ctrl(plane, pipe, false); 1052 1053 /* skip remaining processing on color fill */ 1054 return; 1055 } 1056 1057 if (pipe->sspp->ops.setup_rects) { 1058 pipe->sspp->ops.setup_rects(pipe, 1059 pipe_cfg); 1060 } 1061 1062 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); 1063 1064 if (pipe->sspp->ops.setup_multirect) 1065 pipe->sspp->ops.setup_multirect( 1066 pipe); 1067 1068 if (pipe->sspp->ops.setup_format) { 1069 unsigned int rotation = pstate->rotation; 1070 1071 src_flags = 0x0; 1072 1073 if (rotation & DRM_MODE_REFLECT_X) 1074 src_flags |= DPU_SSPP_FLIP_LR; 1075 1076 if (rotation & DRM_MODE_REFLECT_Y) 1077 src_flags |= DPU_SSPP_FLIP_UD; 1078 1079 if (rotation & DRM_MODE_ROTATE_90) 1080 src_flags |= DPU_SSPP_ROT_90; 1081 1082 /* update format */ 1083 pipe->sspp->ops.setup_format(pipe, fmt, src_flags); 1084 1085 if (pipe->sspp->ops.setup_cdp) { 1086 const struct dpu_perf_cfg *perf = pdpu->catalog->perf; 1087 1088 pipe->sspp->ops.setup_cdp(pipe, fmt, 1089 perf->cdp_cfg[DPU_PERF_CDP_USAGE_RT].rd_enable); 1090 } 1091 } 1092 1093 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); 1094 1095 if (pipe->sspp->idx != SSPP_CURSOR0 && 1096 pipe->sspp->idx != SSPP_CURSOR1) 1097 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); 1098 1099 if (pstate->needs_qos_remap) 1100 _dpu_plane_set_qos_remap(plane, pipe); 1101 } 1102 1103 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1104 { 1105 struct dpu_plane *pdpu = to_dpu_plane(plane); 1106 struct drm_plane_state *state = plane->state; 1107 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1108 struct dpu_sw_pipe *pipe = &pstate->pipe; 1109 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1110 struct drm_crtc *crtc = state->crtc; 1111 struct drm_framebuffer *fb = state->fb; 1112 bool is_rt_pipe; 1113 const struct dpu_format *fmt = 1114 to_dpu_format(msm_framebuffer_format(fb)); 1115 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1116 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1117 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 1118 struct msm_gem_address_space *aspace = kms->base.aspace; 1119 struct dpu_hw_fmt_layout layout; 1120 bool layout_valid = false; 1121 int ret; 1122 1123 ret = dpu_format_populate_layout(aspace, fb, &layout); 1124 if (ret) 1125 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 1126 else 1127 layout_valid = true; 1128 1129 pstate->pending = true; 1130 1131 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1132 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); 1133 pdpu->is_rt_pipe = is_rt_pipe; 1134 1135 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1136 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1137 crtc->base.id, DRM_RECT_ARG(&state->dst), 1138 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1139 1140 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1141 drm_mode_vrefresh(&crtc->mode), 1142 layout_valid ? &layout : NULL); 1143 1144 if (r_pipe->sspp) { 1145 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, 1146 drm_mode_vrefresh(&crtc->mode), 1147 layout_valid ? &layout : NULL); 1148 } 1149 1150 if (pstate->needs_qos_remap) 1151 pstate->needs_qos_remap = false; 1152 1153 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, 1154 &crtc->mode, pipe_cfg); 1155 1156 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); 1157 1158 if (r_pipe->sspp) { 1159 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); 1160 1161 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); 1162 } 1163 } 1164 1165 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1166 { 1167 struct drm_plane_state *state = plane->state; 1168 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1169 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1170 1171 trace_dpu_plane_disable(DRMID(plane), false, 1172 pstate->pipe.multirect_mode); 1173 1174 if (r_pipe->sspp) { 1175 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1176 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1177 1178 if (r_pipe->sspp->ops.setup_multirect) 1179 r_pipe->sspp->ops.setup_multirect(r_pipe); 1180 } 1181 1182 pstate->pending = true; 1183 } 1184 1185 static void dpu_plane_atomic_update(struct drm_plane *plane, 1186 struct drm_atomic_state *state) 1187 { 1188 struct dpu_plane *pdpu = to_dpu_plane(plane); 1189 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1190 plane); 1191 1192 pdpu->is_error = false; 1193 1194 DPU_DEBUG_PLANE(pdpu, "\n"); 1195 1196 if (!new_state->visible) { 1197 _dpu_plane_atomic_disable(plane); 1198 } else { 1199 dpu_plane_sspp_atomic_update(plane); 1200 } 1201 } 1202 1203 static void dpu_plane_destroy(struct drm_plane *plane) 1204 { 1205 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1206 struct dpu_plane_state *pstate; 1207 1208 DPU_DEBUG_PLANE(pdpu, "\n"); 1209 1210 if (pdpu) { 1211 pstate = to_dpu_plane_state(plane->state); 1212 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false); 1213 1214 if (pstate->r_pipe.sspp) 1215 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false); 1216 1217 mutex_destroy(&pdpu->lock); 1218 1219 /* this will destroy the states as well */ 1220 drm_plane_cleanup(plane); 1221 1222 kfree(pdpu); 1223 } 1224 } 1225 1226 static void dpu_plane_destroy_state(struct drm_plane *plane, 1227 struct drm_plane_state *state) 1228 { 1229 __drm_atomic_helper_plane_destroy_state(state); 1230 kfree(to_dpu_plane_state(state)); 1231 } 1232 1233 static struct drm_plane_state * 1234 dpu_plane_duplicate_state(struct drm_plane *plane) 1235 { 1236 struct dpu_plane *pdpu; 1237 struct dpu_plane_state *pstate; 1238 struct dpu_plane_state *old_state; 1239 1240 if (!plane) { 1241 DPU_ERROR("invalid plane\n"); 1242 return NULL; 1243 } else if (!plane->state) { 1244 DPU_ERROR("invalid plane state\n"); 1245 return NULL; 1246 } 1247 1248 old_state = to_dpu_plane_state(plane->state); 1249 pdpu = to_dpu_plane(plane); 1250 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1251 if (!pstate) { 1252 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1253 return NULL; 1254 } 1255 1256 DPU_DEBUG_PLANE(pdpu, "\n"); 1257 1258 pstate->pending = false; 1259 1260 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1261 1262 return &pstate->base; 1263 } 1264 1265 static const char * const multirect_mode_name[] = { 1266 [DPU_SSPP_MULTIRECT_NONE] = "none", 1267 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1268 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1269 }; 1270 1271 static const char * const multirect_index_name[] = { 1272 [DPU_SSPP_RECT_SOLO] = "solo", 1273 [DPU_SSPP_RECT_0] = "rect_0", 1274 [DPU_SSPP_RECT_1] = "rect_1", 1275 }; 1276 1277 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1278 { 1279 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1280 return "unknown"; 1281 1282 return multirect_mode_name[mode]; 1283 } 1284 1285 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1286 { 1287 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1288 return "unknown"; 1289 1290 return multirect_index_name[index]; 1291 } 1292 1293 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1294 const struct drm_plane_state *state) 1295 { 1296 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1297 const struct dpu_sw_pipe *pipe = &pstate->pipe; 1298 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1299 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1300 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1301 1302 drm_printf(p, "\tstage=%d\n", pstate->stage); 1303 1304 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); 1305 drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); 1306 drm_printf(p, "\tmultirect_index[0]=%s\n", 1307 dpu_get_multirect_index(pipe->multirect_index)); 1308 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 1309 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1310 1311 if (r_pipe->sspp) { 1312 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); 1313 drm_printf(p, "\tmultirect_mode[1]=%s\n", 1314 dpu_get_multirect_mode(r_pipe->multirect_mode)); 1315 drm_printf(p, "\tmultirect_index[1]=%s\n", 1316 dpu_get_multirect_index(r_pipe->multirect_index)); 1317 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); 1318 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); 1319 } 1320 } 1321 1322 static void dpu_plane_reset(struct drm_plane *plane) 1323 { 1324 struct dpu_plane *pdpu; 1325 struct dpu_plane_state *pstate; 1326 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1327 1328 if (!plane) { 1329 DPU_ERROR("invalid plane\n"); 1330 return; 1331 } 1332 1333 pdpu = to_dpu_plane(plane); 1334 DPU_DEBUG_PLANE(pdpu, "\n"); 1335 1336 /* remove previous state, if present */ 1337 if (plane->state) { 1338 dpu_plane_destroy_state(plane, plane->state); 1339 plane->state = NULL; 1340 } 1341 1342 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1343 if (!pstate) { 1344 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1345 return; 1346 } 1347 1348 /* 1349 * Set the SSPP here until we have proper virtualized DPU planes. 1350 * This is the place where the state is allocated, so fill it fully. 1351 */ 1352 pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1353 pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; 1354 pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1355 1356 pstate->r_pipe.sspp = NULL; 1357 1358 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1359 } 1360 1361 #ifdef CONFIG_DEBUG_FS 1362 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1363 { 1364 struct dpu_plane *pdpu = to_dpu_plane(plane); 1365 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 1366 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1367 1368 if (!pdpu->is_rt_pipe) 1369 return; 1370 1371 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1372 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); 1373 if (pstate->r_pipe.sspp) 1374 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); 1375 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1376 } 1377 #endif 1378 1379 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1380 uint32_t format, uint64_t modifier) 1381 { 1382 if (modifier == DRM_FORMAT_MOD_LINEAR) 1383 return true; 1384 1385 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) 1386 return dpu_find_format(format, qcom_compressed_supported_formats, 1387 ARRAY_SIZE(qcom_compressed_supported_formats)); 1388 1389 return false; 1390 } 1391 1392 static const struct drm_plane_funcs dpu_plane_funcs = { 1393 .update_plane = drm_atomic_helper_update_plane, 1394 .disable_plane = drm_atomic_helper_disable_plane, 1395 .destroy = dpu_plane_destroy, 1396 .reset = dpu_plane_reset, 1397 .atomic_duplicate_state = dpu_plane_duplicate_state, 1398 .atomic_destroy_state = dpu_plane_destroy_state, 1399 .atomic_print_state = dpu_plane_atomic_print_state, 1400 .format_mod_supported = dpu_plane_format_mod_supported, 1401 }; 1402 1403 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1404 .prepare_fb = dpu_plane_prepare_fb, 1405 .cleanup_fb = dpu_plane_cleanup_fb, 1406 .atomic_check = dpu_plane_atomic_check, 1407 .atomic_update = dpu_plane_atomic_update, 1408 }; 1409 1410 /* initialize plane */ 1411 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1412 uint32_t pipe, enum drm_plane_type type, 1413 unsigned long possible_crtcs) 1414 { 1415 struct drm_plane *plane = NULL; 1416 const uint32_t *format_list; 1417 struct dpu_plane *pdpu; 1418 struct msm_drm_private *priv = dev->dev_private; 1419 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1420 struct dpu_hw_sspp *pipe_hw; 1421 uint32_t num_formats; 1422 uint32_t supported_rotations; 1423 int ret = -EINVAL; 1424 1425 /* create and zero local structure */ 1426 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1427 if (!pdpu) { 1428 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1429 ret = -ENOMEM; 1430 return ERR_PTR(ret); 1431 } 1432 1433 /* cache local stuff for later */ 1434 plane = &pdpu->base; 1435 pdpu->pipe = pipe; 1436 1437 /* initialize underlying h/w driver */ 1438 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); 1439 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { 1440 DPU_ERROR("[%u]SSPP is invalid\n", pipe); 1441 goto clean_plane; 1442 } 1443 1444 format_list = pipe_hw->cap->sblk->format_list; 1445 num_formats = pipe_hw->cap->sblk->num_formats; 1446 1447 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1448 format_list, num_formats, 1449 supported_format_modifiers, type, NULL); 1450 if (ret) 1451 goto clean_plane; 1452 1453 pdpu->catalog = kms->catalog; 1454 1455 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); 1456 if (ret) 1457 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1458 1459 drm_plane_create_alpha_property(plane); 1460 drm_plane_create_blend_mode_property(plane, 1461 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1462 BIT(DRM_MODE_BLEND_PREMULTI) | 1463 BIT(DRM_MODE_BLEND_COVERAGE)); 1464 1465 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1466 1467 if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1468 supported_rotations |= DRM_MODE_ROTATE_MASK; 1469 1470 drm_plane_create_rotation_property(plane, 1471 DRM_MODE_ROTATE_0, supported_rotations); 1472 1473 drm_plane_enable_fb_damage_clips(plane); 1474 1475 /* success! finalize initialization */ 1476 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1477 1478 mutex_init(&pdpu->lock); 1479 1480 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1481 pipe, plane->base.id); 1482 return plane; 1483 1484 clean_plane: 1485 kfree(pdpu); 1486 return ERR_PTR(ret); 1487 } 1488