1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include "msm_drv.h" 21 #include "dpu_kms.h" 22 #include "dpu_formats.h" 23 #include "dpu_hw_sspp.h" 24 #include "dpu_trace.h" 25 #include "dpu_crtc.h" 26 #include "dpu_vbif.h" 27 #include "dpu_plane.h" 28 29 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 30 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 31 32 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 33 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 34 35 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 36 #define PHASE_STEP_SHIFT 21 37 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 38 #define PHASE_RESIDUAL 15 39 40 #define SHARP_STRENGTH_DEFAULT 32 41 #define SHARP_EDGE_THR_DEFAULT 112 42 #define SHARP_SMOOTH_THR_DEFAULT 8 43 #define SHARP_NOISE_THR_DEFAULT 2 44 45 #define DPU_NAME_SIZE 12 46 47 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 48 #define DPU_ZPOS_MAX 255 49 50 /* multirect rect index */ 51 enum { 52 R0, 53 R1, 54 R_MAX 55 }; 56 57 /* 58 * Default Preload Values 59 */ 60 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 61 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 62 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 63 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 64 65 #define DEFAULT_REFRESH_RATE 60 66 67 static const uint32_t qcom_compressed_supported_formats[] = { 68 DRM_FORMAT_ABGR8888, 69 DRM_FORMAT_ARGB8888, 70 DRM_FORMAT_XBGR8888, 71 DRM_FORMAT_XRGB8888, 72 DRM_FORMAT_XRGB2101010, 73 DRM_FORMAT_BGR565, 74 75 DRM_FORMAT_NV12, 76 DRM_FORMAT_P010, 77 }; 78 79 /** 80 * enum dpu_plane_qos - Different qos configurations for each pipe 81 * 82 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. 83 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. 84 * this configuration is mutually exclusive from VBLANK_CTRL. 85 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. 86 */ 87 enum dpu_plane_qos { 88 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), 89 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), 90 DPU_PLANE_QOS_PANIC_CTRL = BIT(2), 91 }; 92 93 /* 94 * struct dpu_plane - local dpu plane structure 95 * @aspace: address space pointer 96 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 97 * @catalog: Points to dpu catalog structure 98 * @revalidate: force revalidation of all the plane properties 99 */ 100 struct dpu_plane { 101 struct drm_plane base; 102 103 struct mutex lock; 104 105 enum dpu_sspp pipe; 106 107 struct dpu_hw_pipe *pipe_hw; 108 uint32_t color_fill; 109 bool is_error; 110 bool is_rt_pipe; 111 const struct dpu_mdss_cfg *catalog; 112 }; 113 114 static const uint64_t supported_format_modifiers[] = { 115 DRM_FORMAT_MOD_QCOM_COMPRESSED, 116 DRM_FORMAT_MOD_LINEAR, 117 DRM_FORMAT_MOD_INVALID 118 }; 119 120 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 121 122 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 123 { 124 struct msm_drm_private *priv = plane->dev->dev_private; 125 126 return to_dpu_kms(priv->kms); 127 } 128 129 /** 130 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 131 * @plane: Pointer to drm plane. 132 * @fb: Pointer to framebuffer associated with the given plane 133 * @pipe_cfg: Pointer to pipe configuration 134 * Result: Updates calculated bandwidth in the plane state. 135 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 136 * Prefill BW Equation: line src bytes * line_time 137 */ 138 static void _dpu_plane_calc_bw(struct drm_plane *plane, 139 struct drm_framebuffer *fb, 140 struct dpu_hw_pipe_cfg *pipe_cfg) 141 { 142 struct dpu_plane_state *pstate; 143 struct drm_display_mode *mode; 144 const struct dpu_format *fmt = NULL; 145 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 146 int src_width, src_height, dst_height, fps; 147 u64 plane_prefill_bw; 148 u64 plane_bw; 149 u32 hw_latency_lines; 150 u64 scale_factor; 151 int vbp, vpw, vfp; 152 153 pstate = to_dpu_plane_state(plane->state); 154 mode = &plane->state->crtc->mode; 155 156 fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier); 157 158 src_width = drm_rect_width(&pipe_cfg->src_rect); 159 src_height = drm_rect_height(&pipe_cfg->src_rect); 160 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 161 fps = drm_mode_vrefresh(mode); 162 vbp = mode->vtotal - mode->vsync_end; 163 vpw = mode->vsync_end - mode->vsync_start; 164 vfp = mode->vsync_start - mode->vdisplay; 165 hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines; 166 scale_factor = src_height > dst_height ? 167 mult_frac(src_height, 1, dst_height) : 1; 168 169 plane_bw = 170 src_width * mode->vtotal * fps * fmt->bpp * 171 scale_factor; 172 173 plane_prefill_bw = 174 src_width * hw_latency_lines * fps * fmt->bpp * 175 scale_factor * mode->vtotal; 176 177 if ((vbp+vpw) > hw_latency_lines) 178 do_div(plane_prefill_bw, (vbp+vpw)); 179 else if ((vbp+vpw+vfp) < hw_latency_lines) 180 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 181 else 182 do_div(plane_prefill_bw, hw_latency_lines); 183 184 185 pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); 186 } 187 188 /** 189 * _dpu_plane_calc_clk - calculate clock required for a plane 190 * @plane: Pointer to drm plane. 191 * @pipe_cfg: Pointer to pipe configuration 192 * Result: Updates calculated clock in the plane state. 193 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 194 */ 195 static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg) 196 { 197 struct dpu_plane_state *pstate; 198 struct drm_display_mode *mode; 199 int dst_width, src_height, dst_height, fps; 200 201 pstate = to_dpu_plane_state(plane->state); 202 mode = &plane->state->crtc->mode; 203 204 src_height = drm_rect_height(&pipe_cfg->src_rect); 205 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 206 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 207 fps = drm_mode_vrefresh(mode); 208 209 pstate->plane_clk = 210 dst_width * mode->vtotal * fps; 211 212 if (src_height > dst_height) { 213 pstate->plane_clk *= src_height; 214 do_div(pstate->plane_clk, dst_height); 215 } 216 } 217 218 /** 219 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 220 * @plane: Pointer to drm plane 221 * @fmt: Pointer to source buffer format 222 * @src_width: width of source buffer 223 * Return: fill level corresponding to the source buffer/format or 0 if error 224 */ 225 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 226 const struct dpu_format *fmt, u32 src_width) 227 { 228 struct dpu_plane *pdpu; 229 struct dpu_plane_state *pstate; 230 u32 fixed_buff_size; 231 u32 total_fl; 232 233 if (!fmt || !plane->state || !src_width || !fmt->bpp) { 234 DPU_ERROR("invalid arguments\n"); 235 return 0; 236 } 237 238 pdpu = to_dpu_plane(plane); 239 pstate = to_dpu_plane_state(plane->state); 240 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 241 242 /* FIXME: in multirect case account for the src_width of all the planes */ 243 244 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 245 if (fmt->chroma_sample == DPU_CHROMA_420) { 246 /* NV12 */ 247 total_fl = (fixed_buff_size / 2) / 248 ((src_width + 32) * fmt->bpp); 249 } else { 250 /* non NV12 */ 251 total_fl = (fixed_buff_size / 2) * 2 / 252 ((src_width + 32) * fmt->bpp); 253 } 254 } else { 255 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 256 total_fl = (fixed_buff_size / 2) * 2 / 257 ((src_width + 32) * fmt->bpp); 258 } else { 259 total_fl = (fixed_buff_size) * 2 / 260 ((src_width + 32) * fmt->bpp); 261 } 262 } 263 264 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", 265 pdpu->pipe - SSPP_VIG0, 266 (char *)&fmt->base.pixel_format, 267 src_width, total_fl); 268 269 return total_fl; 270 } 271 272 /** 273 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 274 * @plane: Pointer to drm plane 275 * @fb: Pointer to framebuffer associated with the given plane 276 * @pipe_cfg: Pointer to pipe configuration 277 */ 278 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 279 struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg) 280 { 281 struct dpu_plane *pdpu = to_dpu_plane(plane); 282 const struct dpu_format *fmt = NULL; 283 u64 qos_lut; 284 u32 total_fl = 0, lut_usage; 285 286 if (!pdpu->is_rt_pipe) { 287 lut_usage = DPU_QOS_LUT_USAGE_NRT; 288 } else { 289 fmt = dpu_get_dpu_format_ext( 290 fb->format->format, 291 fb->modifier); 292 total_fl = _dpu_plane_calc_fill_level(plane, fmt, 293 drm_rect_width(&pipe_cfg->src_rect)); 294 295 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 296 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 297 else 298 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 299 } 300 301 qos_lut = _dpu_hw_get_qos_lut( 302 &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 303 304 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, 305 (fmt) ? fmt->base.pixel_format : 0, 306 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); 307 308 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 309 pdpu->pipe - SSPP_VIG0, 310 fmt ? (char *)&fmt->base.pixel_format : NULL, 311 pdpu->is_rt_pipe, total_fl, qos_lut); 312 313 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut); 314 } 315 316 /** 317 * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane 318 * @plane: Pointer to drm plane 319 * @fb: Pointer to framebuffer associated with the given plane 320 */ 321 static void _dpu_plane_set_danger_lut(struct drm_plane *plane, 322 struct drm_framebuffer *fb) 323 { 324 struct dpu_plane *pdpu = to_dpu_plane(plane); 325 const struct dpu_format *fmt = NULL; 326 u32 danger_lut, safe_lut; 327 328 if (!pdpu->is_rt_pipe) { 329 danger_lut = pdpu->catalog->perf->danger_lut_tbl 330 [DPU_QOS_LUT_USAGE_NRT]; 331 safe_lut = pdpu->catalog->perf->safe_lut_tbl 332 [DPU_QOS_LUT_USAGE_NRT]; 333 } else { 334 fmt = dpu_get_dpu_format_ext( 335 fb->format->format, 336 fb->modifier); 337 338 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { 339 danger_lut = pdpu->catalog->perf->danger_lut_tbl 340 [DPU_QOS_LUT_USAGE_LINEAR]; 341 safe_lut = pdpu->catalog->perf->safe_lut_tbl 342 [DPU_QOS_LUT_USAGE_LINEAR]; 343 } else { 344 danger_lut = pdpu->catalog->perf->danger_lut_tbl 345 [DPU_QOS_LUT_USAGE_MACROTILE]; 346 safe_lut = pdpu->catalog->perf->safe_lut_tbl 347 [DPU_QOS_LUT_USAGE_MACROTILE]; 348 } 349 } 350 351 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 352 (fmt) ? fmt->base.pixel_format : 0, 353 (fmt) ? fmt->fetch_mode : 0, 354 danger_lut, 355 safe_lut); 356 357 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 358 pdpu->pipe - SSPP_VIG0, 359 fmt ? (char *)&fmt->base.pixel_format : NULL, 360 fmt ? fmt->fetch_mode : -1, 361 danger_lut, 362 safe_lut); 363 364 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, 365 danger_lut, safe_lut); 366 } 367 368 /** 369 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 370 * @plane: Pointer to drm plane 371 * @enable: true to enable QoS control 372 * @flags: QoS control mode (enum dpu_plane_qos) 373 */ 374 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 375 bool enable, u32 flags) 376 { 377 struct dpu_plane *pdpu = to_dpu_plane(plane); 378 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; 379 380 memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); 381 382 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { 383 pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank; 384 pipe_qos_cfg.danger_vblank = 385 pdpu->pipe_hw->cap->sblk->danger_vblank; 386 pipe_qos_cfg.vblank_en = enable; 387 } 388 389 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { 390 /* this feature overrules previous VBLANK_CTRL */ 391 pipe_qos_cfg.vblank_en = false; 392 pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ 393 } 394 395 if (flags & DPU_PLANE_QOS_PANIC_CTRL) 396 pipe_qos_cfg.danger_safe_en = enable; 397 398 if (!pdpu->is_rt_pipe) { 399 pipe_qos_cfg.vblank_en = false; 400 pipe_qos_cfg.danger_safe_en = false; 401 } 402 403 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", 404 pdpu->pipe - SSPP_VIG0, 405 pipe_qos_cfg.danger_safe_en, 406 pipe_qos_cfg.vblank_en, 407 pipe_qos_cfg.creq_vblank, 408 pipe_qos_cfg.danger_vblank, 409 pdpu->is_rt_pipe); 410 411 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, 412 &pipe_qos_cfg); 413 } 414 415 /** 416 * _dpu_plane_set_ot_limit - set OT limit for the given plane 417 * @plane: Pointer to drm plane 418 * @crtc: Pointer to drm crtc 419 * @pipe_cfg: Pointer to pipe configuration 420 */ 421 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 422 struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg) 423 { 424 struct dpu_plane *pdpu = to_dpu_plane(plane); 425 struct dpu_vbif_set_ot_params ot_params; 426 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 427 428 memset(&ot_params, 0, sizeof(ot_params)); 429 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; 430 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; 431 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 432 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 433 ot_params.is_wfd = !pdpu->is_rt_pipe; 434 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); 435 ot_params.vbif_idx = VBIF_RT; 436 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 437 ot_params.rd = true; 438 439 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 440 } 441 442 /** 443 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 444 * @plane: Pointer to drm plane 445 */ 446 static void _dpu_plane_set_qos_remap(struct drm_plane *plane) 447 { 448 struct dpu_plane *pdpu = to_dpu_plane(plane); 449 struct dpu_vbif_set_qos_params qos_params; 450 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 451 452 memset(&qos_params, 0, sizeof(qos_params)); 453 qos_params.vbif_idx = VBIF_RT; 454 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 455 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; 456 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; 457 qos_params.is_rt = pdpu->is_rt_pipe; 458 459 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 460 qos_params.num, 461 qos_params.vbif_idx, 462 qos_params.xin_id, qos_params.is_rt, 463 qos_params.clk_ctrl); 464 465 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 466 } 467 468 static void _dpu_plane_set_scanout(struct drm_plane *plane, 469 struct dpu_plane_state *pstate, 470 struct dpu_hw_pipe_cfg *pipe_cfg, 471 struct drm_framebuffer *fb) 472 { 473 struct dpu_plane *pdpu = to_dpu_plane(plane); 474 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 475 struct msm_gem_address_space *aspace = kms->base.aspace; 476 int ret; 477 478 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); 479 if (ret == -EAGAIN) 480 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); 481 else if (ret) 482 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 483 else if (pdpu->pipe_hw->ops.setup_sourceaddress) { 484 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, 485 &pipe_cfg->layout, 486 pstate->multirect_index); 487 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, 488 pstate->multirect_index); 489 } 490 } 491 492 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 493 struct dpu_plane_state *pstate, 494 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 495 struct dpu_hw_scaler3_cfg *scale_cfg, 496 const struct dpu_format *fmt, 497 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 498 { 499 uint32_t i; 500 bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90; 501 502 /* 503 * For inline rotation cases, scaler config is post-rotation, 504 * so swap the dimensions here. However, pixel extension will 505 * need pre-rotation settings. 506 */ 507 if (inline_rotation) 508 swap(src_w, src_h); 509 510 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 511 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 512 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 513 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 514 515 516 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 517 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 518 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 519 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 520 521 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 522 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 523 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 524 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 525 526 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 527 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 528 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 529 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 530 531 for (i = 0; i < DPU_MAX_PLANES; i++) { 532 scale_cfg->src_width[i] = src_w; 533 scale_cfg->src_height[i] = src_h; 534 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 535 scale_cfg->src_width[i] /= chroma_subsmpl_h; 536 scale_cfg->src_height[i] /= chroma_subsmpl_v; 537 } 538 539 if (pdpu->pipe_hw->cap->features & 540 BIT(DPU_SSPP_SCALER_QSEED4)) { 541 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 542 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 543 } else { 544 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 545 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 546 } 547 } 548 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 549 && (src_w == dst_w)) 550 return; 551 552 scale_cfg->dst_width = dst_w; 553 scale_cfg->dst_height = dst_h; 554 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 555 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 556 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 557 scale_cfg->lut_flag = 0; 558 scale_cfg->blend_cfg = 1; 559 scale_cfg->enable = 1; 560 } 561 562 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 563 struct dpu_hw_pixel_ext *pixel_ext, 564 uint32_t src_w, uint32_t src_h, 565 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 566 { 567 int i; 568 569 for (i = 0; i < DPU_MAX_PLANES; i++) { 570 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 571 src_w /= chroma_subsmpl_h; 572 src_h /= chroma_subsmpl_v; 573 } 574 575 pixel_ext->num_ext_pxls_top[i] = src_h; 576 pixel_ext->num_ext_pxls_left[i] = src_w; 577 } 578 } 579 580 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 581 { 582 /* S15.16 format */ 583 0x00012A00, 0x00000000, 0x00019880, 584 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 585 0x00012A00, 0x00020480, 0x00000000, 586 }, 587 /* signed bias */ 588 { 0xfff0, 0xff80, 0xff80,}, 589 { 0x0, 0x0, 0x0,}, 590 /* unsigned clamp */ 591 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 592 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 593 }; 594 595 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 596 { 597 /* S15.16 format */ 598 0x00012A00, 0x00000000, 0x00019880, 599 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 600 0x00012A00, 0x00020480, 0x00000000, 601 }, 602 /* signed bias */ 603 { 0xffc0, 0xfe00, 0xfe00,}, 604 { 0x0, 0x0, 0x0,}, 605 /* unsigned clamp */ 606 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 607 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 608 }; 609 610 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) 611 { 612 const struct dpu_csc_cfg *csc_ptr; 613 614 if (!pdpu) { 615 DPU_ERROR("invalid plane\n"); 616 return NULL; 617 } 618 619 if (!DPU_FORMAT_IS_YUV(fmt)) 620 return NULL; 621 622 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features) 623 csc_ptr = &dpu_csc10_YUV2RGB_601L; 624 else 625 csc_ptr = &dpu_csc_YUV2RGB_601L; 626 627 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 628 csc_ptr->csc_mv[0], 629 csc_ptr->csc_mv[1], 630 csc_ptr->csc_mv[2]); 631 632 return csc_ptr; 633 } 634 635 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 636 struct dpu_plane_state *pstate, 637 const struct dpu_format *fmt, bool color_fill, 638 struct dpu_hw_pipe_cfg *pipe_cfg) 639 { 640 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 641 struct dpu_hw_scaler3_cfg scaler3_cfg; 642 struct dpu_hw_pixel_ext pixel_ext; 643 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 644 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 645 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 646 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 647 648 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 649 memset(&pixel_ext, 0, sizeof(pixel_ext)); 650 651 /* don't chroma subsample if decimating */ 652 /* update scaler. calculate default config for QSEED3 */ 653 _dpu_plane_setup_scaler3(pdpu, pstate, 654 src_width, 655 src_height, 656 dst_width, 657 dst_height, 658 &scaler3_cfg, fmt, 659 info->hsub, info->vsub); 660 661 /* configure pixel extension based on scalar config */ 662 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 663 src_width, src_height, info->hsub, info->vsub); 664 665 if (pdpu->pipe_hw->ops.setup_pe) 666 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 667 &pixel_ext); 668 669 /** 670 * when programmed in multirect mode, scalar block will be 671 * bypassed. Still we need to update alpha and bitwidth 672 * ONLY for RECT0 673 */ 674 if (pdpu->pipe_hw->ops.setup_scaler && 675 pstate->multirect_index != DPU_SSPP_RECT_1) 676 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 677 pipe_cfg, 678 &scaler3_cfg); 679 } 680 681 /** 682 * _dpu_plane_color_fill - enables color fill on plane 683 * @pdpu: Pointer to DPU plane object 684 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 685 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 686 * Returns: 0 on success 687 */ 688 static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 689 uint32_t color, uint32_t alpha) 690 { 691 const struct dpu_format *fmt; 692 const struct drm_plane *plane = &pdpu->base; 693 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 694 struct dpu_hw_pipe_cfg pipe_cfg; 695 696 DPU_DEBUG_PLANE(pdpu, "\n"); 697 698 /* 699 * select fill format to match user property expectation, 700 * h/w only supports RGB variants 701 */ 702 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 703 704 /* update sspp */ 705 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { 706 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, 707 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), 708 pstate->multirect_index); 709 710 /* override scaler/decimation if solid fill */ 711 pipe_cfg.dst_rect = pstate->base.dst; 712 713 pipe_cfg.src_rect.x1 = 0; 714 pipe_cfg.src_rect.y1 = 0; 715 pipe_cfg.src_rect.x2 = 716 drm_rect_width(&pipe_cfg.dst_rect); 717 pipe_cfg.src_rect.y2 = 718 drm_rect_height(&pipe_cfg.dst_rect); 719 720 if (pdpu->pipe_hw->ops.setup_format) 721 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, 722 fmt, DPU_SSPP_SOLID_FILL, 723 pstate->multirect_index); 724 725 if (pdpu->pipe_hw->ops.setup_rects) 726 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 727 &pipe_cfg, 728 pstate->multirect_index); 729 730 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); 731 } 732 733 return 0; 734 } 735 736 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) 737 { 738 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); 739 740 pstate->multirect_index = DPU_SSPP_RECT_SOLO; 741 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 742 } 743 744 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) 745 { 746 struct dpu_plane_state *pstate[R_MAX]; 747 const struct drm_plane_state *drm_state[R_MAX]; 748 struct drm_rect src[R_MAX], dst[R_MAX]; 749 struct dpu_plane *dpu_plane[R_MAX]; 750 const struct dpu_format *fmt[R_MAX]; 751 int i, buffer_lines; 752 unsigned int max_tile_height = 1; 753 bool parallel_fetch_qualified = true; 754 bool has_tiled_rect = false; 755 756 for (i = 0; i < R_MAX; i++) { 757 const struct msm_format *msm_fmt; 758 759 drm_state[i] = i ? plane->r1 : plane->r0; 760 msm_fmt = msm_framebuffer_format(drm_state[i]->fb); 761 fmt[i] = to_dpu_format(msm_fmt); 762 763 if (DPU_FORMAT_IS_UBWC(fmt[i])) { 764 has_tiled_rect = true; 765 if (fmt[i]->tile_height > max_tile_height) 766 max_tile_height = fmt[i]->tile_height; 767 } 768 } 769 770 for (i = 0; i < R_MAX; i++) { 771 int width_threshold; 772 773 pstate[i] = to_dpu_plane_state(drm_state[i]); 774 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); 775 776 if (pstate[i] == NULL) { 777 DPU_ERROR("DPU plane state of plane id %d is NULL\n", 778 drm_state[i]->plane->base.id); 779 return -EINVAL; 780 } 781 782 src[i].x1 = drm_state[i]->src_x >> 16; 783 src[i].y1 = drm_state[i]->src_y >> 16; 784 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); 785 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); 786 787 dst[i] = drm_plane_state_dest(drm_state[i]); 788 789 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || 790 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { 791 DPU_ERROR_PLANE(dpu_plane[i], 792 "scaling is not supported in multirect mode\n"); 793 return -EINVAL; 794 } 795 796 if (DPU_FORMAT_IS_YUV(fmt[i])) { 797 DPU_ERROR_PLANE(dpu_plane[i], 798 "Unsupported format for multirect mode\n"); 799 return -EINVAL; 800 } 801 802 /** 803 * SSPP PD_MEM is split half - one for each RECT. 804 * Tiled formats need 5 lines of buffering while fetching 805 * whereas linear formats need only 2 lines. 806 * So we cannot support more than half of the supported SSPP 807 * width for tiled formats. 808 */ 809 width_threshold = dpu_plane[i]->catalog->caps->max_linewidth; 810 if (has_tiled_rect) 811 width_threshold /= 2; 812 813 if (parallel_fetch_qualified && 814 drm_rect_width(&src[i]) > width_threshold) 815 parallel_fetch_qualified = false; 816 817 } 818 819 /* Validate RECT's and set the mode */ 820 821 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ 822 if (parallel_fetch_qualified) { 823 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 824 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 825 826 goto done; 827 } 828 829 /* TIME_MX Mode */ 830 buffer_lines = 2 * max_tile_height; 831 832 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || 833 dst[R0].y1 >= dst[R1].y2 + buffer_lines) { 834 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 835 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 836 } else { 837 DPU_ERROR( 838 "No multirect mode possible for the planes (%d - %d)\n", 839 drm_state[R0]->plane->base.id, 840 drm_state[R1]->plane->base.id); 841 return -EINVAL; 842 } 843 844 done: 845 pstate[R0]->multirect_index = DPU_SSPP_RECT_0; 846 pstate[R1]->multirect_index = DPU_SSPP_RECT_1; 847 848 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", 849 pstate[R0]->multirect_mode, pstate[R0]->multirect_index); 850 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", 851 pstate[R1]->multirect_mode, pstate[R1]->multirect_index); 852 return 0; 853 } 854 855 static int dpu_plane_prepare_fb(struct drm_plane *plane, 856 struct drm_plane_state *new_state) 857 { 858 struct drm_framebuffer *fb = new_state->fb; 859 struct dpu_plane *pdpu = to_dpu_plane(plane); 860 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 861 struct dpu_hw_fmt_layout layout; 862 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 863 int ret; 864 865 if (!new_state->fb) 866 return 0; 867 868 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 869 870 /* cache aspace */ 871 pstate->aspace = kms->base.aspace; 872 873 /* 874 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 875 * we can use msm_atomic_prepare_fb() instead of doing the 876 * implicit fence and fb prepare by hand here. 877 */ 878 drm_gem_plane_helper_prepare_fb(plane, new_state); 879 880 if (pstate->aspace) { 881 ret = msm_framebuffer_prepare(new_state->fb, 882 pstate->aspace, pstate->needs_dirtyfb); 883 if (ret) { 884 DPU_ERROR("failed to prepare framebuffer\n"); 885 return ret; 886 } 887 } 888 889 /* validate framebuffer layout before commit */ 890 ret = dpu_format_populate_layout(pstate->aspace, 891 new_state->fb, &layout); 892 if (ret) { 893 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 894 return ret; 895 } 896 897 return 0; 898 } 899 900 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 901 struct drm_plane_state *old_state) 902 { 903 struct dpu_plane *pdpu = to_dpu_plane(plane); 904 struct dpu_plane_state *old_pstate; 905 906 if (!old_state || !old_state->fb) 907 return; 908 909 old_pstate = to_dpu_plane_state(old_state); 910 911 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 912 913 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace, 914 old_pstate->needs_dirtyfb); 915 } 916 917 static bool dpu_plane_validate_src(struct drm_rect *src, 918 struct drm_rect *fb_rect, 919 uint32_t min_src_size) 920 { 921 /* Ensure fb size is supported */ 922 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || 923 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) 924 return false; 925 926 /* Ensure src rect is above the minimum size */ 927 if (drm_rect_width(src) < min_src_size || 928 drm_rect_height(src) < min_src_size) 929 return false; 930 931 /* Ensure src is fully encapsulated in fb */ 932 return drm_rect_intersect(fb_rect, src) && 933 drm_rect_equals(fb_rect, src); 934 } 935 936 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 937 const struct dpu_sspp_sub_blks *sblk, 938 struct drm_rect src, const struct dpu_format *fmt) 939 { 940 size_t num_formats; 941 const u32 *supported_formats; 942 943 if (!sblk->rotation_cfg) { 944 DPU_ERROR("invalid rotation cfg\n"); 945 return -EINVAL; 946 } 947 948 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 949 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 950 src.y2, sblk->rotation_cfg->rot_maxheight); 951 return -EINVAL; 952 } 953 954 supported_formats = sblk->rotation_cfg->rot_format_list; 955 num_formats = sblk->rotation_cfg->rot_num_formats; 956 957 if (!DPU_FORMAT_IS_UBWC(fmt) || 958 !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats)) 959 return -EINVAL; 960 961 return 0; 962 } 963 964 static int dpu_plane_atomic_check(struct drm_plane *plane, 965 struct drm_atomic_state *state) 966 { 967 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 968 plane); 969 int ret = 0, min_scale; 970 struct dpu_plane *pdpu = to_dpu_plane(plane); 971 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 972 const struct drm_crtc_state *crtc_state = NULL; 973 const struct dpu_format *fmt; 974 struct drm_rect src, dst, fb_rect = { 0 }; 975 uint32_t min_src_size, max_linewidth; 976 unsigned int rotation; 977 uint32_t supported_rotations; 978 const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap; 979 const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk; 980 981 if (new_plane_state->crtc) 982 crtc_state = drm_atomic_get_new_crtc_state(state, 983 new_plane_state->crtc); 984 985 min_scale = FRAC_16_16(1, sblk->maxupscale); 986 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 987 min_scale, 988 sblk->maxdwnscale << 16, 989 true, true); 990 if (ret) { 991 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 992 return ret; 993 } 994 if (!new_plane_state->visible) 995 return 0; 996 997 src.x1 = new_plane_state->src_x >> 16; 998 src.y1 = new_plane_state->src_y >> 16; 999 src.x2 = src.x1 + (new_plane_state->src_w >> 16); 1000 src.y2 = src.y1 + (new_plane_state->src_h >> 16); 1001 1002 dst = drm_plane_state_dest(new_plane_state); 1003 1004 fb_rect.x2 = new_plane_state->fb->width; 1005 fb_rect.y2 = new_plane_state->fb->height; 1006 1007 max_linewidth = pdpu->catalog->caps->max_linewidth; 1008 1009 fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); 1010 1011 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 1012 1013 if (DPU_FORMAT_IS_YUV(fmt) && 1014 (!(pipe_hw_caps->features & DPU_SSPP_SCALER) || 1015 !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) { 1016 DPU_DEBUG_PLANE(pdpu, 1017 "plane doesn't have scaler/csc for yuv\n"); 1018 return -EINVAL; 1019 1020 /* check src bounds */ 1021 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { 1022 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 1023 DRM_RECT_ARG(&src)); 1024 return -E2BIG; 1025 1026 /* valid yuv image */ 1027 } else if (DPU_FORMAT_IS_YUV(fmt) && 1028 (src.x1 & 0x1 || src.y1 & 0x1 || 1029 drm_rect_width(&src) & 0x1 || 1030 drm_rect_height(&src) & 0x1)) { 1031 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 1032 DRM_RECT_ARG(&src)); 1033 return -EINVAL; 1034 1035 /* min dst support */ 1036 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { 1037 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 1038 DRM_RECT_ARG(&dst)); 1039 return -EINVAL; 1040 1041 /* check decimated source width */ 1042 } else if (drm_rect_width(&src) > max_linewidth) { 1043 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 1044 DRM_RECT_ARG(&src), max_linewidth); 1045 return -E2BIG; 1046 } 1047 1048 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 1049 1050 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1051 supported_rotations |= DRM_MODE_ROTATE_90; 1052 1053 rotation = drm_rotation_simplify(new_plane_state->rotation, 1054 supported_rotations); 1055 1056 if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 1057 (rotation & DRM_MODE_ROTATE_90)) { 1058 ret = dpu_plane_check_inline_rotation(pdpu, sblk, src, fmt); 1059 if (ret) 1060 return ret; 1061 } 1062 1063 pstate->rotation = rotation; 1064 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 1065 1066 return 0; 1067 } 1068 1069 void dpu_plane_flush(struct drm_plane *plane) 1070 { 1071 struct dpu_plane *pdpu; 1072 struct dpu_plane_state *pstate; 1073 1074 if (!plane || !plane->state) { 1075 DPU_ERROR("invalid plane\n"); 1076 return; 1077 } 1078 1079 pdpu = to_dpu_plane(plane); 1080 pstate = to_dpu_plane_state(plane->state); 1081 1082 /* 1083 * These updates have to be done immediately before the plane flush 1084 * timing, and may not be moved to the atomic_update/mode_set functions. 1085 */ 1086 if (pdpu->is_error) 1087 /* force white frame with 100% alpha pipe output on error */ 1088 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 1089 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 1090 /* force 100% alpha */ 1091 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1092 else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) { 1093 const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb)); 1094 const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt); 1095 1096 if (csc_ptr) 1097 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr); 1098 } 1099 1100 /* flag h/w flush complete */ 1101 if (plane->state) 1102 pstate->pending = false; 1103 } 1104 1105 /** 1106 * dpu_plane_set_error: enable/disable error condition 1107 * @plane: pointer to drm_plane structure 1108 * @error: error value to set 1109 */ 1110 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1111 { 1112 struct dpu_plane *pdpu; 1113 1114 if (!plane) 1115 return; 1116 1117 pdpu = to_dpu_plane(plane); 1118 pdpu->is_error = error; 1119 } 1120 1121 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1122 { 1123 uint32_t src_flags; 1124 struct dpu_plane *pdpu = to_dpu_plane(plane); 1125 struct drm_plane_state *state = plane->state; 1126 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1127 struct drm_crtc *crtc = state->crtc; 1128 struct drm_framebuffer *fb = state->fb; 1129 bool is_rt_pipe; 1130 const struct dpu_format *fmt = 1131 to_dpu_format(msm_framebuffer_format(fb)); 1132 struct dpu_hw_pipe_cfg pipe_cfg; 1133 1134 memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg)); 1135 1136 _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb); 1137 1138 pstate->pending = true; 1139 1140 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1141 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); 1142 pdpu->is_rt_pipe = is_rt_pipe; 1143 1144 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1145 1146 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1147 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1148 crtc->base.id, DRM_RECT_ARG(&state->dst), 1149 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1150 1151 pipe_cfg.src_rect = state->src; 1152 1153 /* state->src is 16.16, src_rect is not */ 1154 pipe_cfg.src_rect.x1 >>= 16; 1155 pipe_cfg.src_rect.x2 >>= 16; 1156 pipe_cfg.src_rect.y1 >>= 16; 1157 pipe_cfg.src_rect.y2 >>= 16; 1158 1159 pipe_cfg.dst_rect = state->dst; 1160 1161 /* override for color fill */ 1162 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1163 /* skip remaining processing on color fill */ 1164 return; 1165 } 1166 1167 if (pdpu->pipe_hw->ops.setup_rects) { 1168 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 1169 &pipe_cfg, 1170 pstate->multirect_index); 1171 } 1172 1173 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); 1174 1175 if (pdpu->pipe_hw->ops.setup_multirect) 1176 pdpu->pipe_hw->ops.setup_multirect( 1177 pdpu->pipe_hw, 1178 pstate->multirect_index, 1179 pstate->multirect_mode); 1180 1181 if (pdpu->pipe_hw->ops.setup_format) { 1182 unsigned int rotation = pstate->rotation; 1183 1184 src_flags = 0x0; 1185 1186 if (rotation & DRM_MODE_REFLECT_X) 1187 src_flags |= DPU_SSPP_FLIP_LR; 1188 1189 if (rotation & DRM_MODE_REFLECT_Y) 1190 src_flags |= DPU_SSPP_FLIP_UD; 1191 1192 if (rotation & DRM_MODE_ROTATE_90) 1193 src_flags |= DPU_SSPP_ROT_90; 1194 1195 /* update format */ 1196 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, 1197 pstate->multirect_index); 1198 1199 if (pdpu->pipe_hw->ops.setup_cdp) { 1200 struct dpu_hw_cdp_cfg cdp_cfg; 1201 1202 memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); 1203 1204 cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg 1205 [DPU_PERF_CDP_USAGE_RT].rd_enable; 1206 cdp_cfg.ubwc_meta_enable = 1207 DPU_FORMAT_IS_UBWC(fmt); 1208 cdp_cfg.tile_amortize_enable = 1209 DPU_FORMAT_IS_UBWC(fmt) || 1210 DPU_FORMAT_IS_TILE(fmt); 1211 cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; 1212 1213 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index); 1214 } 1215 } 1216 1217 _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg); 1218 _dpu_plane_set_danger_lut(plane, fb); 1219 1220 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 1221 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); 1222 _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg); 1223 } 1224 1225 if (pstate->needs_qos_remap) { 1226 pstate->needs_qos_remap = false; 1227 _dpu_plane_set_qos_remap(plane); 1228 } 1229 1230 _dpu_plane_calc_bw(plane, fb, &pipe_cfg); 1231 1232 _dpu_plane_calc_clk(plane, &pipe_cfg); 1233 } 1234 1235 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1236 { 1237 struct drm_plane_state *state = plane->state; 1238 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1239 1240 trace_dpu_plane_disable(DRMID(plane), false, 1241 pstate->multirect_mode); 1242 1243 pstate->pending = true; 1244 } 1245 1246 static void dpu_plane_atomic_update(struct drm_plane *plane, 1247 struct drm_atomic_state *state) 1248 { 1249 struct dpu_plane *pdpu = to_dpu_plane(plane); 1250 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1251 plane); 1252 1253 pdpu->is_error = false; 1254 1255 DPU_DEBUG_PLANE(pdpu, "\n"); 1256 1257 if (!new_state->visible) { 1258 _dpu_plane_atomic_disable(plane); 1259 } else { 1260 dpu_plane_sspp_atomic_update(plane); 1261 } 1262 } 1263 1264 static void dpu_plane_destroy(struct drm_plane *plane) 1265 { 1266 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1267 1268 DPU_DEBUG_PLANE(pdpu, "\n"); 1269 1270 if (pdpu) { 1271 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1272 1273 mutex_destroy(&pdpu->lock); 1274 1275 /* this will destroy the states as well */ 1276 drm_plane_cleanup(plane); 1277 1278 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1279 1280 kfree(pdpu); 1281 } 1282 } 1283 1284 static void dpu_plane_destroy_state(struct drm_plane *plane, 1285 struct drm_plane_state *state) 1286 { 1287 __drm_atomic_helper_plane_destroy_state(state); 1288 kfree(to_dpu_plane_state(state)); 1289 } 1290 1291 static struct drm_plane_state * 1292 dpu_plane_duplicate_state(struct drm_plane *plane) 1293 { 1294 struct dpu_plane *pdpu; 1295 struct dpu_plane_state *pstate; 1296 struct dpu_plane_state *old_state; 1297 1298 if (!plane) { 1299 DPU_ERROR("invalid plane\n"); 1300 return NULL; 1301 } else if (!plane->state) { 1302 DPU_ERROR("invalid plane state\n"); 1303 return NULL; 1304 } 1305 1306 old_state = to_dpu_plane_state(plane->state); 1307 pdpu = to_dpu_plane(plane); 1308 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1309 if (!pstate) { 1310 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1311 return NULL; 1312 } 1313 1314 DPU_DEBUG_PLANE(pdpu, "\n"); 1315 1316 pstate->pending = false; 1317 1318 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1319 1320 return &pstate->base; 1321 } 1322 1323 static const char * const multirect_mode_name[] = { 1324 [DPU_SSPP_MULTIRECT_NONE] = "none", 1325 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1326 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1327 }; 1328 1329 static const char * const multirect_index_name[] = { 1330 [DPU_SSPP_RECT_SOLO] = "solo", 1331 [DPU_SSPP_RECT_0] = "rect_0", 1332 [DPU_SSPP_RECT_1] = "rect_1", 1333 }; 1334 1335 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1336 { 1337 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1338 return "unknown"; 1339 1340 return multirect_mode_name[mode]; 1341 } 1342 1343 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1344 { 1345 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1346 return "unknown"; 1347 1348 return multirect_index_name[index]; 1349 } 1350 1351 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1352 const struct drm_plane_state *state) 1353 { 1354 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1355 const struct dpu_plane *pdpu = to_dpu_plane(state->plane); 1356 1357 drm_printf(p, "\tstage=%d\n", pstate->stage); 1358 drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name); 1359 drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode)); 1360 drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index)); 1361 } 1362 1363 static void dpu_plane_reset(struct drm_plane *plane) 1364 { 1365 struct dpu_plane *pdpu; 1366 struct dpu_plane_state *pstate; 1367 1368 if (!plane) { 1369 DPU_ERROR("invalid plane\n"); 1370 return; 1371 } 1372 1373 pdpu = to_dpu_plane(plane); 1374 DPU_DEBUG_PLANE(pdpu, "\n"); 1375 1376 /* remove previous state, if present */ 1377 if (plane->state) { 1378 dpu_plane_destroy_state(plane, plane->state); 1379 plane->state = NULL; 1380 } 1381 1382 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1383 if (!pstate) { 1384 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1385 return; 1386 } 1387 1388 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1389 } 1390 1391 #ifdef CONFIG_DEBUG_FS 1392 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1393 { 1394 struct dpu_plane *pdpu = to_dpu_plane(plane); 1395 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1396 1397 if (!pdpu->is_rt_pipe) 1398 return; 1399 1400 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1401 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); 1402 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1403 } 1404 1405 /* SSPP live inside dpu_plane private data only. Enumerate them here. */ 1406 void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) 1407 { 1408 struct drm_plane *plane; 1409 struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); 1410 1411 if (IS_ERR(entry)) 1412 return; 1413 1414 drm_for_each_plane(plane, dpu_kms->dev) { 1415 struct dpu_plane *pdpu = to_dpu_plane(plane); 1416 1417 _dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry); 1418 } 1419 } 1420 #endif 1421 1422 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1423 uint32_t format, uint64_t modifier) 1424 { 1425 if (modifier == DRM_FORMAT_MOD_LINEAR) 1426 return true; 1427 1428 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) 1429 return dpu_find_format(format, qcom_compressed_supported_formats, 1430 ARRAY_SIZE(qcom_compressed_supported_formats)); 1431 1432 return false; 1433 } 1434 1435 static const struct drm_plane_funcs dpu_plane_funcs = { 1436 .update_plane = drm_atomic_helper_update_plane, 1437 .disable_plane = drm_atomic_helper_disable_plane, 1438 .destroy = dpu_plane_destroy, 1439 .reset = dpu_plane_reset, 1440 .atomic_duplicate_state = dpu_plane_duplicate_state, 1441 .atomic_destroy_state = dpu_plane_destroy_state, 1442 .atomic_print_state = dpu_plane_atomic_print_state, 1443 .format_mod_supported = dpu_plane_format_mod_supported, 1444 }; 1445 1446 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1447 .prepare_fb = dpu_plane_prepare_fb, 1448 .cleanup_fb = dpu_plane_cleanup_fb, 1449 .atomic_check = dpu_plane_atomic_check, 1450 .atomic_update = dpu_plane_atomic_update, 1451 }; 1452 1453 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) 1454 { 1455 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; 1456 } 1457 1458 /* initialize plane */ 1459 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1460 uint32_t pipe, enum drm_plane_type type, 1461 unsigned long possible_crtcs) 1462 { 1463 struct drm_plane *plane = NULL; 1464 const uint32_t *format_list; 1465 struct dpu_plane *pdpu; 1466 struct msm_drm_private *priv = dev->dev_private; 1467 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1468 uint32_t num_formats; 1469 uint32_t supported_rotations; 1470 int ret = -EINVAL; 1471 1472 /* create and zero local structure */ 1473 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1474 if (!pdpu) { 1475 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1476 ret = -ENOMEM; 1477 return ERR_PTR(ret); 1478 } 1479 1480 /* cache local stuff for later */ 1481 plane = &pdpu->base; 1482 pdpu->pipe = pipe; 1483 1484 /* initialize underlying h/w driver */ 1485 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog); 1486 if (IS_ERR(pdpu->pipe_hw)) { 1487 DPU_ERROR("[%u]SSPP init failed\n", pipe); 1488 ret = PTR_ERR(pdpu->pipe_hw); 1489 goto clean_plane; 1490 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { 1491 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); 1492 goto clean_sspp; 1493 } 1494 1495 format_list = pdpu->pipe_hw->cap->sblk->format_list; 1496 num_formats = pdpu->pipe_hw->cap->sblk->num_formats; 1497 1498 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1499 format_list, num_formats, 1500 supported_format_modifiers, type, NULL); 1501 if (ret) 1502 goto clean_sspp; 1503 1504 pdpu->catalog = kms->catalog; 1505 1506 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); 1507 if (ret) 1508 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1509 1510 drm_plane_create_alpha_property(plane); 1511 drm_plane_create_blend_mode_property(plane, 1512 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1513 BIT(DRM_MODE_BLEND_PREMULTI) | 1514 BIT(DRM_MODE_BLEND_COVERAGE)); 1515 1516 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1517 1518 if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1519 supported_rotations |= DRM_MODE_ROTATE_MASK; 1520 1521 drm_plane_create_rotation_property(plane, 1522 DRM_MODE_ROTATE_0, supported_rotations); 1523 1524 drm_plane_enable_fb_damage_clips(plane); 1525 1526 /* success! finalize initialization */ 1527 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1528 1529 mutex_init(&pdpu->lock); 1530 1531 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1532 pipe, plane->base.id); 1533 return plane; 1534 1535 clean_sspp: 1536 if (pdpu && pdpu->pipe_hw) 1537 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1538 clean_plane: 1539 kfree(pdpu); 1540 return ERR_PTR(ret); 1541 } 1542