1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_damage_helper.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_gem_framebuffer_helper.h> 16 17 #include "msm_drv.h" 18 #include "dpu_kms.h" 19 #include "dpu_formats.h" 20 #include "dpu_hw_sspp.h" 21 #include "dpu_hw_catalog_format.h" 22 #include "dpu_trace.h" 23 #include "dpu_crtc.h" 24 #include "dpu_vbif.h" 25 #include "dpu_plane.h" 26 27 #define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\ 28 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 29 30 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 31 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 32 33 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 34 #define PHASE_STEP_SHIFT 21 35 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 36 #define PHASE_RESIDUAL 15 37 38 #define SHARP_STRENGTH_DEFAULT 32 39 #define SHARP_EDGE_THR_DEFAULT 112 40 #define SHARP_SMOOTH_THR_DEFAULT 8 41 #define SHARP_NOISE_THR_DEFAULT 2 42 43 #define DPU_NAME_SIZE 12 44 45 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 46 #define DPU_ZPOS_MAX 255 47 48 /* multirect rect index */ 49 enum { 50 R0, 51 R1, 52 R_MAX 53 }; 54 55 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 56 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 57 58 #define DEFAULT_REFRESH_RATE 60 59 60 /** 61 * enum dpu_plane_qos - Different qos configurations for each pipe 62 * 63 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. 64 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. 65 * this configuration is mutually exclusive from VBLANK_CTRL. 66 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. 67 */ 68 enum dpu_plane_qos { 69 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), 70 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), 71 DPU_PLANE_QOS_PANIC_CTRL = BIT(2), 72 }; 73 74 /* 75 * struct dpu_plane - local dpu plane structure 76 * @aspace: address space pointer 77 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 78 * @mplane_list: List of multirect planes of the same pipe 79 * @catalog: Points to dpu catalog structure 80 * @revalidate: force revalidation of all the plane properties 81 */ 82 struct dpu_plane { 83 struct drm_plane base; 84 85 struct mutex lock; 86 87 enum dpu_sspp pipe; 88 uint32_t features; /* capabilities from catalog */ 89 90 struct dpu_hw_pipe *pipe_hw; 91 struct dpu_hw_pipe_cfg pipe_cfg; 92 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; 93 uint32_t color_fill; 94 bool is_error; 95 bool is_rt_pipe; 96 bool is_virtual; 97 struct list_head mplane_list; 98 struct dpu_mdss_cfg *catalog; 99 100 struct dpu_csc_cfg *csc_ptr; 101 102 const struct dpu_sspp_sub_blks *pipe_sblk; 103 char pipe_name[DPU_NAME_SIZE]; 104 105 /* debugfs related stuff */ 106 struct dentry *debugfs_root; 107 struct dpu_debugfs_regset32 debugfs_src; 108 struct dpu_debugfs_regset32 debugfs_scaler; 109 struct dpu_debugfs_regset32 debugfs_csc; 110 bool debugfs_default_scale; 111 }; 112 113 static const uint64_t supported_format_modifiers[] = { 114 DRM_FORMAT_MOD_QCOM_COMPRESSED, 115 DRM_FORMAT_MOD_LINEAR, 116 DRM_FORMAT_MOD_INVALID 117 }; 118 119 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 120 121 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 122 { 123 struct msm_drm_private *priv = plane->dev->dev_private; 124 125 return to_dpu_kms(priv->kms); 126 } 127 128 /** 129 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 130 * @plane: Pointer to drm plane 131 * @fmt: Pointer to source buffer format 132 * @src_wdith: width of source buffer 133 * Return: fill level corresponding to the source buffer/format or 0 if error 134 */ 135 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 136 const struct dpu_format *fmt, u32 src_width) 137 { 138 struct dpu_plane *pdpu, *tmp; 139 struct dpu_plane_state *pstate; 140 u32 fixed_buff_size; 141 u32 total_fl; 142 143 if (!fmt || !plane->state || !src_width || !fmt->bpp) { 144 DPU_ERROR("invalid arguments\n"); 145 return 0; 146 } 147 148 pdpu = to_dpu_plane(plane); 149 pstate = to_dpu_plane_state(plane->state); 150 fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size; 151 152 list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) { 153 if (!tmp->base.state->visible) 154 continue; 155 DPU_DEBUG("plane%d/%d src_width:%d/%d\n", 156 pdpu->base.base.id, tmp->base.base.id, 157 src_width, 158 drm_rect_width(&tmp->pipe_cfg.src_rect)); 159 src_width = max_t(u32, src_width, 160 drm_rect_width(&tmp->pipe_cfg.src_rect)); 161 } 162 163 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 164 if (fmt->chroma_sample == DPU_CHROMA_420) { 165 /* NV12 */ 166 total_fl = (fixed_buff_size / 2) / 167 ((src_width + 32) * fmt->bpp); 168 } else { 169 /* non NV12 */ 170 total_fl = (fixed_buff_size / 2) * 2 / 171 ((src_width + 32) * fmt->bpp); 172 } 173 } else { 174 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 175 total_fl = (fixed_buff_size / 2) * 2 / 176 ((src_width + 32) * fmt->bpp); 177 } else { 178 total_fl = (fixed_buff_size) * 2 / 179 ((src_width + 32) * fmt->bpp); 180 } 181 } 182 183 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n", 184 plane->base.id, pdpu->pipe - SSPP_VIG0, 185 (char *)&fmt->base.pixel_format, 186 src_width, total_fl); 187 188 return total_fl; 189 } 190 191 /** 192 * _dpu_plane_get_qos_lut - get LUT mapping based on fill level 193 * @tbl: Pointer to LUT table 194 * @total_fl: fill level 195 * Return: LUT setting corresponding to the fill level 196 */ 197 static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, 198 u32 total_fl) 199 { 200 int i; 201 202 if (!tbl || !tbl->nentry || !tbl->entries) 203 return 0; 204 205 for (i = 0; i < tbl->nentry; i++) 206 if (total_fl <= tbl->entries[i].fl) 207 return tbl->entries[i].lut; 208 209 /* if last fl is zero, use as default */ 210 if (!tbl->entries[i-1].fl) 211 return tbl->entries[i-1].lut; 212 213 return 0; 214 } 215 216 /** 217 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 218 * @plane: Pointer to drm plane 219 * @fb: Pointer to framebuffer associated with the given plane 220 */ 221 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 222 struct drm_framebuffer *fb) 223 { 224 struct dpu_plane *pdpu = to_dpu_plane(plane); 225 const struct dpu_format *fmt = NULL; 226 u64 qos_lut; 227 u32 total_fl = 0, lut_usage; 228 229 if (!pdpu->is_rt_pipe) { 230 lut_usage = DPU_QOS_LUT_USAGE_NRT; 231 } else { 232 fmt = dpu_get_dpu_format_ext( 233 fb->format->format, 234 fb->modifier); 235 total_fl = _dpu_plane_calc_fill_level(plane, fmt, 236 drm_rect_width(&pdpu->pipe_cfg.src_rect)); 237 238 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 239 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 240 else 241 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 242 } 243 244 qos_lut = _dpu_plane_get_qos_lut( 245 &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); 246 247 pdpu->pipe_qos_cfg.creq_lut = qos_lut; 248 249 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, 250 (fmt) ? fmt->base.pixel_format : 0, 251 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); 252 253 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 254 plane->base.id, 255 pdpu->pipe - SSPP_VIG0, 256 fmt ? (char *)&fmt->base.pixel_format : NULL, 257 pdpu->is_rt_pipe, total_fl, qos_lut); 258 259 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg); 260 } 261 262 /** 263 * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane 264 * @plane: Pointer to drm plane 265 * @fb: Pointer to framebuffer associated with the given plane 266 */ 267 static void _dpu_plane_set_danger_lut(struct drm_plane *plane, 268 struct drm_framebuffer *fb) 269 { 270 struct dpu_plane *pdpu = to_dpu_plane(plane); 271 const struct dpu_format *fmt = NULL; 272 u32 danger_lut, safe_lut; 273 274 if (!pdpu->is_rt_pipe) { 275 danger_lut = pdpu->catalog->perf.danger_lut_tbl 276 [DPU_QOS_LUT_USAGE_NRT]; 277 safe_lut = pdpu->catalog->perf.safe_lut_tbl 278 [DPU_QOS_LUT_USAGE_NRT]; 279 } else { 280 fmt = dpu_get_dpu_format_ext( 281 fb->format->format, 282 fb->modifier); 283 284 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { 285 danger_lut = pdpu->catalog->perf.danger_lut_tbl 286 [DPU_QOS_LUT_USAGE_LINEAR]; 287 safe_lut = pdpu->catalog->perf.safe_lut_tbl 288 [DPU_QOS_LUT_USAGE_LINEAR]; 289 } else { 290 danger_lut = pdpu->catalog->perf.danger_lut_tbl 291 [DPU_QOS_LUT_USAGE_MACROTILE]; 292 safe_lut = pdpu->catalog->perf.safe_lut_tbl 293 [DPU_QOS_LUT_USAGE_MACROTILE]; 294 } 295 } 296 297 pdpu->pipe_qos_cfg.danger_lut = danger_lut; 298 pdpu->pipe_qos_cfg.safe_lut = safe_lut; 299 300 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 301 (fmt) ? fmt->base.pixel_format : 0, 302 (fmt) ? fmt->fetch_mode : 0, 303 pdpu->pipe_qos_cfg.danger_lut, 304 pdpu->pipe_qos_cfg.safe_lut); 305 306 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 307 plane->base.id, 308 pdpu->pipe - SSPP_VIG0, 309 fmt ? (char *)&fmt->base.pixel_format : NULL, 310 fmt ? fmt->fetch_mode : -1, 311 pdpu->pipe_qos_cfg.danger_lut, 312 pdpu->pipe_qos_cfg.safe_lut); 313 314 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, 315 &pdpu->pipe_qos_cfg); 316 } 317 318 /** 319 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 320 * @plane: Pointer to drm plane 321 * @enable: true to enable QoS control 322 * @flags: QoS control mode (enum dpu_plane_qos) 323 */ 324 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 325 bool enable, u32 flags) 326 { 327 struct dpu_plane *pdpu = to_dpu_plane(plane); 328 329 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { 330 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; 331 pdpu->pipe_qos_cfg.danger_vblank = 332 pdpu->pipe_sblk->danger_vblank; 333 pdpu->pipe_qos_cfg.vblank_en = enable; 334 } 335 336 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { 337 /* this feature overrules previous VBLANK_CTRL */ 338 pdpu->pipe_qos_cfg.vblank_en = false; 339 pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ 340 } 341 342 if (flags & DPU_PLANE_QOS_PANIC_CTRL) 343 pdpu->pipe_qos_cfg.danger_safe_en = enable; 344 345 if (!pdpu->is_rt_pipe) { 346 pdpu->pipe_qos_cfg.vblank_en = false; 347 pdpu->pipe_qos_cfg.danger_safe_en = false; 348 } 349 350 DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", 351 plane->base.id, 352 pdpu->pipe - SSPP_VIG0, 353 pdpu->pipe_qos_cfg.danger_safe_en, 354 pdpu->pipe_qos_cfg.vblank_en, 355 pdpu->pipe_qos_cfg.creq_vblank, 356 pdpu->pipe_qos_cfg.danger_vblank, 357 pdpu->is_rt_pipe); 358 359 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, 360 &pdpu->pipe_qos_cfg); 361 } 362 363 /** 364 * _dpu_plane_set_ot_limit - set OT limit for the given plane 365 * @plane: Pointer to drm plane 366 * @crtc: Pointer to drm crtc 367 */ 368 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 369 struct drm_crtc *crtc) 370 { 371 struct dpu_plane *pdpu = to_dpu_plane(plane); 372 struct dpu_vbif_set_ot_params ot_params; 373 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 374 375 memset(&ot_params, 0, sizeof(ot_params)); 376 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; 377 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; 378 ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect); 379 ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 380 ot_params.is_wfd = !pdpu->is_rt_pipe; 381 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); 382 ot_params.vbif_idx = VBIF_RT; 383 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 384 ot_params.rd = true; 385 386 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 387 } 388 389 /** 390 * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane 391 * @plane: Pointer to drm plane 392 */ 393 static void _dpu_plane_set_qos_remap(struct drm_plane *plane) 394 { 395 struct dpu_plane *pdpu = to_dpu_plane(plane); 396 struct dpu_vbif_set_qos_params qos_params; 397 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 398 399 memset(&qos_params, 0, sizeof(qos_params)); 400 qos_params.vbif_idx = VBIF_RT; 401 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 402 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; 403 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; 404 qos_params.is_rt = pdpu->is_rt_pipe; 405 406 DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 407 plane->base.id, qos_params.num, 408 qos_params.vbif_idx, 409 qos_params.xin_id, qos_params.is_rt, 410 qos_params.clk_ctrl); 411 412 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 413 } 414 415 static void _dpu_plane_set_scanout(struct drm_plane *plane, 416 struct dpu_plane_state *pstate, 417 struct dpu_hw_pipe_cfg *pipe_cfg, 418 struct drm_framebuffer *fb) 419 { 420 struct dpu_plane *pdpu = to_dpu_plane(plane); 421 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 422 struct msm_gem_address_space *aspace = kms->base.aspace; 423 int ret; 424 425 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); 426 if (ret == -EAGAIN) 427 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); 428 else if (ret) 429 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 430 else if (pdpu->pipe_hw->ops.setup_sourceaddress) { 431 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, 432 &pipe_cfg->layout, 433 pstate->multirect_index); 434 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, 435 pstate->multirect_index); 436 } 437 } 438 439 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 440 struct dpu_plane_state *pstate, 441 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 442 struct dpu_hw_scaler3_cfg *scale_cfg, 443 const struct dpu_format *fmt, 444 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 445 { 446 uint32_t i; 447 448 memset(scale_cfg, 0, sizeof(*scale_cfg)); 449 memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext)); 450 451 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 452 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 453 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 454 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 455 456 457 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 458 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 459 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 460 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 461 462 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 463 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 464 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 465 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 466 467 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 468 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 469 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 470 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 471 472 for (i = 0; i < DPU_MAX_PLANES; i++) { 473 scale_cfg->src_width[i] = src_w; 474 scale_cfg->src_height[i] = src_h; 475 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 476 scale_cfg->src_width[i] /= chroma_subsmpl_h; 477 scale_cfg->src_height[i] /= chroma_subsmpl_v; 478 } 479 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 480 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 481 pstate->pixel_ext.num_ext_pxls_top[i] = 482 scale_cfg->src_height[i]; 483 pstate->pixel_ext.num_ext_pxls_left[i] = 484 scale_cfg->src_width[i]; 485 } 486 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 487 && (src_w == dst_w)) 488 return; 489 490 scale_cfg->dst_width = dst_w; 491 scale_cfg->dst_height = dst_h; 492 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 493 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 494 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 495 scale_cfg->lut_flag = 0; 496 scale_cfg->blend_cfg = 1; 497 scale_cfg->enable = 1; 498 } 499 500 static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) 501 { 502 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 503 { 504 /* S15.16 format */ 505 0x00012A00, 0x00000000, 0x00019880, 506 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 507 0x00012A00, 0x00020480, 0x00000000, 508 }, 509 /* signed bias */ 510 { 0xfff0, 0xff80, 0xff80,}, 511 { 0x0, 0x0, 0x0,}, 512 /* unsigned clamp */ 513 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 514 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 515 }; 516 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 517 { 518 /* S15.16 format */ 519 0x00012A00, 0x00000000, 0x00019880, 520 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 521 0x00012A00, 0x00020480, 0x00000000, 522 }, 523 /* signed bias */ 524 { 0xffc0, 0xfe00, 0xfe00,}, 525 { 0x0, 0x0, 0x0,}, 526 /* unsigned clamp */ 527 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 528 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 529 }; 530 531 if (!pdpu) { 532 DPU_ERROR("invalid plane\n"); 533 return; 534 } 535 536 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features) 537 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L; 538 else 539 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L; 540 541 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 542 pdpu->csc_ptr->csc_mv[0], 543 pdpu->csc_ptr->csc_mv[1], 544 pdpu->csc_ptr->csc_mv[2]); 545 } 546 547 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 548 struct dpu_plane_state *pstate, 549 const struct dpu_format *fmt, bool color_fill) 550 { 551 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 552 553 /* don't chroma subsample if decimating */ 554 /* update scaler. calculate default config for QSEED3 */ 555 _dpu_plane_setup_scaler3(pdpu, pstate, 556 drm_rect_width(&pdpu->pipe_cfg.src_rect), 557 drm_rect_height(&pdpu->pipe_cfg.src_rect), 558 drm_rect_width(&pdpu->pipe_cfg.dst_rect), 559 drm_rect_height(&pdpu->pipe_cfg.dst_rect), 560 &pstate->scaler3_cfg, fmt, 561 info->hsub, info->vsub); 562 } 563 564 /** 565 * _dpu_plane_color_fill - enables color fill on plane 566 * @pdpu: Pointer to DPU plane object 567 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 568 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 569 * Returns: 0 on success 570 */ 571 static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 572 uint32_t color, uint32_t alpha) 573 { 574 const struct dpu_format *fmt; 575 const struct drm_plane *plane = &pdpu->base; 576 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 577 578 DPU_DEBUG_PLANE(pdpu, "\n"); 579 580 /* 581 * select fill format to match user property expectation, 582 * h/w only supports RGB variants 583 */ 584 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 585 586 /* update sspp */ 587 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { 588 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, 589 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), 590 pstate->multirect_index); 591 592 /* override scaler/decimation if solid fill */ 593 pdpu->pipe_cfg.src_rect.x1 = 0; 594 pdpu->pipe_cfg.src_rect.y1 = 0; 595 pdpu->pipe_cfg.src_rect.x2 = 596 drm_rect_width(&pdpu->pipe_cfg.dst_rect); 597 pdpu->pipe_cfg.src_rect.y2 = 598 drm_rect_height(&pdpu->pipe_cfg.dst_rect); 599 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true); 600 601 if (pdpu->pipe_hw->ops.setup_format) 602 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, 603 fmt, DPU_SSPP_SOLID_FILL, 604 pstate->multirect_index); 605 606 if (pdpu->pipe_hw->ops.setup_rects) 607 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 608 &pdpu->pipe_cfg, 609 pstate->multirect_index); 610 611 if (pdpu->pipe_hw->ops.setup_pe) 612 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 613 &pstate->pixel_ext); 614 615 if (pdpu->pipe_hw->ops.setup_scaler && 616 pstate->multirect_index != DPU_SSPP_RECT_1) 617 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 618 &pdpu->pipe_cfg, &pstate->pixel_ext, 619 &pstate->scaler3_cfg); 620 } 621 622 return 0; 623 } 624 625 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) 626 { 627 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); 628 629 pstate->multirect_index = DPU_SSPP_RECT_SOLO; 630 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 631 } 632 633 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) 634 { 635 struct dpu_plane_state *pstate[R_MAX]; 636 const struct drm_plane_state *drm_state[R_MAX]; 637 struct drm_rect src[R_MAX], dst[R_MAX]; 638 struct dpu_plane *dpu_plane[R_MAX]; 639 const struct dpu_format *fmt[R_MAX]; 640 int i, buffer_lines; 641 unsigned int max_tile_height = 1; 642 bool parallel_fetch_qualified = true; 643 bool has_tiled_rect = false; 644 645 for (i = 0; i < R_MAX; i++) { 646 const struct msm_format *msm_fmt; 647 648 drm_state[i] = i ? plane->r1 : plane->r0; 649 msm_fmt = msm_framebuffer_format(drm_state[i]->fb); 650 fmt[i] = to_dpu_format(msm_fmt); 651 652 if (DPU_FORMAT_IS_UBWC(fmt[i])) { 653 has_tiled_rect = true; 654 if (fmt[i]->tile_height > max_tile_height) 655 max_tile_height = fmt[i]->tile_height; 656 } 657 } 658 659 for (i = 0; i < R_MAX; i++) { 660 int width_threshold; 661 662 pstate[i] = to_dpu_plane_state(drm_state[i]); 663 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); 664 665 if (pstate[i] == NULL) { 666 DPU_ERROR("DPU plane state of plane id %d is NULL\n", 667 drm_state[i]->plane->base.id); 668 return -EINVAL; 669 } 670 671 src[i].x1 = drm_state[i]->src_x >> 16; 672 src[i].y1 = drm_state[i]->src_y >> 16; 673 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); 674 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); 675 676 dst[i] = drm_plane_state_dest(drm_state[i]); 677 678 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || 679 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { 680 DPU_ERROR_PLANE(dpu_plane[i], 681 "scaling is not supported in multirect mode\n"); 682 return -EINVAL; 683 } 684 685 if (DPU_FORMAT_IS_YUV(fmt[i])) { 686 DPU_ERROR_PLANE(dpu_plane[i], 687 "Unsupported format for multirect mode\n"); 688 return -EINVAL; 689 } 690 691 /** 692 * SSPP PD_MEM is split half - one for each RECT. 693 * Tiled formats need 5 lines of buffering while fetching 694 * whereas linear formats need only 2 lines. 695 * So we cannot support more than half of the supported SSPP 696 * width for tiled formats. 697 */ 698 width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth; 699 if (has_tiled_rect) 700 width_threshold /= 2; 701 702 if (parallel_fetch_qualified && 703 drm_rect_width(&src[i]) > width_threshold) 704 parallel_fetch_qualified = false; 705 706 } 707 708 /* Validate RECT's and set the mode */ 709 710 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ 711 if (parallel_fetch_qualified) { 712 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 713 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 714 715 goto done; 716 } 717 718 /* TIME_MX Mode */ 719 buffer_lines = 2 * max_tile_height; 720 721 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || 722 dst[R0].y1 >= dst[R1].y2 + buffer_lines) { 723 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 724 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 725 } else { 726 DPU_ERROR( 727 "No multirect mode possible for the planes (%d - %d)\n", 728 drm_state[R0]->plane->base.id, 729 drm_state[R1]->plane->base.id); 730 return -EINVAL; 731 } 732 733 done: 734 if (dpu_plane[R0]->is_virtual) { 735 pstate[R0]->multirect_index = DPU_SSPP_RECT_1; 736 pstate[R1]->multirect_index = DPU_SSPP_RECT_0; 737 } else { 738 pstate[R0]->multirect_index = DPU_SSPP_RECT_0; 739 pstate[R1]->multirect_index = DPU_SSPP_RECT_1; 740 }; 741 742 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", 743 pstate[R0]->multirect_mode, pstate[R0]->multirect_index); 744 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", 745 pstate[R1]->multirect_mode, pstate[R1]->multirect_index); 746 return 0; 747 } 748 749 /** 750 * dpu_plane_get_ctl_flush - get control flush for the given plane 751 * @plane: Pointer to drm plane structure 752 * @ctl: Pointer to hardware control driver 753 * @flush_sspp: Pointer to sspp flush control word 754 */ 755 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, 756 u32 *flush_sspp) 757 { 758 *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane)); 759 } 760 761 static int dpu_plane_prepare_fb(struct drm_plane *plane, 762 struct drm_plane_state *new_state) 763 { 764 struct drm_framebuffer *fb = new_state->fb; 765 struct dpu_plane *pdpu = to_dpu_plane(plane); 766 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 767 struct dpu_hw_fmt_layout layout; 768 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 769 int ret; 770 771 if (!new_state->fb) 772 return 0; 773 774 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 775 776 /* cache aspace */ 777 pstate->aspace = kms->base.aspace; 778 779 /* 780 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 781 * we can use msm_atomic_prepare_fb() instead of doing the 782 * implicit fence and fb prepare by hand here. 783 */ 784 drm_gem_fb_prepare_fb(plane, new_state); 785 786 if (pstate->aspace) { 787 ret = msm_framebuffer_prepare(new_state->fb, 788 pstate->aspace); 789 if (ret) { 790 DPU_ERROR("failed to prepare framebuffer\n"); 791 return ret; 792 } 793 } 794 795 /* validate framebuffer layout before commit */ 796 ret = dpu_format_populate_layout(pstate->aspace, 797 new_state->fb, &layout); 798 if (ret) { 799 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 800 return ret; 801 } 802 803 return 0; 804 } 805 806 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 807 struct drm_plane_state *old_state) 808 { 809 struct dpu_plane *pdpu = to_dpu_plane(plane); 810 struct dpu_plane_state *old_pstate; 811 812 if (!old_state || !old_state->fb) 813 return; 814 815 old_pstate = to_dpu_plane_state(old_state); 816 817 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 818 819 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace); 820 } 821 822 static bool dpu_plane_validate_src(struct drm_rect *src, 823 struct drm_rect *fb_rect, 824 uint32_t min_src_size) 825 { 826 /* Ensure fb size is supported */ 827 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || 828 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) 829 return false; 830 831 /* Ensure src rect is above the minimum size */ 832 if (drm_rect_width(src) < min_src_size || 833 drm_rect_height(src) < min_src_size) 834 return false; 835 836 /* Ensure src is fully encapsulated in fb */ 837 return drm_rect_intersect(fb_rect, src) && 838 drm_rect_equals(fb_rect, src); 839 } 840 841 static int dpu_plane_atomic_check(struct drm_plane *plane, 842 struct drm_plane_state *state) 843 { 844 int ret = 0, min_scale; 845 struct dpu_plane *pdpu = to_dpu_plane(plane); 846 const struct drm_crtc_state *crtc_state = NULL; 847 const struct dpu_format *fmt; 848 struct drm_rect src, dst, fb_rect = { 0 }; 849 uint32_t min_src_size, max_linewidth; 850 851 if (state->crtc) 852 crtc_state = drm_atomic_get_new_crtc_state(state->state, 853 state->crtc); 854 855 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale); 856 ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale, 857 pdpu->pipe_sblk->maxupscale << 16, 858 true, true); 859 if (ret) { 860 DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 861 return ret; 862 } 863 if (!state->visible) 864 return 0; 865 866 src.x1 = state->src_x >> 16; 867 src.y1 = state->src_y >> 16; 868 src.x2 = src.x1 + (state->src_w >> 16); 869 src.y2 = src.y1 + (state->src_h >> 16); 870 871 dst = drm_plane_state_dest(state); 872 873 fb_rect.x2 = state->fb->width; 874 fb_rect.y2 = state->fb->height; 875 876 max_linewidth = pdpu->pipe_sblk->common->maxlinewidth; 877 878 fmt = to_dpu_format(msm_framebuffer_format(state->fb)); 879 880 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 881 882 if (DPU_FORMAT_IS_YUV(fmt) && 883 (!(pdpu->features & DPU_SSPP_SCALER) || 884 !(pdpu->features & (BIT(DPU_SSPP_CSC) 885 | BIT(DPU_SSPP_CSC_10BIT))))) { 886 DPU_ERROR_PLANE(pdpu, 887 "plane doesn't have scaler/csc for yuv\n"); 888 return -EINVAL; 889 890 /* check src bounds */ 891 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { 892 DPU_ERROR_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 893 DRM_RECT_ARG(&src)); 894 return -E2BIG; 895 896 /* valid yuv image */ 897 } else if (DPU_FORMAT_IS_YUV(fmt) && 898 (src.x1 & 0x1 || src.y1 & 0x1 || 899 drm_rect_width(&src) & 0x1 || 900 drm_rect_height(&src) & 0x1)) { 901 DPU_ERROR_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 902 DRM_RECT_ARG(&src)); 903 return -EINVAL; 904 905 /* min dst support */ 906 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { 907 DPU_ERROR_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 908 DRM_RECT_ARG(&dst)); 909 return -EINVAL; 910 911 /* check decimated source width */ 912 } else if (drm_rect_width(&src) > max_linewidth) { 913 DPU_ERROR_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 914 DRM_RECT_ARG(&src), max_linewidth); 915 return -E2BIG; 916 } 917 918 return 0; 919 } 920 921 void dpu_plane_flush(struct drm_plane *plane) 922 { 923 struct dpu_plane *pdpu; 924 struct dpu_plane_state *pstate; 925 926 if (!plane || !plane->state) { 927 DPU_ERROR("invalid plane\n"); 928 return; 929 } 930 931 pdpu = to_dpu_plane(plane); 932 pstate = to_dpu_plane_state(plane->state); 933 934 /* 935 * These updates have to be done immediately before the plane flush 936 * timing, and may not be moved to the atomic_update/mode_set functions. 937 */ 938 if (pdpu->is_error) 939 /* force white frame with 100% alpha pipe output on error */ 940 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 941 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 942 /* force 100% alpha */ 943 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 944 else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc) 945 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr); 946 947 /* flag h/w flush complete */ 948 if (plane->state) 949 pstate->pending = false; 950 } 951 952 /** 953 * dpu_plane_set_error: enable/disable error condition 954 * @plane: pointer to drm_plane structure 955 */ 956 void dpu_plane_set_error(struct drm_plane *plane, bool error) 957 { 958 struct dpu_plane *pdpu; 959 960 if (!plane) 961 return; 962 963 pdpu = to_dpu_plane(plane); 964 pdpu->is_error = error; 965 } 966 967 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 968 { 969 uint32_t src_flags; 970 struct dpu_plane *pdpu = to_dpu_plane(plane); 971 struct drm_plane_state *state = plane->state; 972 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 973 struct drm_crtc *crtc = state->crtc; 974 struct drm_framebuffer *fb = state->fb; 975 const struct dpu_format *fmt = 976 to_dpu_format(msm_framebuffer_format(fb)); 977 978 memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg)); 979 980 _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb); 981 982 pstate->pending = true; 983 984 pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 985 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 986 987 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 988 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 989 crtc->base.id, DRM_RECT_ARG(&state->dst), 990 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 991 992 pdpu->pipe_cfg.src_rect = state->src; 993 994 /* state->src is 16.16, src_rect is not */ 995 pdpu->pipe_cfg.src_rect.x1 >>= 16; 996 pdpu->pipe_cfg.src_rect.x2 >>= 16; 997 pdpu->pipe_cfg.src_rect.y1 >>= 16; 998 pdpu->pipe_cfg.src_rect.y2 >>= 16; 999 1000 pdpu->pipe_cfg.dst_rect = state->dst; 1001 1002 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false); 1003 1004 /* override for color fill */ 1005 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1006 /* skip remaining processing on color fill */ 1007 return; 1008 } 1009 1010 if (pdpu->pipe_hw->ops.setup_rects) { 1011 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 1012 &pdpu->pipe_cfg, 1013 pstate->multirect_index); 1014 } 1015 1016 if (pdpu->pipe_hw->ops.setup_pe && 1017 (pstate->multirect_index != DPU_SSPP_RECT_1)) 1018 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 1019 &pstate->pixel_ext); 1020 1021 /** 1022 * when programmed in multirect mode, scalar block will be 1023 * bypassed. Still we need to update alpha and bitwidth 1024 * ONLY for RECT0 1025 */ 1026 if (pdpu->pipe_hw->ops.setup_scaler && 1027 pstate->multirect_index != DPU_SSPP_RECT_1) 1028 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 1029 &pdpu->pipe_cfg, &pstate->pixel_ext, 1030 &pstate->scaler3_cfg); 1031 1032 if (pdpu->pipe_hw->ops.setup_multirect) 1033 pdpu->pipe_hw->ops.setup_multirect( 1034 pdpu->pipe_hw, 1035 pstate->multirect_index, 1036 pstate->multirect_mode); 1037 1038 if (pdpu->pipe_hw->ops.setup_format) { 1039 src_flags = 0x0; 1040 1041 /* update format */ 1042 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, 1043 pstate->multirect_index); 1044 1045 if (pdpu->pipe_hw->ops.setup_cdp) { 1046 struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg; 1047 1048 memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg)); 1049 1050 cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg 1051 [DPU_PERF_CDP_USAGE_RT].rd_enable; 1052 cdp_cfg->ubwc_meta_enable = 1053 DPU_FORMAT_IS_UBWC(fmt); 1054 cdp_cfg->tile_amortize_enable = 1055 DPU_FORMAT_IS_UBWC(fmt) || 1056 DPU_FORMAT_IS_TILE(fmt); 1057 cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; 1058 1059 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg); 1060 } 1061 1062 /* update csc */ 1063 if (DPU_FORMAT_IS_YUV(fmt)) 1064 _dpu_plane_setup_csc(pdpu); 1065 else 1066 pdpu->csc_ptr = 0; 1067 } 1068 1069 _dpu_plane_set_qos_lut(plane, fb); 1070 _dpu_plane_set_danger_lut(plane, fb); 1071 1072 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 1073 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); 1074 _dpu_plane_set_ot_limit(plane, crtc); 1075 } 1076 1077 _dpu_plane_set_qos_remap(plane); 1078 } 1079 1080 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1081 { 1082 struct dpu_plane *pdpu = to_dpu_plane(plane); 1083 struct drm_plane_state *state = plane->state; 1084 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1085 1086 trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane), 1087 pstate->multirect_mode); 1088 1089 pstate->pending = true; 1090 1091 if (is_dpu_plane_virtual(plane) && 1092 pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect) 1093 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw, 1094 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE); 1095 } 1096 1097 static void dpu_plane_atomic_update(struct drm_plane *plane, 1098 struct drm_plane_state *old_state) 1099 { 1100 struct dpu_plane *pdpu = to_dpu_plane(plane); 1101 struct drm_plane_state *state = plane->state; 1102 1103 pdpu->is_error = false; 1104 1105 DPU_DEBUG_PLANE(pdpu, "\n"); 1106 1107 if (!state->visible) { 1108 _dpu_plane_atomic_disable(plane); 1109 } else { 1110 dpu_plane_sspp_atomic_update(plane); 1111 } 1112 } 1113 1114 void dpu_plane_restore(struct drm_plane *plane) 1115 { 1116 struct dpu_plane *pdpu; 1117 1118 if (!plane || !plane->state) { 1119 DPU_ERROR("invalid plane\n"); 1120 return; 1121 } 1122 1123 pdpu = to_dpu_plane(plane); 1124 1125 DPU_DEBUG_PLANE(pdpu, "\n"); 1126 1127 /* last plane state is same as current state */ 1128 dpu_plane_atomic_update(plane, plane->state); 1129 } 1130 1131 static void dpu_plane_destroy(struct drm_plane *plane) 1132 { 1133 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1134 1135 DPU_DEBUG_PLANE(pdpu, "\n"); 1136 1137 if (pdpu) { 1138 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1139 1140 mutex_destroy(&pdpu->lock); 1141 1142 /* this will destroy the states as well */ 1143 drm_plane_cleanup(plane); 1144 1145 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1146 1147 kfree(pdpu); 1148 } 1149 } 1150 1151 static void dpu_plane_destroy_state(struct drm_plane *plane, 1152 struct drm_plane_state *state) 1153 { 1154 __drm_atomic_helper_plane_destroy_state(state); 1155 kfree(to_dpu_plane_state(state)); 1156 } 1157 1158 static struct drm_plane_state * 1159 dpu_plane_duplicate_state(struct drm_plane *plane) 1160 { 1161 struct dpu_plane *pdpu; 1162 struct dpu_plane_state *pstate; 1163 struct dpu_plane_state *old_state; 1164 1165 if (!plane) { 1166 DPU_ERROR("invalid plane\n"); 1167 return NULL; 1168 } else if (!plane->state) { 1169 DPU_ERROR("invalid plane state\n"); 1170 return NULL; 1171 } 1172 1173 old_state = to_dpu_plane_state(plane->state); 1174 pdpu = to_dpu_plane(plane); 1175 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1176 if (!pstate) { 1177 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1178 return NULL; 1179 } 1180 1181 DPU_DEBUG_PLANE(pdpu, "\n"); 1182 1183 pstate->pending = false; 1184 1185 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1186 1187 return &pstate->base; 1188 } 1189 1190 static void dpu_plane_reset(struct drm_plane *plane) 1191 { 1192 struct dpu_plane *pdpu; 1193 struct dpu_plane_state *pstate; 1194 1195 if (!plane) { 1196 DPU_ERROR("invalid plane\n"); 1197 return; 1198 } 1199 1200 pdpu = to_dpu_plane(plane); 1201 DPU_DEBUG_PLANE(pdpu, "\n"); 1202 1203 /* remove previous state, if present */ 1204 if (plane->state) { 1205 dpu_plane_destroy_state(plane, plane->state); 1206 plane->state = 0; 1207 } 1208 1209 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1210 if (!pstate) { 1211 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1212 return; 1213 } 1214 1215 pstate->base.plane = plane; 1216 1217 plane->state = &pstate->base; 1218 } 1219 1220 #ifdef CONFIG_DEBUG_FS 1221 static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1222 { 1223 struct dpu_plane *pdpu = to_dpu_plane(plane); 1224 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1225 1226 if (!pdpu->is_rt_pipe) 1227 return; 1228 1229 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1230 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); 1231 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1232 } 1233 1234 static ssize_t _dpu_plane_danger_read(struct file *file, 1235 char __user *buff, size_t count, loff_t *ppos) 1236 { 1237 struct dpu_kms *kms = file->private_data; 1238 int len; 1239 char buf[40]; 1240 1241 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 1242 1243 return simple_read_from_buffer(buff, count, ppos, buf, len); 1244 } 1245 1246 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 1247 { 1248 struct drm_plane *plane; 1249 1250 drm_for_each_plane(plane, kms->dev) { 1251 if (plane->fb && plane->state) { 1252 dpu_plane_danger_signal_ctrl(plane, enable); 1253 DPU_DEBUG("plane:%d img:%dx%d ", 1254 plane->base.id, plane->fb->width, 1255 plane->fb->height); 1256 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 1257 plane->state->src_x >> 16, 1258 plane->state->src_y >> 16, 1259 plane->state->src_w >> 16, 1260 plane->state->src_h >> 16, 1261 plane->state->crtc_x, plane->state->crtc_y, 1262 plane->state->crtc_w, plane->state->crtc_h); 1263 } else { 1264 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 1265 } 1266 } 1267 } 1268 1269 static ssize_t _dpu_plane_danger_write(struct file *file, 1270 const char __user *user_buf, size_t count, loff_t *ppos) 1271 { 1272 struct dpu_kms *kms = file->private_data; 1273 int disable_panic; 1274 int ret; 1275 1276 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 1277 if (ret) 1278 return ret; 1279 1280 if (disable_panic) { 1281 /* Disable panic signal for all active pipes */ 1282 DPU_DEBUG("Disabling danger:\n"); 1283 _dpu_plane_set_danger_state(kms, false); 1284 kms->has_danger_ctrl = false; 1285 } else { 1286 /* Enable panic signal for all active pipes */ 1287 DPU_DEBUG("Enabling danger:\n"); 1288 kms->has_danger_ctrl = true; 1289 _dpu_plane_set_danger_state(kms, true); 1290 } 1291 1292 return count; 1293 } 1294 1295 static const struct file_operations dpu_plane_danger_enable = { 1296 .open = simple_open, 1297 .read = _dpu_plane_danger_read, 1298 .write = _dpu_plane_danger_write, 1299 }; 1300 1301 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1302 { 1303 struct dpu_plane *pdpu = to_dpu_plane(plane); 1304 struct dpu_kms *kms = _dpu_plane_get_kms(plane); 1305 const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap; 1306 const struct dpu_sspp_sub_blks *sblk = cfg->sblk; 1307 1308 /* create overall sub-directory for the pipe */ 1309 pdpu->debugfs_root = 1310 debugfs_create_dir(pdpu->pipe_name, 1311 plane->dev->primary->debugfs_root); 1312 1313 /* don't error check these */ 1314 debugfs_create_x32("features", 0600, 1315 pdpu->debugfs_root, &pdpu->features); 1316 1317 /* add register dump support */ 1318 dpu_debugfs_setup_regset32(&pdpu->debugfs_src, 1319 sblk->src_blk.base + cfg->base, 1320 sblk->src_blk.len, 1321 kms); 1322 dpu_debugfs_create_regset32("src_blk", 0400, 1323 pdpu->debugfs_root, &pdpu->debugfs_src); 1324 1325 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || 1326 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) { 1327 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler, 1328 sblk->scaler_blk.base + cfg->base, 1329 sblk->scaler_blk.len, 1330 kms); 1331 dpu_debugfs_create_regset32("scaler_blk", 0400, 1332 pdpu->debugfs_root, 1333 &pdpu->debugfs_scaler); 1334 debugfs_create_bool("default_scaling", 1335 0600, 1336 pdpu->debugfs_root, 1337 &pdpu->debugfs_default_scale); 1338 } 1339 1340 if (cfg->features & BIT(DPU_SSPP_CSC) || 1341 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) { 1342 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc, 1343 sblk->csc_blk.base + cfg->base, 1344 sblk->csc_blk.len, 1345 kms); 1346 dpu_debugfs_create_regset32("csc_blk", 0400, 1347 pdpu->debugfs_root, &pdpu->debugfs_csc); 1348 } 1349 1350 debugfs_create_u32("xin_id", 1351 0400, 1352 pdpu->debugfs_root, 1353 (u32 *) &cfg->xin_id); 1354 debugfs_create_u32("clk_ctrl", 1355 0400, 1356 pdpu->debugfs_root, 1357 (u32 *) &cfg->clk_ctrl); 1358 debugfs_create_x32("creq_vblank", 1359 0600, 1360 pdpu->debugfs_root, 1361 (u32 *) &sblk->creq_vblank); 1362 debugfs_create_x32("danger_vblank", 1363 0600, 1364 pdpu->debugfs_root, 1365 (u32 *) &sblk->danger_vblank); 1366 1367 debugfs_create_file("disable_danger", 1368 0600, 1369 pdpu->debugfs_root, 1370 kms, &dpu_plane_danger_enable); 1371 1372 return 0; 1373 } 1374 #else 1375 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1376 { 1377 return 0; 1378 } 1379 #endif 1380 1381 static int dpu_plane_late_register(struct drm_plane *plane) 1382 { 1383 return _dpu_plane_init_debugfs(plane); 1384 } 1385 1386 static void dpu_plane_early_unregister(struct drm_plane *plane) 1387 { 1388 struct dpu_plane *pdpu = to_dpu_plane(plane); 1389 1390 debugfs_remove_recursive(pdpu->debugfs_root); 1391 } 1392 1393 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1394 uint32_t format, uint64_t modifier) 1395 { 1396 if (modifier == DRM_FORMAT_MOD_LINEAR) 1397 return true; 1398 1399 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) { 1400 int i; 1401 for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) { 1402 if (format == qcom_compressed_supported_formats[i]) 1403 return true; 1404 } 1405 } 1406 1407 return false; 1408 } 1409 1410 static const struct drm_plane_funcs dpu_plane_funcs = { 1411 .update_plane = drm_atomic_helper_update_plane, 1412 .disable_plane = drm_atomic_helper_disable_plane, 1413 .destroy = dpu_plane_destroy, 1414 .reset = dpu_plane_reset, 1415 .atomic_duplicate_state = dpu_plane_duplicate_state, 1416 .atomic_destroy_state = dpu_plane_destroy_state, 1417 .late_register = dpu_plane_late_register, 1418 .early_unregister = dpu_plane_early_unregister, 1419 .format_mod_supported = dpu_plane_format_mod_supported, 1420 }; 1421 1422 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1423 .prepare_fb = dpu_plane_prepare_fb, 1424 .cleanup_fb = dpu_plane_cleanup_fb, 1425 .atomic_check = dpu_plane_atomic_check, 1426 .atomic_update = dpu_plane_atomic_update, 1427 }; 1428 1429 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) 1430 { 1431 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; 1432 } 1433 1434 bool is_dpu_plane_virtual(struct drm_plane *plane) 1435 { 1436 return plane ? to_dpu_plane(plane)->is_virtual : false; 1437 } 1438 1439 /* initialize plane */ 1440 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1441 uint32_t pipe, enum drm_plane_type type, 1442 unsigned long possible_crtcs, u32 master_plane_id) 1443 { 1444 struct drm_plane *plane = NULL, *master_plane = NULL; 1445 const uint32_t *format_list; 1446 struct dpu_plane *pdpu; 1447 struct msm_drm_private *priv = dev->dev_private; 1448 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1449 int zpos_max = DPU_ZPOS_MAX; 1450 uint32_t num_formats; 1451 int ret = -EINVAL; 1452 1453 /* create and zero local structure */ 1454 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1455 if (!pdpu) { 1456 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1457 ret = -ENOMEM; 1458 return ERR_PTR(ret); 1459 } 1460 1461 /* cache local stuff for later */ 1462 plane = &pdpu->base; 1463 pdpu->pipe = pipe; 1464 pdpu->is_virtual = (master_plane_id != 0); 1465 INIT_LIST_HEAD(&pdpu->mplane_list); 1466 master_plane = drm_plane_find(dev, NULL, master_plane_id); 1467 if (master_plane) { 1468 struct dpu_plane *mpdpu = to_dpu_plane(master_plane); 1469 1470 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list); 1471 } 1472 1473 /* initialize underlying h/w driver */ 1474 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, 1475 master_plane_id != 0); 1476 if (IS_ERR(pdpu->pipe_hw)) { 1477 DPU_ERROR("[%u]SSPP init failed\n", pipe); 1478 ret = PTR_ERR(pdpu->pipe_hw); 1479 goto clean_plane; 1480 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { 1481 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); 1482 goto clean_sspp; 1483 } 1484 1485 /* cache features mask for later */ 1486 pdpu->features = pdpu->pipe_hw->cap->features; 1487 pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk; 1488 if (!pdpu->pipe_sblk) { 1489 DPU_ERROR("[%u]invalid sblk\n", pipe); 1490 goto clean_sspp; 1491 } 1492 1493 if (pdpu->is_virtual) { 1494 format_list = pdpu->pipe_sblk->virt_format_list; 1495 num_formats = pdpu->pipe_sblk->virt_num_formats; 1496 } 1497 else { 1498 format_list = pdpu->pipe_sblk->format_list; 1499 num_formats = pdpu->pipe_sblk->num_formats; 1500 } 1501 1502 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1503 format_list, num_formats, 1504 supported_format_modifiers, type, NULL); 1505 if (ret) 1506 goto clean_sspp; 1507 1508 pdpu->catalog = kms->catalog; 1509 1510 if (kms->catalog->mixer_count && 1511 kms->catalog->mixer[0].sblk->maxblendstages) { 1512 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; 1513 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) 1514 zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; 1515 } 1516 1517 ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); 1518 if (ret) 1519 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1520 1521 drm_plane_enable_fb_damage_clips(plane); 1522 1523 /* success! finalize initialization */ 1524 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1525 1526 /* save user friendly pipe name for later */ 1527 snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id); 1528 1529 mutex_init(&pdpu->lock); 1530 1531 DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name, 1532 pipe, plane->base.id, master_plane_id); 1533 return plane; 1534 1535 clean_sspp: 1536 if (pdpu && pdpu->pipe_hw) 1537 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1538 clean_plane: 1539 kfree(pdpu); 1540 return ERR_PTR(ret); 1541 } 1542