1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_damage_helper.h> 14 #include <drm/drm_atomic_uapi.h> 15 16 #include "msm_drv.h" 17 #include "dpu_kms.h" 18 #include "dpu_formats.h" 19 #include "dpu_hw_sspp.h" 20 #include "dpu_hw_catalog_format.h" 21 #include "dpu_trace.h" 22 #include "dpu_crtc.h" 23 #include "dpu_vbif.h" 24 #include "dpu_plane.h" 25 26 #define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\ 27 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 28 29 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 30 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 31 32 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 33 #define PHASE_STEP_SHIFT 21 34 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 35 #define PHASE_RESIDUAL 15 36 37 #define SHARP_STRENGTH_DEFAULT 32 38 #define SHARP_EDGE_THR_DEFAULT 112 39 #define SHARP_SMOOTH_THR_DEFAULT 8 40 #define SHARP_NOISE_THR_DEFAULT 2 41 42 #define DPU_NAME_SIZE 12 43 44 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 45 #define DPU_ZPOS_MAX 255 46 47 /* multirect rect index */ 48 enum { 49 R0, 50 R1, 51 R_MAX 52 }; 53 54 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 55 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 56 57 #define DEFAULT_REFRESH_RATE 60 58 59 /** 60 * enum dpu_plane_qos - Different qos configurations for each pipe 61 * 62 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. 63 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. 64 * this configuration is mutually exclusive from VBLANK_CTRL. 65 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. 66 */ 67 enum dpu_plane_qos { 68 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), 69 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), 70 DPU_PLANE_QOS_PANIC_CTRL = BIT(2), 71 }; 72 73 /* 74 * struct dpu_plane - local dpu plane structure 75 * @aspace: address space pointer 76 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 77 * @mplane_list: List of multirect planes of the same pipe 78 * @catalog: Points to dpu catalog structure 79 * @revalidate: force revalidation of all the plane properties 80 */ 81 struct dpu_plane { 82 struct drm_plane base; 83 84 struct mutex lock; 85 86 enum dpu_sspp pipe; 87 uint32_t features; /* capabilities from catalog */ 88 89 struct dpu_hw_pipe *pipe_hw; 90 struct dpu_hw_pipe_cfg pipe_cfg; 91 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; 92 uint32_t color_fill; 93 bool is_error; 94 bool is_rt_pipe; 95 bool is_virtual; 96 struct list_head mplane_list; 97 struct dpu_mdss_cfg *catalog; 98 99 struct dpu_csc_cfg *csc_ptr; 100 101 const struct dpu_sspp_sub_blks *pipe_sblk; 102 char pipe_name[DPU_NAME_SIZE]; 103 104 /* debugfs related stuff */ 105 struct dentry *debugfs_root; 106 struct dpu_debugfs_regset32 debugfs_src; 107 struct dpu_debugfs_regset32 debugfs_scaler; 108 struct dpu_debugfs_regset32 debugfs_csc; 109 bool debugfs_default_scale; 110 }; 111 112 static const uint64_t supported_format_modifiers[] = { 113 DRM_FORMAT_MOD_QCOM_COMPRESSED, 114 DRM_FORMAT_MOD_LINEAR, 115 DRM_FORMAT_MOD_INVALID 116 }; 117 118 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 119 120 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 121 { 122 struct msm_drm_private *priv = plane->dev->dev_private; 123 124 return to_dpu_kms(priv->kms); 125 } 126 127 /** 128 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 129 * @plane: Pointer to drm plane 130 * @fmt: Pointer to source buffer format 131 * @src_wdith: width of source buffer 132 * Return: fill level corresponding to the source buffer/format or 0 if error 133 */ 134 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 135 const struct dpu_format *fmt, u32 src_width) 136 { 137 struct dpu_plane *pdpu, *tmp; 138 struct dpu_plane_state *pstate; 139 u32 fixed_buff_size; 140 u32 total_fl; 141 142 if (!fmt || !plane->state || !src_width || !fmt->bpp) { 143 DPU_ERROR("invalid arguments\n"); 144 return 0; 145 } 146 147 pdpu = to_dpu_plane(plane); 148 pstate = to_dpu_plane_state(plane->state); 149 fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size; 150 151 list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) { 152 if (!tmp->base.state->visible) 153 continue; 154 DPU_DEBUG("plane%d/%d src_width:%d/%d\n", 155 pdpu->base.base.id, tmp->base.base.id, 156 src_width, 157 drm_rect_width(&tmp->pipe_cfg.src_rect)); 158 src_width = max_t(u32, src_width, 159 drm_rect_width(&tmp->pipe_cfg.src_rect)); 160 } 161 162 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 163 if (fmt->chroma_sample == DPU_CHROMA_420) { 164 /* NV12 */ 165 total_fl = (fixed_buff_size / 2) / 166 ((src_width + 32) * fmt->bpp); 167 } else { 168 /* non NV12 */ 169 total_fl = (fixed_buff_size / 2) * 2 / 170 ((src_width + 32) * fmt->bpp); 171 } 172 } else { 173 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 174 total_fl = (fixed_buff_size / 2) * 2 / 175 ((src_width + 32) * fmt->bpp); 176 } else { 177 total_fl = (fixed_buff_size) * 2 / 178 ((src_width + 32) * fmt->bpp); 179 } 180 } 181 182 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n", 183 plane->base.id, pdpu->pipe - SSPP_VIG0, 184 (char *)&fmt->base.pixel_format, 185 src_width, total_fl); 186 187 return total_fl; 188 } 189 190 /** 191 * _dpu_plane_get_qos_lut - get LUT mapping based on fill level 192 * @tbl: Pointer to LUT table 193 * @total_fl: fill level 194 * Return: LUT setting corresponding to the fill level 195 */ 196 static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, 197 u32 total_fl) 198 { 199 int i; 200 201 if (!tbl || !tbl->nentry || !tbl->entries) 202 return 0; 203 204 for (i = 0; i < tbl->nentry; i++) 205 if (total_fl <= tbl->entries[i].fl) 206 return tbl->entries[i].lut; 207 208 /* if last fl is zero, use as default */ 209 if (!tbl->entries[i-1].fl) 210 return tbl->entries[i-1].lut; 211 212 return 0; 213 } 214 215 /** 216 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 217 * @plane: Pointer to drm plane 218 * @fb: Pointer to framebuffer associated with the given plane 219 */ 220 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 221 struct drm_framebuffer *fb) 222 { 223 struct dpu_plane *pdpu = to_dpu_plane(plane); 224 const struct dpu_format *fmt = NULL; 225 u64 qos_lut; 226 u32 total_fl = 0, lut_usage; 227 228 if (!pdpu->is_rt_pipe) { 229 lut_usage = DPU_QOS_LUT_USAGE_NRT; 230 } else { 231 fmt = dpu_get_dpu_format_ext( 232 fb->format->format, 233 fb->modifier); 234 total_fl = _dpu_plane_calc_fill_level(plane, fmt, 235 drm_rect_width(&pdpu->pipe_cfg.src_rect)); 236 237 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 238 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 239 else 240 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 241 } 242 243 qos_lut = _dpu_plane_get_qos_lut( 244 &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); 245 246 pdpu->pipe_qos_cfg.creq_lut = qos_lut; 247 248 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, 249 (fmt) ? fmt->base.pixel_format : 0, 250 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); 251 252 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 253 plane->base.id, 254 pdpu->pipe - SSPP_VIG0, 255 fmt ? (char *)&fmt->base.pixel_format : NULL, 256 pdpu->is_rt_pipe, total_fl, qos_lut); 257 258 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg); 259 } 260 261 /** 262 * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane 263 * @plane: Pointer to drm plane 264 * @fb: Pointer to framebuffer associated with the given plane 265 */ 266 static void _dpu_plane_set_danger_lut(struct drm_plane *plane, 267 struct drm_framebuffer *fb) 268 { 269 struct dpu_plane *pdpu = to_dpu_plane(plane); 270 const struct dpu_format *fmt = NULL; 271 u32 danger_lut, safe_lut; 272 273 if (!pdpu->is_rt_pipe) { 274 danger_lut = pdpu->catalog->perf.danger_lut_tbl 275 [DPU_QOS_LUT_USAGE_NRT]; 276 safe_lut = pdpu->catalog->perf.safe_lut_tbl 277 [DPU_QOS_LUT_USAGE_NRT]; 278 } else { 279 fmt = dpu_get_dpu_format_ext( 280 fb->format->format, 281 fb->modifier); 282 283 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { 284 danger_lut = pdpu->catalog->perf.danger_lut_tbl 285 [DPU_QOS_LUT_USAGE_LINEAR]; 286 safe_lut = pdpu->catalog->perf.safe_lut_tbl 287 [DPU_QOS_LUT_USAGE_LINEAR]; 288 } else { 289 danger_lut = pdpu->catalog->perf.danger_lut_tbl 290 [DPU_QOS_LUT_USAGE_MACROTILE]; 291 safe_lut = pdpu->catalog->perf.safe_lut_tbl 292 [DPU_QOS_LUT_USAGE_MACROTILE]; 293 } 294 } 295 296 pdpu->pipe_qos_cfg.danger_lut = danger_lut; 297 pdpu->pipe_qos_cfg.safe_lut = safe_lut; 298 299 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 300 (fmt) ? fmt->base.pixel_format : 0, 301 (fmt) ? fmt->fetch_mode : 0, 302 pdpu->pipe_qos_cfg.danger_lut, 303 pdpu->pipe_qos_cfg.safe_lut); 304 305 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 306 plane->base.id, 307 pdpu->pipe - SSPP_VIG0, 308 fmt ? (char *)&fmt->base.pixel_format : NULL, 309 fmt ? fmt->fetch_mode : -1, 310 pdpu->pipe_qos_cfg.danger_lut, 311 pdpu->pipe_qos_cfg.safe_lut); 312 313 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, 314 &pdpu->pipe_qos_cfg); 315 } 316 317 /** 318 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 319 * @plane: Pointer to drm plane 320 * @enable: true to enable QoS control 321 * @flags: QoS control mode (enum dpu_plane_qos) 322 */ 323 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 324 bool enable, u32 flags) 325 { 326 struct dpu_plane *pdpu = to_dpu_plane(plane); 327 328 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { 329 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; 330 pdpu->pipe_qos_cfg.danger_vblank = 331 pdpu->pipe_sblk->danger_vblank; 332 pdpu->pipe_qos_cfg.vblank_en = enable; 333 } 334 335 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { 336 /* this feature overrules previous VBLANK_CTRL */ 337 pdpu->pipe_qos_cfg.vblank_en = false; 338 pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ 339 } 340 341 if (flags & DPU_PLANE_QOS_PANIC_CTRL) 342 pdpu->pipe_qos_cfg.danger_safe_en = enable; 343 344 if (!pdpu->is_rt_pipe) { 345 pdpu->pipe_qos_cfg.vblank_en = false; 346 pdpu->pipe_qos_cfg.danger_safe_en = false; 347 } 348 349 DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", 350 plane->base.id, 351 pdpu->pipe - SSPP_VIG0, 352 pdpu->pipe_qos_cfg.danger_safe_en, 353 pdpu->pipe_qos_cfg.vblank_en, 354 pdpu->pipe_qos_cfg.creq_vblank, 355 pdpu->pipe_qos_cfg.danger_vblank, 356 pdpu->is_rt_pipe); 357 358 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, 359 &pdpu->pipe_qos_cfg); 360 } 361 362 /** 363 * _dpu_plane_set_ot_limit - set OT limit for the given plane 364 * @plane: Pointer to drm plane 365 * @crtc: Pointer to drm crtc 366 */ 367 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 368 struct drm_crtc *crtc) 369 { 370 struct dpu_plane *pdpu = to_dpu_plane(plane); 371 struct dpu_vbif_set_ot_params ot_params; 372 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 373 374 memset(&ot_params, 0, sizeof(ot_params)); 375 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; 376 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; 377 ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect); 378 ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 379 ot_params.is_wfd = !pdpu->is_rt_pipe; 380 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); 381 ot_params.vbif_idx = VBIF_RT; 382 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 383 ot_params.rd = true; 384 385 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 386 } 387 388 /** 389 * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane 390 * @plane: Pointer to drm plane 391 */ 392 static void _dpu_plane_set_qos_remap(struct drm_plane *plane) 393 { 394 struct dpu_plane *pdpu = to_dpu_plane(plane); 395 struct dpu_vbif_set_qos_params qos_params; 396 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 397 398 memset(&qos_params, 0, sizeof(qos_params)); 399 qos_params.vbif_idx = VBIF_RT; 400 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 401 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; 402 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; 403 qos_params.is_rt = pdpu->is_rt_pipe; 404 405 DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 406 plane->base.id, qos_params.num, 407 qos_params.vbif_idx, 408 qos_params.xin_id, qos_params.is_rt, 409 qos_params.clk_ctrl); 410 411 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 412 } 413 414 static void _dpu_plane_set_scanout(struct drm_plane *plane, 415 struct dpu_plane_state *pstate, 416 struct dpu_hw_pipe_cfg *pipe_cfg, 417 struct drm_framebuffer *fb) 418 { 419 struct dpu_plane *pdpu = to_dpu_plane(plane); 420 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 421 struct msm_gem_address_space *aspace = kms->base.aspace; 422 int ret; 423 424 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); 425 if (ret == -EAGAIN) 426 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); 427 else if (ret) 428 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 429 else if (pdpu->pipe_hw->ops.setup_sourceaddress) { 430 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, 431 &pipe_cfg->layout, 432 pstate->multirect_index); 433 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, 434 pstate->multirect_index); 435 } 436 } 437 438 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 439 struct dpu_plane_state *pstate, 440 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 441 struct dpu_hw_scaler3_cfg *scale_cfg, 442 const struct dpu_format *fmt, 443 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 444 { 445 uint32_t i; 446 447 memset(scale_cfg, 0, sizeof(*scale_cfg)); 448 memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext)); 449 450 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 451 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 452 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 453 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 454 455 456 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 457 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 458 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 459 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 460 461 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 462 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 463 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 464 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 465 466 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 467 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 468 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 469 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 470 471 for (i = 0; i < DPU_MAX_PLANES; i++) { 472 scale_cfg->src_width[i] = src_w; 473 scale_cfg->src_height[i] = src_h; 474 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 475 scale_cfg->src_width[i] /= chroma_subsmpl_h; 476 scale_cfg->src_height[i] /= chroma_subsmpl_v; 477 } 478 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 479 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 480 pstate->pixel_ext.num_ext_pxls_top[i] = 481 scale_cfg->src_height[i]; 482 pstate->pixel_ext.num_ext_pxls_left[i] = 483 scale_cfg->src_width[i]; 484 } 485 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 486 && (src_w == dst_w)) 487 return; 488 489 scale_cfg->dst_width = dst_w; 490 scale_cfg->dst_height = dst_h; 491 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 492 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 493 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 494 scale_cfg->lut_flag = 0; 495 scale_cfg->blend_cfg = 1; 496 scale_cfg->enable = 1; 497 } 498 499 static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) 500 { 501 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 502 { 503 /* S15.16 format */ 504 0x00012A00, 0x00000000, 0x00019880, 505 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 506 0x00012A00, 0x00020480, 0x00000000, 507 }, 508 /* signed bias */ 509 { 0xfff0, 0xff80, 0xff80,}, 510 { 0x0, 0x0, 0x0,}, 511 /* unsigned clamp */ 512 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 513 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 514 }; 515 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 516 { 517 /* S15.16 format */ 518 0x00012A00, 0x00000000, 0x00019880, 519 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 520 0x00012A00, 0x00020480, 0x00000000, 521 }, 522 /* signed bias */ 523 { 0xffc0, 0xfe00, 0xfe00,}, 524 { 0x0, 0x0, 0x0,}, 525 /* unsigned clamp */ 526 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 527 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 528 }; 529 530 if (!pdpu) { 531 DPU_ERROR("invalid plane\n"); 532 return; 533 } 534 535 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features) 536 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L; 537 else 538 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L; 539 540 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 541 pdpu->csc_ptr->csc_mv[0], 542 pdpu->csc_ptr->csc_mv[1], 543 pdpu->csc_ptr->csc_mv[2]); 544 } 545 546 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 547 struct dpu_plane_state *pstate, 548 const struct dpu_format *fmt, bool color_fill) 549 { 550 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 551 552 /* don't chroma subsample if decimating */ 553 /* update scaler. calculate default config for QSEED3 */ 554 _dpu_plane_setup_scaler3(pdpu, pstate, 555 drm_rect_width(&pdpu->pipe_cfg.src_rect), 556 drm_rect_height(&pdpu->pipe_cfg.src_rect), 557 drm_rect_width(&pdpu->pipe_cfg.dst_rect), 558 drm_rect_height(&pdpu->pipe_cfg.dst_rect), 559 &pstate->scaler3_cfg, fmt, 560 info->hsub, info->vsub); 561 } 562 563 /** 564 * _dpu_plane_color_fill - enables color fill on plane 565 * @pdpu: Pointer to DPU plane object 566 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 567 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 568 * Returns: 0 on success 569 */ 570 static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 571 uint32_t color, uint32_t alpha) 572 { 573 const struct dpu_format *fmt; 574 const struct drm_plane *plane = &pdpu->base; 575 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 576 577 DPU_DEBUG_PLANE(pdpu, "\n"); 578 579 /* 580 * select fill format to match user property expectation, 581 * h/w only supports RGB variants 582 */ 583 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 584 585 /* update sspp */ 586 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { 587 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, 588 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), 589 pstate->multirect_index); 590 591 /* override scaler/decimation if solid fill */ 592 pdpu->pipe_cfg.src_rect.x1 = 0; 593 pdpu->pipe_cfg.src_rect.y1 = 0; 594 pdpu->pipe_cfg.src_rect.x2 = 595 drm_rect_width(&pdpu->pipe_cfg.dst_rect); 596 pdpu->pipe_cfg.src_rect.y2 = 597 drm_rect_height(&pdpu->pipe_cfg.dst_rect); 598 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true); 599 600 if (pdpu->pipe_hw->ops.setup_format) 601 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, 602 fmt, DPU_SSPP_SOLID_FILL, 603 pstate->multirect_index); 604 605 if (pdpu->pipe_hw->ops.setup_rects) 606 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 607 &pdpu->pipe_cfg, 608 pstate->multirect_index); 609 610 if (pdpu->pipe_hw->ops.setup_pe) 611 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 612 &pstate->pixel_ext); 613 614 if (pdpu->pipe_hw->ops.setup_scaler && 615 pstate->multirect_index != DPU_SSPP_RECT_1) 616 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 617 &pdpu->pipe_cfg, &pstate->pixel_ext, 618 &pstate->scaler3_cfg); 619 } 620 621 return 0; 622 } 623 624 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) 625 { 626 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); 627 628 pstate->multirect_index = DPU_SSPP_RECT_SOLO; 629 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 630 } 631 632 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) 633 { 634 struct dpu_plane_state *pstate[R_MAX]; 635 const struct drm_plane_state *drm_state[R_MAX]; 636 struct drm_rect src[R_MAX], dst[R_MAX]; 637 struct dpu_plane *dpu_plane[R_MAX]; 638 const struct dpu_format *fmt[R_MAX]; 639 int i, buffer_lines; 640 unsigned int max_tile_height = 1; 641 bool parallel_fetch_qualified = true; 642 bool has_tiled_rect = false; 643 644 for (i = 0; i < R_MAX; i++) { 645 const struct msm_format *msm_fmt; 646 647 drm_state[i] = i ? plane->r1 : plane->r0; 648 msm_fmt = msm_framebuffer_format(drm_state[i]->fb); 649 fmt[i] = to_dpu_format(msm_fmt); 650 651 if (DPU_FORMAT_IS_UBWC(fmt[i])) { 652 has_tiled_rect = true; 653 if (fmt[i]->tile_height > max_tile_height) 654 max_tile_height = fmt[i]->tile_height; 655 } 656 } 657 658 for (i = 0; i < R_MAX; i++) { 659 int width_threshold; 660 661 pstate[i] = to_dpu_plane_state(drm_state[i]); 662 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); 663 664 if (pstate[i] == NULL) { 665 DPU_ERROR("DPU plane state of plane id %d is NULL\n", 666 drm_state[i]->plane->base.id); 667 return -EINVAL; 668 } 669 670 src[i].x1 = drm_state[i]->src_x >> 16; 671 src[i].y1 = drm_state[i]->src_y >> 16; 672 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); 673 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); 674 675 dst[i] = drm_plane_state_dest(drm_state[i]); 676 677 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || 678 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { 679 DPU_ERROR_PLANE(dpu_plane[i], 680 "scaling is not supported in multirect mode\n"); 681 return -EINVAL; 682 } 683 684 if (DPU_FORMAT_IS_YUV(fmt[i])) { 685 DPU_ERROR_PLANE(dpu_plane[i], 686 "Unsupported format for multirect mode\n"); 687 return -EINVAL; 688 } 689 690 /** 691 * SSPP PD_MEM is split half - one for each RECT. 692 * Tiled formats need 5 lines of buffering while fetching 693 * whereas linear formats need only 2 lines. 694 * So we cannot support more than half of the supported SSPP 695 * width for tiled formats. 696 */ 697 width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth; 698 if (has_tiled_rect) 699 width_threshold /= 2; 700 701 if (parallel_fetch_qualified && 702 drm_rect_width(&src[i]) > width_threshold) 703 parallel_fetch_qualified = false; 704 705 } 706 707 /* Validate RECT's and set the mode */ 708 709 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ 710 if (parallel_fetch_qualified) { 711 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 712 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 713 714 goto done; 715 } 716 717 /* TIME_MX Mode */ 718 buffer_lines = 2 * max_tile_height; 719 720 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || 721 dst[R0].y1 >= dst[R1].y2 + buffer_lines) { 722 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 723 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 724 } else { 725 DPU_ERROR( 726 "No multirect mode possible for the planes (%d - %d)\n", 727 drm_state[R0]->plane->base.id, 728 drm_state[R1]->plane->base.id); 729 return -EINVAL; 730 } 731 732 done: 733 if (dpu_plane[R0]->is_virtual) { 734 pstate[R0]->multirect_index = DPU_SSPP_RECT_1; 735 pstate[R1]->multirect_index = DPU_SSPP_RECT_0; 736 } else { 737 pstate[R0]->multirect_index = DPU_SSPP_RECT_0; 738 pstate[R1]->multirect_index = DPU_SSPP_RECT_1; 739 }; 740 741 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", 742 pstate[R0]->multirect_mode, pstate[R0]->multirect_index); 743 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", 744 pstate[R1]->multirect_mode, pstate[R1]->multirect_index); 745 return 0; 746 } 747 748 /** 749 * dpu_plane_get_ctl_flush - get control flush for the given plane 750 * @plane: Pointer to drm plane structure 751 * @ctl: Pointer to hardware control driver 752 * @flush_sspp: Pointer to sspp flush control word 753 */ 754 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, 755 u32 *flush_sspp) 756 { 757 *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane)); 758 } 759 760 static int dpu_plane_prepare_fb(struct drm_plane *plane, 761 struct drm_plane_state *new_state) 762 { 763 struct drm_framebuffer *fb = new_state->fb; 764 struct dpu_plane *pdpu = to_dpu_plane(plane); 765 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 766 struct dpu_hw_fmt_layout layout; 767 struct drm_gem_object *obj; 768 struct dma_fence *fence; 769 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 770 int ret; 771 772 if (!new_state->fb) 773 return 0; 774 775 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 776 777 /* cache aspace */ 778 pstate->aspace = kms->base.aspace; 779 780 /* 781 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 782 * we can use msm_atomic_prepare_fb() instead of doing the 783 * implicit fence and fb prepare by hand here. 784 */ 785 obj = msm_framebuffer_bo(new_state->fb, 0); 786 fence = reservation_object_get_excl_rcu(obj->resv); 787 if (fence) 788 drm_atomic_set_fence_for_plane(new_state, fence); 789 790 if (pstate->aspace) { 791 ret = msm_framebuffer_prepare(new_state->fb, 792 pstate->aspace); 793 if (ret) { 794 DPU_ERROR("failed to prepare framebuffer\n"); 795 return ret; 796 } 797 } 798 799 /* validate framebuffer layout before commit */ 800 ret = dpu_format_populate_layout(pstate->aspace, 801 new_state->fb, &layout); 802 if (ret) { 803 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 804 return ret; 805 } 806 807 return 0; 808 } 809 810 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 811 struct drm_plane_state *old_state) 812 { 813 struct dpu_plane *pdpu = to_dpu_plane(plane); 814 struct dpu_plane_state *old_pstate; 815 816 if (!old_state || !old_state->fb) 817 return; 818 819 old_pstate = to_dpu_plane_state(old_state); 820 821 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 822 823 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace); 824 } 825 826 static bool dpu_plane_validate_src(struct drm_rect *src, 827 struct drm_rect *fb_rect, 828 uint32_t min_src_size) 829 { 830 /* Ensure fb size is supported */ 831 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || 832 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) 833 return false; 834 835 /* Ensure src rect is above the minimum size */ 836 if (drm_rect_width(src) < min_src_size || 837 drm_rect_height(src) < min_src_size) 838 return false; 839 840 /* Ensure src is fully encapsulated in fb */ 841 return drm_rect_intersect(fb_rect, src) && 842 drm_rect_equals(fb_rect, src); 843 } 844 845 static int dpu_plane_atomic_check(struct drm_plane *plane, 846 struct drm_plane_state *state) 847 { 848 int ret = 0, min_scale; 849 struct dpu_plane *pdpu = to_dpu_plane(plane); 850 const struct drm_crtc_state *crtc_state = NULL; 851 const struct dpu_format *fmt; 852 struct drm_rect src, dst, fb_rect = { 0 }; 853 uint32_t min_src_size, max_linewidth; 854 855 if (state->crtc) 856 crtc_state = drm_atomic_get_new_crtc_state(state->state, 857 state->crtc); 858 859 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale); 860 ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale, 861 pdpu->pipe_sblk->maxupscale << 16, 862 true, true); 863 if (ret) { 864 DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 865 return ret; 866 } 867 if (!state->visible) 868 return 0; 869 870 src.x1 = state->src_x >> 16; 871 src.y1 = state->src_y >> 16; 872 src.x2 = src.x1 + (state->src_w >> 16); 873 src.y2 = src.y1 + (state->src_h >> 16); 874 875 dst = drm_plane_state_dest(state); 876 877 fb_rect.x2 = state->fb->width; 878 fb_rect.y2 = state->fb->height; 879 880 max_linewidth = pdpu->pipe_sblk->common->maxlinewidth; 881 882 fmt = to_dpu_format(msm_framebuffer_format(state->fb)); 883 884 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 885 886 if (DPU_FORMAT_IS_YUV(fmt) && 887 (!(pdpu->features & DPU_SSPP_SCALER) || 888 !(pdpu->features & (BIT(DPU_SSPP_CSC) 889 | BIT(DPU_SSPP_CSC_10BIT))))) { 890 DPU_ERROR_PLANE(pdpu, 891 "plane doesn't have scaler/csc for yuv\n"); 892 return -EINVAL; 893 894 /* check src bounds */ 895 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { 896 DPU_ERROR_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 897 DRM_RECT_ARG(&src)); 898 return -E2BIG; 899 900 /* valid yuv image */ 901 } else if (DPU_FORMAT_IS_YUV(fmt) && 902 (src.x1 & 0x1 || src.y1 & 0x1 || 903 drm_rect_width(&src) & 0x1 || 904 drm_rect_height(&src) & 0x1)) { 905 DPU_ERROR_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 906 DRM_RECT_ARG(&src)); 907 return -EINVAL; 908 909 /* min dst support */ 910 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { 911 DPU_ERROR_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 912 DRM_RECT_ARG(&dst)); 913 return -EINVAL; 914 915 /* check decimated source width */ 916 } else if (drm_rect_width(&src) > max_linewidth) { 917 DPU_ERROR_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 918 DRM_RECT_ARG(&src), max_linewidth); 919 return -E2BIG; 920 } 921 922 return 0; 923 } 924 925 void dpu_plane_flush(struct drm_plane *plane) 926 { 927 struct dpu_plane *pdpu; 928 struct dpu_plane_state *pstate; 929 930 if (!plane || !plane->state) { 931 DPU_ERROR("invalid plane\n"); 932 return; 933 } 934 935 pdpu = to_dpu_plane(plane); 936 pstate = to_dpu_plane_state(plane->state); 937 938 /* 939 * These updates have to be done immediately before the plane flush 940 * timing, and may not be moved to the atomic_update/mode_set functions. 941 */ 942 if (pdpu->is_error) 943 /* force white frame with 100% alpha pipe output on error */ 944 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 945 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 946 /* force 100% alpha */ 947 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 948 else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc) 949 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr); 950 951 /* flag h/w flush complete */ 952 if (plane->state) 953 pstate->pending = false; 954 } 955 956 /** 957 * dpu_plane_set_error: enable/disable error condition 958 * @plane: pointer to drm_plane structure 959 */ 960 void dpu_plane_set_error(struct drm_plane *plane, bool error) 961 { 962 struct dpu_plane *pdpu; 963 964 if (!plane) 965 return; 966 967 pdpu = to_dpu_plane(plane); 968 pdpu->is_error = error; 969 } 970 971 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 972 { 973 uint32_t src_flags; 974 struct dpu_plane *pdpu = to_dpu_plane(plane); 975 struct drm_plane_state *state = plane->state; 976 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 977 struct drm_crtc *crtc = state->crtc; 978 struct drm_framebuffer *fb = state->fb; 979 const struct dpu_format *fmt = 980 to_dpu_format(msm_framebuffer_format(fb)); 981 982 memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg)); 983 984 _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb); 985 986 pstate->pending = true; 987 988 pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 989 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 990 991 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 992 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 993 crtc->base.id, DRM_RECT_ARG(&state->dst), 994 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 995 996 pdpu->pipe_cfg.src_rect = state->src; 997 998 /* state->src is 16.16, src_rect is not */ 999 pdpu->pipe_cfg.src_rect.x1 >>= 16; 1000 pdpu->pipe_cfg.src_rect.x2 >>= 16; 1001 pdpu->pipe_cfg.src_rect.y1 >>= 16; 1002 pdpu->pipe_cfg.src_rect.y2 >>= 16; 1003 1004 pdpu->pipe_cfg.dst_rect = state->dst; 1005 1006 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false); 1007 1008 /* override for color fill */ 1009 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1010 /* skip remaining processing on color fill */ 1011 return; 1012 } 1013 1014 if (pdpu->pipe_hw->ops.setup_rects) { 1015 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 1016 &pdpu->pipe_cfg, 1017 pstate->multirect_index); 1018 } 1019 1020 if (pdpu->pipe_hw->ops.setup_pe && 1021 (pstate->multirect_index != DPU_SSPP_RECT_1)) 1022 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 1023 &pstate->pixel_ext); 1024 1025 /** 1026 * when programmed in multirect mode, scalar block will be 1027 * bypassed. Still we need to update alpha and bitwidth 1028 * ONLY for RECT0 1029 */ 1030 if (pdpu->pipe_hw->ops.setup_scaler && 1031 pstate->multirect_index != DPU_SSPP_RECT_1) 1032 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 1033 &pdpu->pipe_cfg, &pstate->pixel_ext, 1034 &pstate->scaler3_cfg); 1035 1036 if (pdpu->pipe_hw->ops.setup_multirect) 1037 pdpu->pipe_hw->ops.setup_multirect( 1038 pdpu->pipe_hw, 1039 pstate->multirect_index, 1040 pstate->multirect_mode); 1041 1042 if (pdpu->pipe_hw->ops.setup_format) { 1043 src_flags = 0x0; 1044 1045 /* update format */ 1046 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, 1047 pstate->multirect_index); 1048 1049 if (pdpu->pipe_hw->ops.setup_cdp) { 1050 struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg; 1051 1052 memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg)); 1053 1054 cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg 1055 [DPU_PERF_CDP_USAGE_RT].rd_enable; 1056 cdp_cfg->ubwc_meta_enable = 1057 DPU_FORMAT_IS_UBWC(fmt); 1058 cdp_cfg->tile_amortize_enable = 1059 DPU_FORMAT_IS_UBWC(fmt) || 1060 DPU_FORMAT_IS_TILE(fmt); 1061 cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; 1062 1063 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg); 1064 } 1065 1066 /* update csc */ 1067 if (DPU_FORMAT_IS_YUV(fmt)) 1068 _dpu_plane_setup_csc(pdpu); 1069 else 1070 pdpu->csc_ptr = 0; 1071 } 1072 1073 _dpu_plane_set_qos_lut(plane, fb); 1074 _dpu_plane_set_danger_lut(plane, fb); 1075 1076 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 1077 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); 1078 _dpu_plane_set_ot_limit(plane, crtc); 1079 } 1080 1081 _dpu_plane_set_qos_remap(plane); 1082 } 1083 1084 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1085 { 1086 struct dpu_plane *pdpu = to_dpu_plane(plane); 1087 struct drm_plane_state *state = plane->state; 1088 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1089 1090 trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane), 1091 pstate->multirect_mode); 1092 1093 pstate->pending = true; 1094 1095 if (is_dpu_plane_virtual(plane) && 1096 pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect) 1097 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw, 1098 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE); 1099 } 1100 1101 static void dpu_plane_atomic_update(struct drm_plane *plane, 1102 struct drm_plane_state *old_state) 1103 { 1104 struct dpu_plane *pdpu = to_dpu_plane(plane); 1105 struct drm_plane_state *state = plane->state; 1106 1107 pdpu->is_error = false; 1108 1109 DPU_DEBUG_PLANE(pdpu, "\n"); 1110 1111 if (!state->visible) { 1112 _dpu_plane_atomic_disable(plane); 1113 } else { 1114 dpu_plane_sspp_atomic_update(plane); 1115 } 1116 } 1117 1118 void dpu_plane_restore(struct drm_plane *plane) 1119 { 1120 struct dpu_plane *pdpu; 1121 1122 if (!plane || !plane->state) { 1123 DPU_ERROR("invalid plane\n"); 1124 return; 1125 } 1126 1127 pdpu = to_dpu_plane(plane); 1128 1129 DPU_DEBUG_PLANE(pdpu, "\n"); 1130 1131 /* last plane state is same as current state */ 1132 dpu_plane_atomic_update(plane, plane->state); 1133 } 1134 1135 static void dpu_plane_destroy(struct drm_plane *plane) 1136 { 1137 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1138 1139 DPU_DEBUG_PLANE(pdpu, "\n"); 1140 1141 if (pdpu) { 1142 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1143 1144 mutex_destroy(&pdpu->lock); 1145 1146 /* this will destroy the states as well */ 1147 drm_plane_cleanup(plane); 1148 1149 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1150 1151 kfree(pdpu); 1152 } 1153 } 1154 1155 static void dpu_plane_destroy_state(struct drm_plane *plane, 1156 struct drm_plane_state *state) 1157 { 1158 __drm_atomic_helper_plane_destroy_state(state); 1159 kfree(to_dpu_plane_state(state)); 1160 } 1161 1162 static struct drm_plane_state * 1163 dpu_plane_duplicate_state(struct drm_plane *plane) 1164 { 1165 struct dpu_plane *pdpu; 1166 struct dpu_plane_state *pstate; 1167 struct dpu_plane_state *old_state; 1168 1169 if (!plane) { 1170 DPU_ERROR("invalid plane\n"); 1171 return NULL; 1172 } else if (!plane->state) { 1173 DPU_ERROR("invalid plane state\n"); 1174 return NULL; 1175 } 1176 1177 old_state = to_dpu_plane_state(plane->state); 1178 pdpu = to_dpu_plane(plane); 1179 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1180 if (!pstate) { 1181 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1182 return NULL; 1183 } 1184 1185 DPU_DEBUG_PLANE(pdpu, "\n"); 1186 1187 pstate->pending = false; 1188 1189 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1190 1191 return &pstate->base; 1192 } 1193 1194 static void dpu_plane_reset(struct drm_plane *plane) 1195 { 1196 struct dpu_plane *pdpu; 1197 struct dpu_plane_state *pstate; 1198 1199 if (!plane) { 1200 DPU_ERROR("invalid plane\n"); 1201 return; 1202 } 1203 1204 pdpu = to_dpu_plane(plane); 1205 DPU_DEBUG_PLANE(pdpu, "\n"); 1206 1207 /* remove previous state, if present */ 1208 if (plane->state) { 1209 dpu_plane_destroy_state(plane, plane->state); 1210 plane->state = 0; 1211 } 1212 1213 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1214 if (!pstate) { 1215 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1216 return; 1217 } 1218 1219 pstate->base.plane = plane; 1220 1221 plane->state = &pstate->base; 1222 } 1223 1224 #ifdef CONFIG_DEBUG_FS 1225 static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1226 { 1227 struct dpu_plane *pdpu = to_dpu_plane(plane); 1228 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1229 1230 if (!pdpu->is_rt_pipe) 1231 return; 1232 1233 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1234 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); 1235 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1236 } 1237 1238 static ssize_t _dpu_plane_danger_read(struct file *file, 1239 char __user *buff, size_t count, loff_t *ppos) 1240 { 1241 struct dpu_kms *kms = file->private_data; 1242 int len; 1243 char buf[40]; 1244 1245 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 1246 1247 return simple_read_from_buffer(buff, count, ppos, buf, len); 1248 } 1249 1250 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 1251 { 1252 struct drm_plane *plane; 1253 1254 drm_for_each_plane(plane, kms->dev) { 1255 if (plane->fb && plane->state) { 1256 dpu_plane_danger_signal_ctrl(plane, enable); 1257 DPU_DEBUG("plane:%d img:%dx%d ", 1258 plane->base.id, plane->fb->width, 1259 plane->fb->height); 1260 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 1261 plane->state->src_x >> 16, 1262 plane->state->src_y >> 16, 1263 plane->state->src_w >> 16, 1264 plane->state->src_h >> 16, 1265 plane->state->crtc_x, plane->state->crtc_y, 1266 plane->state->crtc_w, plane->state->crtc_h); 1267 } else { 1268 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 1269 } 1270 } 1271 } 1272 1273 static ssize_t _dpu_plane_danger_write(struct file *file, 1274 const char __user *user_buf, size_t count, loff_t *ppos) 1275 { 1276 struct dpu_kms *kms = file->private_data; 1277 int disable_panic; 1278 int ret; 1279 1280 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 1281 if (ret) 1282 return ret; 1283 1284 if (disable_panic) { 1285 /* Disable panic signal for all active pipes */ 1286 DPU_DEBUG("Disabling danger:\n"); 1287 _dpu_plane_set_danger_state(kms, false); 1288 kms->has_danger_ctrl = false; 1289 } else { 1290 /* Enable panic signal for all active pipes */ 1291 DPU_DEBUG("Enabling danger:\n"); 1292 kms->has_danger_ctrl = true; 1293 _dpu_plane_set_danger_state(kms, true); 1294 } 1295 1296 return count; 1297 } 1298 1299 static const struct file_operations dpu_plane_danger_enable = { 1300 .open = simple_open, 1301 .read = _dpu_plane_danger_read, 1302 .write = _dpu_plane_danger_write, 1303 }; 1304 1305 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1306 { 1307 struct dpu_plane *pdpu = to_dpu_plane(plane); 1308 struct dpu_kms *kms = _dpu_plane_get_kms(plane); 1309 const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap; 1310 const struct dpu_sspp_sub_blks *sblk = cfg->sblk; 1311 1312 /* create overall sub-directory for the pipe */ 1313 pdpu->debugfs_root = 1314 debugfs_create_dir(pdpu->pipe_name, 1315 plane->dev->primary->debugfs_root); 1316 1317 /* don't error check these */ 1318 debugfs_create_x32("features", 0600, 1319 pdpu->debugfs_root, &pdpu->features); 1320 1321 /* add register dump support */ 1322 dpu_debugfs_setup_regset32(&pdpu->debugfs_src, 1323 sblk->src_blk.base + cfg->base, 1324 sblk->src_blk.len, 1325 kms); 1326 dpu_debugfs_create_regset32("src_blk", 0400, 1327 pdpu->debugfs_root, &pdpu->debugfs_src); 1328 1329 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || 1330 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) { 1331 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler, 1332 sblk->scaler_blk.base + cfg->base, 1333 sblk->scaler_blk.len, 1334 kms); 1335 dpu_debugfs_create_regset32("scaler_blk", 0400, 1336 pdpu->debugfs_root, 1337 &pdpu->debugfs_scaler); 1338 debugfs_create_bool("default_scaling", 1339 0600, 1340 pdpu->debugfs_root, 1341 &pdpu->debugfs_default_scale); 1342 } 1343 1344 if (cfg->features & BIT(DPU_SSPP_CSC) || 1345 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) { 1346 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc, 1347 sblk->csc_blk.base + cfg->base, 1348 sblk->csc_blk.len, 1349 kms); 1350 dpu_debugfs_create_regset32("csc_blk", 0400, 1351 pdpu->debugfs_root, &pdpu->debugfs_csc); 1352 } 1353 1354 debugfs_create_u32("xin_id", 1355 0400, 1356 pdpu->debugfs_root, 1357 (u32 *) &cfg->xin_id); 1358 debugfs_create_u32("clk_ctrl", 1359 0400, 1360 pdpu->debugfs_root, 1361 (u32 *) &cfg->clk_ctrl); 1362 debugfs_create_x32("creq_vblank", 1363 0600, 1364 pdpu->debugfs_root, 1365 (u32 *) &sblk->creq_vblank); 1366 debugfs_create_x32("danger_vblank", 1367 0600, 1368 pdpu->debugfs_root, 1369 (u32 *) &sblk->danger_vblank); 1370 1371 debugfs_create_file("disable_danger", 1372 0600, 1373 pdpu->debugfs_root, 1374 kms, &dpu_plane_danger_enable); 1375 1376 return 0; 1377 } 1378 #else 1379 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1380 { 1381 return 0; 1382 } 1383 #endif 1384 1385 static int dpu_plane_late_register(struct drm_plane *plane) 1386 { 1387 return _dpu_plane_init_debugfs(plane); 1388 } 1389 1390 static void dpu_plane_early_unregister(struct drm_plane *plane) 1391 { 1392 struct dpu_plane *pdpu = to_dpu_plane(plane); 1393 1394 debugfs_remove_recursive(pdpu->debugfs_root); 1395 } 1396 1397 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1398 uint32_t format, uint64_t modifier) 1399 { 1400 if (modifier == DRM_FORMAT_MOD_LINEAR) 1401 return true; 1402 1403 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) { 1404 int i; 1405 for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) { 1406 if (format == qcom_compressed_supported_formats[i]) 1407 return true; 1408 } 1409 } 1410 1411 return false; 1412 } 1413 1414 static const struct drm_plane_funcs dpu_plane_funcs = { 1415 .update_plane = drm_atomic_helper_update_plane, 1416 .disable_plane = drm_atomic_helper_disable_plane, 1417 .destroy = dpu_plane_destroy, 1418 .reset = dpu_plane_reset, 1419 .atomic_duplicate_state = dpu_plane_duplicate_state, 1420 .atomic_destroy_state = dpu_plane_destroy_state, 1421 .late_register = dpu_plane_late_register, 1422 .early_unregister = dpu_plane_early_unregister, 1423 .format_mod_supported = dpu_plane_format_mod_supported, 1424 }; 1425 1426 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1427 .prepare_fb = dpu_plane_prepare_fb, 1428 .cleanup_fb = dpu_plane_cleanup_fb, 1429 .atomic_check = dpu_plane_atomic_check, 1430 .atomic_update = dpu_plane_atomic_update, 1431 }; 1432 1433 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) 1434 { 1435 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; 1436 } 1437 1438 bool is_dpu_plane_virtual(struct drm_plane *plane) 1439 { 1440 return plane ? to_dpu_plane(plane)->is_virtual : false; 1441 } 1442 1443 /* initialize plane */ 1444 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1445 uint32_t pipe, enum drm_plane_type type, 1446 unsigned long possible_crtcs, u32 master_plane_id) 1447 { 1448 struct drm_plane *plane = NULL, *master_plane = NULL; 1449 const uint32_t *format_list; 1450 struct dpu_plane *pdpu; 1451 struct msm_drm_private *priv = dev->dev_private; 1452 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1453 int zpos_max = DPU_ZPOS_MAX; 1454 uint32_t num_formats; 1455 int ret = -EINVAL; 1456 1457 /* create and zero local structure */ 1458 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1459 if (!pdpu) { 1460 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1461 ret = -ENOMEM; 1462 return ERR_PTR(ret); 1463 } 1464 1465 /* cache local stuff for later */ 1466 plane = &pdpu->base; 1467 pdpu->pipe = pipe; 1468 pdpu->is_virtual = (master_plane_id != 0); 1469 INIT_LIST_HEAD(&pdpu->mplane_list); 1470 master_plane = drm_plane_find(dev, NULL, master_plane_id); 1471 if (master_plane) { 1472 struct dpu_plane *mpdpu = to_dpu_plane(master_plane); 1473 1474 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list); 1475 } 1476 1477 /* initialize underlying h/w driver */ 1478 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, 1479 master_plane_id != 0); 1480 if (IS_ERR(pdpu->pipe_hw)) { 1481 DPU_ERROR("[%u]SSPP init failed\n", pipe); 1482 ret = PTR_ERR(pdpu->pipe_hw); 1483 goto clean_plane; 1484 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { 1485 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); 1486 goto clean_sspp; 1487 } 1488 1489 /* cache features mask for later */ 1490 pdpu->features = pdpu->pipe_hw->cap->features; 1491 pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk; 1492 if (!pdpu->pipe_sblk) { 1493 DPU_ERROR("[%u]invalid sblk\n", pipe); 1494 goto clean_sspp; 1495 } 1496 1497 if (pdpu->is_virtual) { 1498 format_list = pdpu->pipe_sblk->virt_format_list; 1499 num_formats = pdpu->pipe_sblk->virt_num_formats; 1500 } 1501 else { 1502 format_list = pdpu->pipe_sblk->format_list; 1503 num_formats = pdpu->pipe_sblk->num_formats; 1504 } 1505 1506 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1507 format_list, num_formats, 1508 supported_format_modifiers, type, NULL); 1509 if (ret) 1510 goto clean_sspp; 1511 1512 pdpu->catalog = kms->catalog; 1513 1514 if (kms->catalog->mixer_count && 1515 kms->catalog->mixer[0].sblk->maxblendstages) { 1516 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; 1517 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) 1518 zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; 1519 } 1520 1521 ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); 1522 if (ret) 1523 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1524 1525 drm_plane_enable_fb_damage_clips(plane); 1526 1527 /* success! finalize initialization */ 1528 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1529 1530 /* save user friendly pipe name for later */ 1531 snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id); 1532 1533 mutex_init(&pdpu->lock); 1534 1535 DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name, 1536 pipe, plane->base.id, master_plane_id); 1537 return plane; 1538 1539 clean_sspp: 1540 if (pdpu && pdpu->pipe_hw) 1541 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1542 clean_plane: 1543 kfree(pdpu); 1544 return ERR_PTR(ret); 1545 } 1546