1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include "msm_drv.h" 21 #include "dpu_kms.h" 22 #include "dpu_formats.h" 23 #include "dpu_hw_sspp.h" 24 #include "dpu_trace.h" 25 #include "dpu_crtc.h" 26 #include "dpu_vbif.h" 27 #include "dpu_plane.h" 28 29 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 30 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 31 32 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 33 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 34 35 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 36 #define PHASE_STEP_SHIFT 21 37 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 38 #define PHASE_RESIDUAL 15 39 40 #define SHARP_STRENGTH_DEFAULT 32 41 #define SHARP_EDGE_THR_DEFAULT 112 42 #define SHARP_SMOOTH_THR_DEFAULT 8 43 #define SHARP_NOISE_THR_DEFAULT 2 44 45 #define DPU_NAME_SIZE 12 46 47 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 48 #define DPU_ZPOS_MAX 255 49 50 /* 51 * Default Preload Values 52 */ 53 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 54 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 55 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 56 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 57 58 #define DEFAULT_REFRESH_RATE 60 59 60 static const uint32_t qcom_compressed_supported_formats[] = { 61 DRM_FORMAT_ABGR8888, 62 DRM_FORMAT_ARGB8888, 63 DRM_FORMAT_XBGR8888, 64 DRM_FORMAT_XRGB8888, 65 DRM_FORMAT_ARGB2101010, 66 DRM_FORMAT_XRGB2101010, 67 DRM_FORMAT_BGR565, 68 69 DRM_FORMAT_NV12, 70 DRM_FORMAT_P010, 71 }; 72 73 /** 74 * enum dpu_plane_qos - Different qos configurations for each pipe 75 * 76 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. 77 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. 78 * this configuration is mutually exclusive from VBLANK_CTRL. 79 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. 80 */ 81 enum dpu_plane_qos { 82 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), 83 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), 84 DPU_PLANE_QOS_PANIC_CTRL = BIT(2), 85 }; 86 87 /* 88 * struct dpu_plane - local dpu plane structure 89 * @aspace: address space pointer 90 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 91 * @catalog: Points to dpu catalog structure 92 * @revalidate: force revalidation of all the plane properties 93 */ 94 struct dpu_plane { 95 struct drm_plane base; 96 97 struct mutex lock; 98 99 enum dpu_sspp pipe; 100 101 uint32_t color_fill; 102 bool is_error; 103 bool is_rt_pipe; 104 const struct dpu_mdss_cfg *catalog; 105 }; 106 107 static const uint64_t supported_format_modifiers[] = { 108 DRM_FORMAT_MOD_QCOM_COMPRESSED, 109 DRM_FORMAT_MOD_LINEAR, 110 DRM_FORMAT_MOD_INVALID 111 }; 112 113 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 114 115 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 116 { 117 struct msm_drm_private *priv = plane->dev->dev_private; 118 119 return to_dpu_kms(priv->kms); 120 } 121 122 /** 123 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 124 * @catalog: Points to dpu catalog structure 125 * @fmt: Pointer to source buffer format 126 * @mode: Pointer to drm display mode 127 * @pipe_cfg: Pointer to pipe configuration 128 * Result: Updates calculated bandwidth in the plane state. 129 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 130 * Prefill BW Equation: line src bytes * line_time 131 */ 132 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, 133 const struct dpu_format *fmt, 134 const struct drm_display_mode *mode, 135 struct dpu_sw_pipe_cfg *pipe_cfg) 136 { 137 int src_width, src_height, dst_height, fps; 138 u64 plane_prefill_bw; 139 u64 plane_bw; 140 u32 hw_latency_lines; 141 u64 scale_factor; 142 int vbp, vpw, vfp; 143 144 src_width = drm_rect_width(&pipe_cfg->src_rect); 145 src_height = drm_rect_height(&pipe_cfg->src_rect); 146 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 147 fps = drm_mode_vrefresh(mode); 148 vbp = mode->vtotal - mode->vsync_end; 149 vpw = mode->vsync_end - mode->vsync_start; 150 vfp = mode->vsync_start - mode->vdisplay; 151 hw_latency_lines = catalog->perf->min_prefill_lines; 152 scale_factor = src_height > dst_height ? 153 mult_frac(src_height, 1, dst_height) : 1; 154 155 plane_bw = 156 src_width * mode->vtotal * fps * fmt->bpp * 157 scale_factor; 158 159 plane_prefill_bw = 160 src_width * hw_latency_lines * fps * fmt->bpp * 161 scale_factor * mode->vtotal; 162 163 if ((vbp+vpw) > hw_latency_lines) 164 do_div(plane_prefill_bw, (vbp+vpw)); 165 else if ((vbp+vpw+vfp) < hw_latency_lines) 166 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 167 else 168 do_div(plane_prefill_bw, hw_latency_lines); 169 170 171 return max(plane_bw, plane_prefill_bw); 172 } 173 174 /** 175 * _dpu_plane_calc_clk - calculate clock required for a plane 176 * @mode: Pointer to drm display mode 177 * @pipe_cfg: Pointer to pipe configuration 178 * Result: Updates calculated clock in the plane state. 179 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 180 */ 181 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, 182 struct dpu_sw_pipe_cfg *pipe_cfg) 183 { 184 int dst_width, src_height, dst_height, fps; 185 u64 plane_clk; 186 187 src_height = drm_rect_height(&pipe_cfg->src_rect); 188 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 189 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 190 fps = drm_mode_vrefresh(mode); 191 192 plane_clk = 193 dst_width * mode->vtotal * fps; 194 195 if (src_height > dst_height) { 196 plane_clk *= src_height; 197 do_div(plane_clk, dst_height); 198 } 199 200 return plane_clk; 201 } 202 203 /** 204 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 205 * @plane: Pointer to drm plane 206 * @pipe: Pointer to software pipe 207 * @fmt: Pointer to source buffer format 208 * @src_width: width of source buffer 209 * Return: fill level corresponding to the source buffer/format or 0 if error 210 */ 211 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 212 struct dpu_sw_pipe *pipe, 213 const struct dpu_format *fmt, u32 src_width) 214 { 215 struct dpu_plane *pdpu; 216 u32 fixed_buff_size; 217 u32 total_fl; 218 219 if (!fmt || !pipe || !src_width || !fmt->bpp) { 220 DPU_ERROR("invalid arguments\n"); 221 return 0; 222 } 223 224 pdpu = to_dpu_plane(plane); 225 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 226 227 /* FIXME: in multirect case account for the src_width of all the planes */ 228 229 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 230 if (fmt->chroma_sample == DPU_CHROMA_420) { 231 /* NV12 */ 232 total_fl = (fixed_buff_size / 2) / 233 ((src_width + 32) * fmt->bpp); 234 } else { 235 /* non NV12 */ 236 total_fl = (fixed_buff_size / 2) * 2 / 237 ((src_width + 32) * fmt->bpp); 238 } 239 } else { 240 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 241 total_fl = (fixed_buff_size / 2) * 2 / 242 ((src_width + 32) * fmt->bpp); 243 } else { 244 total_fl = (fixed_buff_size) * 2 / 245 ((src_width + 32) * fmt->bpp); 246 } 247 } 248 249 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", 250 pipe->sspp->idx - SSPP_VIG0, 251 (char *)&fmt->base.pixel_format, 252 src_width, total_fl); 253 254 return total_fl; 255 } 256 257 /** 258 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 259 * @plane: Pointer to drm plane 260 * @pipe: Pointer to software pipe 261 * @fmt: Pointer to source buffer format 262 * @pipe_cfg: Pointer to pipe configuration 263 */ 264 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 265 struct dpu_sw_pipe *pipe, 266 const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) 267 { 268 struct dpu_plane *pdpu = to_dpu_plane(plane); 269 u64 qos_lut; 270 u32 total_fl = 0, lut_usage; 271 272 if (!pdpu->is_rt_pipe) { 273 lut_usage = DPU_QOS_LUT_USAGE_NRT; 274 } else { 275 total_fl = _dpu_plane_calc_fill_level(plane, pipe, fmt, 276 drm_rect_width(&pipe_cfg->src_rect)); 277 278 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 279 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 280 else 281 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 282 } 283 284 qos_lut = _dpu_hw_get_qos_lut( 285 &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 286 287 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, 288 (fmt) ? fmt->base.pixel_format : 0, 289 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); 290 291 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 292 pdpu->pipe - SSPP_VIG0, 293 fmt ? (char *)&fmt->base.pixel_format : NULL, 294 pdpu->is_rt_pipe, total_fl, qos_lut); 295 296 pipe->sspp->ops.setup_creq_lut(pipe->sspp, qos_lut); 297 } 298 299 /** 300 * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane 301 * @plane: Pointer to drm plane 302 * @pipe: Pointer to software pipe 303 * @fmt: Pointer to source buffer format 304 */ 305 static void _dpu_plane_set_danger_lut(struct drm_plane *plane, 306 struct dpu_sw_pipe *pipe, 307 const struct dpu_format *fmt) 308 { 309 struct dpu_plane *pdpu = to_dpu_plane(plane); 310 u32 danger_lut, safe_lut; 311 312 if (!pdpu->is_rt_pipe) { 313 danger_lut = pdpu->catalog->perf->danger_lut_tbl 314 [DPU_QOS_LUT_USAGE_NRT]; 315 safe_lut = pdpu->catalog->perf->safe_lut_tbl 316 [DPU_QOS_LUT_USAGE_NRT]; 317 } else { 318 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { 319 danger_lut = pdpu->catalog->perf->danger_lut_tbl 320 [DPU_QOS_LUT_USAGE_LINEAR]; 321 safe_lut = pdpu->catalog->perf->safe_lut_tbl 322 [DPU_QOS_LUT_USAGE_LINEAR]; 323 } else { 324 danger_lut = pdpu->catalog->perf->danger_lut_tbl 325 [DPU_QOS_LUT_USAGE_MACROTILE]; 326 safe_lut = pdpu->catalog->perf->safe_lut_tbl 327 [DPU_QOS_LUT_USAGE_MACROTILE]; 328 } 329 } 330 331 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 332 (fmt) ? fmt->base.pixel_format : 0, 333 (fmt) ? fmt->fetch_mode : 0, 334 danger_lut, 335 safe_lut); 336 337 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 338 pdpu->pipe - SSPP_VIG0, 339 fmt ? (char *)&fmt->base.pixel_format : NULL, 340 fmt ? fmt->fetch_mode : -1, 341 danger_lut, 342 safe_lut); 343 344 pipe->sspp->ops.setup_danger_safe_lut(pipe->sspp, 345 danger_lut, safe_lut); 346 } 347 348 /** 349 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 350 * @plane: Pointer to drm plane 351 * @pipe: Pointer to software pipe 352 * @enable: true to enable QoS control 353 * @flags: QoS control mode (enum dpu_plane_qos) 354 */ 355 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 356 struct dpu_sw_pipe *pipe, 357 bool enable, u32 flags) 358 { 359 struct dpu_plane *pdpu = to_dpu_plane(plane); 360 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; 361 362 memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); 363 364 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { 365 pipe_qos_cfg.creq_vblank = pipe->sspp->cap->sblk->creq_vblank; 366 pipe_qos_cfg.danger_vblank = 367 pipe->sspp->cap->sblk->danger_vblank; 368 pipe_qos_cfg.vblank_en = enable; 369 } 370 371 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { 372 /* this feature overrules previous VBLANK_CTRL */ 373 pipe_qos_cfg.vblank_en = false; 374 pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ 375 } 376 377 if (flags & DPU_PLANE_QOS_PANIC_CTRL) 378 pipe_qos_cfg.danger_safe_en = enable; 379 380 if (!pdpu->is_rt_pipe) { 381 pipe_qos_cfg.vblank_en = false; 382 pipe_qos_cfg.danger_safe_en = false; 383 } 384 385 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", 386 pdpu->pipe - SSPP_VIG0, 387 pipe_qos_cfg.danger_safe_en, 388 pipe_qos_cfg.vblank_en, 389 pipe_qos_cfg.creq_vblank, 390 pipe_qos_cfg.danger_vblank, 391 pdpu->is_rt_pipe); 392 393 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, 394 &pipe_qos_cfg); 395 } 396 397 /** 398 * _dpu_plane_set_ot_limit - set OT limit for the given plane 399 * @plane: Pointer to drm plane 400 * @pipe: Pointer to software pipe 401 * @pipe_cfg: Pointer to pipe configuration 402 * @frame_rate: CRTC's frame rate 403 */ 404 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 405 struct dpu_sw_pipe *pipe, 406 struct dpu_sw_pipe_cfg *pipe_cfg, 407 int frame_rate) 408 { 409 struct dpu_plane *pdpu = to_dpu_plane(plane); 410 struct dpu_vbif_set_ot_params ot_params; 411 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 412 413 memset(&ot_params, 0, sizeof(ot_params)); 414 ot_params.xin_id = pipe->sspp->cap->xin_id; 415 ot_params.num = pipe->sspp->idx - SSPP_NONE; 416 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 417 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 418 ot_params.is_wfd = !pdpu->is_rt_pipe; 419 ot_params.frame_rate = frame_rate; 420 ot_params.vbif_idx = VBIF_RT; 421 ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; 422 ot_params.rd = true; 423 424 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 425 } 426 427 /** 428 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 429 * @plane: Pointer to drm plane 430 * @pipe: Pointer to software pipe 431 */ 432 static void _dpu_plane_set_qos_remap(struct drm_plane *plane, 433 struct dpu_sw_pipe *pipe) 434 { 435 struct dpu_plane *pdpu = to_dpu_plane(plane); 436 struct dpu_vbif_set_qos_params qos_params; 437 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 438 439 memset(&qos_params, 0, sizeof(qos_params)); 440 qos_params.vbif_idx = VBIF_RT; 441 qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; 442 qos_params.xin_id = pipe->sspp->cap->xin_id; 443 qos_params.num = pipe->sspp->idx - SSPP_VIG0; 444 qos_params.is_rt = pdpu->is_rt_pipe; 445 446 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 447 qos_params.num, 448 qos_params.vbif_idx, 449 qos_params.xin_id, qos_params.is_rt, 450 qos_params.clk_ctrl); 451 452 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 453 } 454 455 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, 456 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 457 struct dpu_hw_scaler3_cfg *scale_cfg, 458 const struct dpu_format *fmt, 459 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, 460 unsigned int rotation) 461 { 462 uint32_t i; 463 bool inline_rotation = rotation & DRM_MODE_ROTATE_90; 464 465 /* 466 * For inline rotation cases, scaler config is post-rotation, 467 * so swap the dimensions here. However, pixel extension will 468 * need pre-rotation settings. 469 */ 470 if (inline_rotation) 471 swap(src_w, src_h); 472 473 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 474 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 475 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 476 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 477 478 479 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 480 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 481 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 482 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 483 484 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 485 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 486 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 487 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 488 489 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 490 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 491 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 492 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 493 494 for (i = 0; i < DPU_MAX_PLANES; i++) { 495 scale_cfg->src_width[i] = src_w; 496 scale_cfg->src_height[i] = src_h; 497 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 498 scale_cfg->src_width[i] /= chroma_subsmpl_h; 499 scale_cfg->src_height[i] /= chroma_subsmpl_v; 500 } 501 502 if (pipe_hw->cap->features & 503 BIT(DPU_SSPP_SCALER_QSEED4)) { 504 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 505 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 506 } else { 507 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 508 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 509 } 510 } 511 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 512 && (src_w == dst_w)) 513 return; 514 515 scale_cfg->dst_width = dst_w; 516 scale_cfg->dst_height = dst_h; 517 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 518 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 519 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 520 scale_cfg->lut_flag = 0; 521 scale_cfg->blend_cfg = 1; 522 scale_cfg->enable = 1; 523 } 524 525 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 526 struct dpu_hw_pixel_ext *pixel_ext, 527 uint32_t src_w, uint32_t src_h, 528 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 529 { 530 int i; 531 532 for (i = 0; i < DPU_MAX_PLANES; i++) { 533 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 534 src_w /= chroma_subsmpl_h; 535 src_h /= chroma_subsmpl_v; 536 } 537 538 pixel_ext->num_ext_pxls_top[i] = src_h; 539 pixel_ext->num_ext_pxls_left[i] = src_w; 540 } 541 } 542 543 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 544 { 545 /* S15.16 format */ 546 0x00012A00, 0x00000000, 0x00019880, 547 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 548 0x00012A00, 0x00020480, 0x00000000, 549 }, 550 /* signed bias */ 551 { 0xfff0, 0xff80, 0xff80,}, 552 { 0x0, 0x0, 0x0,}, 553 /* unsigned clamp */ 554 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 555 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 556 }; 557 558 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 559 { 560 /* S15.16 format */ 561 0x00012A00, 0x00000000, 0x00019880, 562 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 563 0x00012A00, 0x00020480, 0x00000000, 564 }, 565 /* signed bias */ 566 { 0xffc0, 0xfe00, 0xfe00,}, 567 { 0x0, 0x0, 0x0,}, 568 /* unsigned clamp */ 569 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 570 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 571 }; 572 573 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, 574 const struct dpu_format *fmt) 575 { 576 const struct dpu_csc_cfg *csc_ptr; 577 578 if (!DPU_FORMAT_IS_YUV(fmt)) 579 return NULL; 580 581 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) 582 csc_ptr = &dpu_csc10_YUV2RGB_601L; 583 else 584 csc_ptr = &dpu_csc_YUV2RGB_601L; 585 586 return csc_ptr; 587 } 588 589 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 590 const struct dpu_format *fmt, bool color_fill, 591 struct dpu_sw_pipe_cfg *pipe_cfg, 592 unsigned int rotation) 593 { 594 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 595 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 596 struct dpu_hw_scaler3_cfg scaler3_cfg; 597 struct dpu_hw_pixel_ext pixel_ext; 598 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 599 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 600 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 601 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 602 603 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 604 memset(&pixel_ext, 0, sizeof(pixel_ext)); 605 606 /* don't chroma subsample if decimating */ 607 /* update scaler. calculate default config for QSEED3 */ 608 _dpu_plane_setup_scaler3(pipe_hw, 609 src_width, 610 src_height, 611 dst_width, 612 dst_height, 613 &scaler3_cfg, fmt, 614 info->hsub, info->vsub, 615 rotation); 616 617 /* configure pixel extension based on scalar config */ 618 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 619 src_width, src_height, info->hsub, info->vsub); 620 621 if (pipe_hw->ops.setup_pe) 622 pipe_hw->ops.setup_pe(pipe_hw, 623 &pixel_ext); 624 625 /** 626 * when programmed in multirect mode, scalar block will be 627 * bypassed. Still we need to update alpha and bitwidth 628 * ONLY for RECT0 629 */ 630 if (pipe_hw->ops.setup_scaler && 631 pipe->multirect_index != DPU_SSPP_RECT_1) 632 pipe_hw->ops.setup_scaler(pipe_hw, 633 &scaler3_cfg, 634 fmt); 635 } 636 637 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, 638 struct dpu_sw_pipe *pipe, 639 struct drm_rect *dst_rect, 640 u32 fill_color, 641 const struct dpu_format *fmt) 642 { 643 struct dpu_sw_pipe_cfg pipe_cfg; 644 645 /* update sspp */ 646 if (!pipe->sspp->ops.setup_solidfill) 647 return; 648 649 pipe->sspp->ops.setup_solidfill(pipe, fill_color); 650 651 /* override scaler/decimation if solid fill */ 652 pipe_cfg.dst_rect = *dst_rect; 653 654 pipe_cfg.src_rect.x1 = 0; 655 pipe_cfg.src_rect.y1 = 0; 656 pipe_cfg.src_rect.x2 = 657 drm_rect_width(&pipe_cfg.dst_rect); 658 pipe_cfg.src_rect.y2 = 659 drm_rect_height(&pipe_cfg.dst_rect); 660 661 if (pipe->sspp->ops.setup_format) 662 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); 663 664 if (pipe->sspp->ops.setup_rects) 665 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 666 667 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); 668 } 669 670 /** 671 * _dpu_plane_color_fill - enables color fill on plane 672 * @pdpu: Pointer to DPU plane object 673 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 674 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 675 */ 676 static void _dpu_plane_color_fill(struct dpu_plane *pdpu, 677 uint32_t color, uint32_t alpha) 678 { 679 const struct dpu_format *fmt; 680 const struct drm_plane *plane = &pdpu->base; 681 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 682 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); 683 684 DPU_DEBUG_PLANE(pdpu, "\n"); 685 686 /* 687 * select fill format to match user property expectation, 688 * h/w only supports RGB variants 689 */ 690 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 691 /* should not happen ever */ 692 if (!fmt) 693 return; 694 695 /* update sspp */ 696 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, 697 fill_color, fmt); 698 699 if (pstate->r_pipe.sspp) 700 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, 701 fill_color, fmt); 702 } 703 704 static int dpu_plane_prepare_fb(struct drm_plane *plane, 705 struct drm_plane_state *new_state) 706 { 707 struct drm_framebuffer *fb = new_state->fb; 708 struct dpu_plane *pdpu = to_dpu_plane(plane); 709 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 710 struct dpu_hw_fmt_layout layout; 711 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 712 int ret; 713 714 if (!new_state->fb) 715 return 0; 716 717 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 718 719 /* cache aspace */ 720 pstate->aspace = kms->base.aspace; 721 722 /* 723 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 724 * we can use msm_atomic_prepare_fb() instead of doing the 725 * implicit fence and fb prepare by hand here. 726 */ 727 drm_gem_plane_helper_prepare_fb(plane, new_state); 728 729 if (pstate->aspace) { 730 ret = msm_framebuffer_prepare(new_state->fb, 731 pstate->aspace, pstate->needs_dirtyfb); 732 if (ret) { 733 DPU_ERROR("failed to prepare framebuffer\n"); 734 return ret; 735 } 736 } 737 738 /* validate framebuffer layout before commit */ 739 ret = dpu_format_populate_layout(pstate->aspace, 740 new_state->fb, &layout); 741 if (ret) { 742 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 743 return ret; 744 } 745 746 return 0; 747 } 748 749 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 750 struct drm_plane_state *old_state) 751 { 752 struct dpu_plane *pdpu = to_dpu_plane(plane); 753 struct dpu_plane_state *old_pstate; 754 755 if (!old_state || !old_state->fb) 756 return; 757 758 old_pstate = to_dpu_plane_state(old_state); 759 760 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 761 762 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace, 763 old_pstate->needs_dirtyfb); 764 } 765 766 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 767 const struct dpu_sspp_sub_blks *sblk, 768 struct drm_rect src, const struct dpu_format *fmt) 769 { 770 size_t num_formats; 771 const u32 *supported_formats; 772 773 if (!sblk->rotation_cfg) { 774 DPU_ERROR("invalid rotation cfg\n"); 775 return -EINVAL; 776 } 777 778 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 779 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 780 src.y2, sblk->rotation_cfg->rot_maxheight); 781 return -EINVAL; 782 } 783 784 supported_formats = sblk->rotation_cfg->rot_format_list; 785 num_formats = sblk->rotation_cfg->rot_num_formats; 786 787 if (!DPU_FORMAT_IS_UBWC(fmt) || 788 !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats)) 789 return -EINVAL; 790 791 return 0; 792 } 793 794 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, 795 struct dpu_sw_pipe *pipe, 796 struct dpu_sw_pipe_cfg *pipe_cfg, 797 const struct dpu_format *fmt) 798 { 799 uint32_t min_src_size; 800 801 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 802 803 if (DPU_FORMAT_IS_YUV(fmt) && 804 (!(pipe->sspp->cap->features & DPU_SSPP_SCALER) || 805 !(pipe->sspp->cap->features & DPU_SSPP_CSC_ANY))) { 806 DPU_DEBUG_PLANE(pdpu, 807 "plane doesn't have scaler/csc for yuv\n"); 808 return -EINVAL; 809 } 810 811 /* check src bounds */ 812 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || 813 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { 814 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 815 DRM_RECT_ARG(&pipe_cfg->src_rect)); 816 return -E2BIG; 817 } 818 819 /* valid yuv image */ 820 if (DPU_FORMAT_IS_YUV(fmt) && 821 (pipe_cfg->src_rect.x1 & 0x1 || 822 pipe_cfg->src_rect.y1 & 0x1 || 823 drm_rect_width(&pipe_cfg->src_rect) & 0x1 || 824 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { 825 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 826 DRM_RECT_ARG(&pipe_cfg->src_rect)); 827 return -EINVAL; 828 } 829 830 /* min dst support */ 831 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || 832 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { 833 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 834 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 835 return -EINVAL; 836 } 837 838 return 0; 839 } 840 841 static int dpu_plane_atomic_check(struct drm_plane *plane, 842 struct drm_atomic_state *state) 843 { 844 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 845 plane); 846 int ret = 0, min_scale; 847 struct dpu_plane *pdpu = to_dpu_plane(plane); 848 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 849 struct dpu_sw_pipe *pipe = &pstate->pipe; 850 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 851 const struct drm_crtc_state *crtc_state = NULL; 852 const struct dpu_format *fmt; 853 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 854 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 855 struct drm_rect fb_rect = { 0 }; 856 uint32_t max_linewidth; 857 unsigned int rotation; 858 uint32_t supported_rotations; 859 const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; 860 const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; 861 862 if (new_plane_state->crtc) 863 crtc_state = drm_atomic_get_new_crtc_state(state, 864 new_plane_state->crtc); 865 866 min_scale = FRAC_16_16(1, sblk->maxupscale); 867 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 868 min_scale, 869 sblk->maxdwnscale << 16, 870 true, true); 871 if (ret) { 872 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 873 return ret; 874 } 875 if (!new_plane_state->visible) 876 return 0; 877 878 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 879 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 880 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 881 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 882 r_pipe->sspp = NULL; 883 884 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; 885 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { 886 DPU_ERROR("> %d plane stages assigned\n", 887 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); 888 return -EINVAL; 889 } 890 891 pipe_cfg->src_rect = new_plane_state->src; 892 893 /* state->src is 16.16, src_rect is not */ 894 pipe_cfg->src_rect.x1 >>= 16; 895 pipe_cfg->src_rect.x2 >>= 16; 896 pipe_cfg->src_rect.y1 >>= 16; 897 pipe_cfg->src_rect.y2 >>= 16; 898 899 pipe_cfg->dst_rect = new_plane_state->dst; 900 901 fb_rect.x2 = new_plane_state->fb->width; 902 fb_rect.y2 = new_plane_state->fb->height; 903 904 /* Ensure fb size is supported */ 905 if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || 906 drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) { 907 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", 908 DRM_RECT_ARG(&fb_rect)); 909 return -E2BIG; 910 } 911 912 fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); 913 914 max_linewidth = pdpu->catalog->caps->max_linewidth; 915 916 if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { 917 /* 918 * In parallel multirect case only the half of the usual width 919 * is supported for tiled formats. If we are here, we know that 920 * full width is more than max_linewidth, thus each rect is 921 * wider than allowed. 922 */ 923 if (DPU_FORMAT_IS_UBWC(fmt)) { 924 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", 925 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 926 return -E2BIG; 927 } 928 929 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 930 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 931 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 932 return -E2BIG; 933 } 934 935 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || 936 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || 937 (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && 938 !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || 939 DPU_FORMAT_IS_YUV(fmt)) { 940 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", 941 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 942 return -E2BIG; 943 } 944 945 /* 946 * Use multirect for wide plane. We do not support dynamic 947 * assignment of SSPPs, so we know the configuration. 948 */ 949 pipe->multirect_index = DPU_SSPP_RECT_0; 950 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 951 952 r_pipe->sspp = pipe->sspp; 953 r_pipe->multirect_index = DPU_SSPP_RECT_1; 954 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 955 956 *r_pipe_cfg = *pipe_cfg; 957 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 958 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 959 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 960 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 961 } 962 963 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); 964 if (ret) 965 return ret; 966 967 if (r_pipe->sspp) { 968 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt); 969 if (ret) 970 return ret; 971 } 972 973 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 974 975 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 976 supported_rotations |= DRM_MODE_ROTATE_90; 977 978 rotation = drm_rotation_simplify(new_plane_state->rotation, 979 supported_rotations); 980 981 if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 982 (rotation & DRM_MODE_ROTATE_90)) { 983 ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); 984 if (ret) 985 return ret; 986 } 987 988 pstate->rotation = rotation; 989 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 990 991 return 0; 992 } 993 994 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) 995 { 996 const struct dpu_format *format = 997 to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb)); 998 const struct dpu_csc_cfg *csc_ptr; 999 1000 if (!pipe->sspp || !pipe->sspp->ops.setup_csc) 1001 return; 1002 1003 csc_ptr = _dpu_plane_get_csc(pipe, format); 1004 if (!csc_ptr) 1005 return; 1006 1007 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 1008 csc_ptr->csc_mv[0], 1009 csc_ptr->csc_mv[1], 1010 csc_ptr->csc_mv[2]); 1011 1012 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); 1013 1014 } 1015 1016 void dpu_plane_flush(struct drm_plane *plane) 1017 { 1018 struct dpu_plane *pdpu; 1019 struct dpu_plane_state *pstate; 1020 1021 if (!plane || !plane->state) { 1022 DPU_ERROR("invalid plane\n"); 1023 return; 1024 } 1025 1026 pdpu = to_dpu_plane(plane); 1027 pstate = to_dpu_plane_state(plane->state); 1028 1029 /* 1030 * These updates have to be done immediately before the plane flush 1031 * timing, and may not be moved to the atomic_update/mode_set functions. 1032 */ 1033 if (pdpu->is_error) 1034 /* force white frame with 100% alpha pipe output on error */ 1035 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 1036 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 1037 /* force 100% alpha */ 1038 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 1039 else { 1040 dpu_plane_flush_csc(pdpu, &pstate->pipe); 1041 dpu_plane_flush_csc(pdpu, &pstate->r_pipe); 1042 } 1043 1044 /* flag h/w flush complete */ 1045 if (plane->state) 1046 pstate->pending = false; 1047 } 1048 1049 /** 1050 * dpu_plane_set_error: enable/disable error condition 1051 * @plane: pointer to drm_plane structure 1052 * @error: error value to set 1053 */ 1054 void dpu_plane_set_error(struct drm_plane *plane, bool error) 1055 { 1056 struct dpu_plane *pdpu; 1057 1058 if (!plane) 1059 return; 1060 1061 pdpu = to_dpu_plane(plane); 1062 pdpu->is_error = error; 1063 } 1064 1065 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, 1066 struct dpu_sw_pipe *pipe, 1067 struct dpu_sw_pipe_cfg *pipe_cfg, 1068 const struct dpu_format *fmt, 1069 int frame_rate, 1070 struct dpu_hw_fmt_layout *layout) 1071 { 1072 uint32_t src_flags; 1073 struct dpu_plane *pdpu = to_dpu_plane(plane); 1074 struct drm_plane_state *state = plane->state; 1075 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1076 1077 if (layout && pipe->sspp->ops.setup_sourceaddress) { 1078 trace_dpu_plane_set_scanout(pipe, layout); 1079 pipe->sspp->ops.setup_sourceaddress(pipe, layout); 1080 } 1081 1082 _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL); 1083 1084 /* override for color fill */ 1085 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1086 /* skip remaining processing on color fill */ 1087 return; 1088 } 1089 1090 if (pipe->sspp->ops.setup_rects) { 1091 pipe->sspp->ops.setup_rects(pipe, 1092 pipe_cfg); 1093 } 1094 1095 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); 1096 1097 if (pipe->sspp->ops.setup_multirect) 1098 pipe->sspp->ops.setup_multirect( 1099 pipe); 1100 1101 if (pipe->sspp->ops.setup_format) { 1102 unsigned int rotation = pstate->rotation; 1103 1104 src_flags = 0x0; 1105 1106 if (rotation & DRM_MODE_REFLECT_X) 1107 src_flags |= DPU_SSPP_FLIP_LR; 1108 1109 if (rotation & DRM_MODE_REFLECT_Y) 1110 src_flags |= DPU_SSPP_FLIP_UD; 1111 1112 if (rotation & DRM_MODE_ROTATE_90) 1113 src_flags |= DPU_SSPP_ROT_90; 1114 1115 /* update format */ 1116 pipe->sspp->ops.setup_format(pipe, fmt, src_flags); 1117 1118 if (pipe->sspp->ops.setup_cdp) { 1119 struct dpu_hw_cdp_cfg cdp_cfg; 1120 1121 memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); 1122 1123 cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg 1124 [DPU_PERF_CDP_USAGE_RT].rd_enable; 1125 cdp_cfg.ubwc_meta_enable = 1126 DPU_FORMAT_IS_UBWC(fmt); 1127 cdp_cfg.tile_amortize_enable = 1128 DPU_FORMAT_IS_UBWC(fmt) || 1129 DPU_FORMAT_IS_TILE(fmt); 1130 cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; 1131 1132 pipe->sspp->ops.setup_cdp(pipe, &cdp_cfg); 1133 } 1134 } 1135 1136 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); 1137 _dpu_plane_set_danger_lut(plane, pipe, fmt); 1138 1139 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 1140 _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL); 1141 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); 1142 } 1143 1144 if (pstate->needs_qos_remap) 1145 _dpu_plane_set_qos_remap(plane, pipe); 1146 } 1147 1148 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1149 { 1150 struct dpu_plane *pdpu = to_dpu_plane(plane); 1151 struct drm_plane_state *state = plane->state; 1152 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1153 struct dpu_sw_pipe *pipe = &pstate->pipe; 1154 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1155 struct drm_crtc *crtc = state->crtc; 1156 struct drm_framebuffer *fb = state->fb; 1157 bool is_rt_pipe; 1158 const struct dpu_format *fmt = 1159 to_dpu_format(msm_framebuffer_format(fb)); 1160 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1161 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1162 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 1163 struct msm_gem_address_space *aspace = kms->base.aspace; 1164 struct dpu_hw_fmt_layout layout; 1165 bool layout_valid = false; 1166 int ret; 1167 1168 ret = dpu_format_populate_layout(aspace, fb, &layout); 1169 if (ret) 1170 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 1171 else 1172 layout_valid = true; 1173 1174 pstate->pending = true; 1175 1176 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1177 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); 1178 pdpu->is_rt_pipe = is_rt_pipe; 1179 1180 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1181 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1182 crtc->base.id, DRM_RECT_ARG(&state->dst), 1183 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1184 1185 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1186 drm_mode_vrefresh(&crtc->mode), 1187 layout_valid ? &layout : NULL); 1188 1189 if (r_pipe->sspp) { 1190 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, 1191 drm_mode_vrefresh(&crtc->mode), 1192 layout_valid ? &layout : NULL); 1193 } 1194 1195 if (pstate->needs_qos_remap) 1196 pstate->needs_qos_remap = false; 1197 1198 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, 1199 &crtc->mode, pipe_cfg); 1200 1201 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); 1202 1203 if (r_pipe->sspp) { 1204 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); 1205 1206 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); 1207 } 1208 } 1209 1210 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1211 { 1212 struct drm_plane_state *state = plane->state; 1213 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1214 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1215 1216 trace_dpu_plane_disable(DRMID(plane), false, 1217 pstate->pipe.multirect_mode); 1218 1219 if (r_pipe->sspp) { 1220 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1221 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1222 1223 if (r_pipe->sspp->ops.setup_multirect) 1224 r_pipe->sspp->ops.setup_multirect(r_pipe); 1225 } 1226 1227 pstate->pending = true; 1228 } 1229 1230 static void dpu_plane_atomic_update(struct drm_plane *plane, 1231 struct drm_atomic_state *state) 1232 { 1233 struct dpu_plane *pdpu = to_dpu_plane(plane); 1234 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1235 plane); 1236 1237 pdpu->is_error = false; 1238 1239 DPU_DEBUG_PLANE(pdpu, "\n"); 1240 1241 if (!new_state->visible) { 1242 _dpu_plane_atomic_disable(plane); 1243 } else { 1244 dpu_plane_sspp_atomic_update(plane); 1245 } 1246 } 1247 1248 static void dpu_plane_destroy(struct drm_plane *plane) 1249 { 1250 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1251 struct dpu_plane_state *pstate; 1252 1253 DPU_DEBUG_PLANE(pdpu, "\n"); 1254 1255 if (pdpu) { 1256 pstate = to_dpu_plane_state(plane->state); 1257 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL); 1258 1259 if (pstate->r_pipe.sspp) 1260 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false, DPU_PLANE_QOS_PANIC_CTRL); 1261 1262 mutex_destroy(&pdpu->lock); 1263 1264 /* this will destroy the states as well */ 1265 drm_plane_cleanup(plane); 1266 1267 kfree(pdpu); 1268 } 1269 } 1270 1271 static void dpu_plane_destroy_state(struct drm_plane *plane, 1272 struct drm_plane_state *state) 1273 { 1274 __drm_atomic_helper_plane_destroy_state(state); 1275 kfree(to_dpu_plane_state(state)); 1276 } 1277 1278 static struct drm_plane_state * 1279 dpu_plane_duplicate_state(struct drm_plane *plane) 1280 { 1281 struct dpu_plane *pdpu; 1282 struct dpu_plane_state *pstate; 1283 struct dpu_plane_state *old_state; 1284 1285 if (!plane) { 1286 DPU_ERROR("invalid plane\n"); 1287 return NULL; 1288 } else if (!plane->state) { 1289 DPU_ERROR("invalid plane state\n"); 1290 return NULL; 1291 } 1292 1293 old_state = to_dpu_plane_state(plane->state); 1294 pdpu = to_dpu_plane(plane); 1295 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1296 if (!pstate) { 1297 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1298 return NULL; 1299 } 1300 1301 DPU_DEBUG_PLANE(pdpu, "\n"); 1302 1303 pstate->pending = false; 1304 1305 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1306 1307 return &pstate->base; 1308 } 1309 1310 static const char * const multirect_mode_name[] = { 1311 [DPU_SSPP_MULTIRECT_NONE] = "none", 1312 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1313 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1314 }; 1315 1316 static const char * const multirect_index_name[] = { 1317 [DPU_SSPP_RECT_SOLO] = "solo", 1318 [DPU_SSPP_RECT_0] = "rect_0", 1319 [DPU_SSPP_RECT_1] = "rect_1", 1320 }; 1321 1322 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1323 { 1324 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1325 return "unknown"; 1326 1327 return multirect_mode_name[mode]; 1328 } 1329 1330 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1331 { 1332 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1333 return "unknown"; 1334 1335 return multirect_index_name[index]; 1336 } 1337 1338 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1339 const struct drm_plane_state *state) 1340 { 1341 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1342 const struct dpu_sw_pipe *pipe = &pstate->pipe; 1343 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1344 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1345 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1346 1347 drm_printf(p, "\tstage=%d\n", pstate->stage); 1348 1349 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); 1350 drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); 1351 drm_printf(p, "\tmultirect_index[0]=%s\n", 1352 dpu_get_multirect_index(pipe->multirect_index)); 1353 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 1354 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1355 1356 if (r_pipe->sspp) { 1357 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); 1358 drm_printf(p, "\tmultirect_mode[1]=%s\n", 1359 dpu_get_multirect_mode(r_pipe->multirect_mode)); 1360 drm_printf(p, "\tmultirect_index[1]=%s\n", 1361 dpu_get_multirect_index(r_pipe->multirect_index)); 1362 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); 1363 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); 1364 } 1365 } 1366 1367 static void dpu_plane_reset(struct drm_plane *plane) 1368 { 1369 struct dpu_plane *pdpu; 1370 struct dpu_plane_state *pstate; 1371 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1372 1373 if (!plane) { 1374 DPU_ERROR("invalid plane\n"); 1375 return; 1376 } 1377 1378 pdpu = to_dpu_plane(plane); 1379 DPU_DEBUG_PLANE(pdpu, "\n"); 1380 1381 /* remove previous state, if present */ 1382 if (plane->state) { 1383 dpu_plane_destroy_state(plane, plane->state); 1384 plane->state = NULL; 1385 } 1386 1387 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1388 if (!pstate) { 1389 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1390 return; 1391 } 1392 1393 /* 1394 * Set the SSPP here until we have proper virtualized DPU planes. 1395 * This is the place where the state is allocated, so fill it fully. 1396 */ 1397 pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1398 pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; 1399 pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1400 1401 pstate->r_pipe.sspp = NULL; 1402 1403 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1404 } 1405 1406 #ifdef CONFIG_DEBUG_FS 1407 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1408 { 1409 struct dpu_plane *pdpu = to_dpu_plane(plane); 1410 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 1411 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1412 1413 if (!pdpu->is_rt_pipe) 1414 return; 1415 1416 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1417 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); 1418 if (pstate->r_pipe.sspp) 1419 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); 1420 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1421 } 1422 #endif 1423 1424 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1425 uint32_t format, uint64_t modifier) 1426 { 1427 if (modifier == DRM_FORMAT_MOD_LINEAR) 1428 return true; 1429 1430 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) 1431 return dpu_find_format(format, qcom_compressed_supported_formats, 1432 ARRAY_SIZE(qcom_compressed_supported_formats)); 1433 1434 return false; 1435 } 1436 1437 static const struct drm_plane_funcs dpu_plane_funcs = { 1438 .update_plane = drm_atomic_helper_update_plane, 1439 .disable_plane = drm_atomic_helper_disable_plane, 1440 .destroy = dpu_plane_destroy, 1441 .reset = dpu_plane_reset, 1442 .atomic_duplicate_state = dpu_plane_duplicate_state, 1443 .atomic_destroy_state = dpu_plane_destroy_state, 1444 .atomic_print_state = dpu_plane_atomic_print_state, 1445 .format_mod_supported = dpu_plane_format_mod_supported, 1446 }; 1447 1448 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1449 .prepare_fb = dpu_plane_prepare_fb, 1450 .cleanup_fb = dpu_plane_cleanup_fb, 1451 .atomic_check = dpu_plane_atomic_check, 1452 .atomic_update = dpu_plane_atomic_update, 1453 }; 1454 1455 /* initialize plane */ 1456 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1457 uint32_t pipe, enum drm_plane_type type, 1458 unsigned long possible_crtcs) 1459 { 1460 struct drm_plane *plane = NULL; 1461 const uint32_t *format_list; 1462 struct dpu_plane *pdpu; 1463 struct msm_drm_private *priv = dev->dev_private; 1464 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1465 struct dpu_hw_sspp *pipe_hw; 1466 uint32_t num_formats; 1467 uint32_t supported_rotations; 1468 int ret = -EINVAL; 1469 1470 /* create and zero local structure */ 1471 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1472 if (!pdpu) { 1473 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1474 ret = -ENOMEM; 1475 return ERR_PTR(ret); 1476 } 1477 1478 /* cache local stuff for later */ 1479 plane = &pdpu->base; 1480 pdpu->pipe = pipe; 1481 1482 /* initialize underlying h/w driver */ 1483 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); 1484 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { 1485 DPU_ERROR("[%u]SSPP is invalid\n", pipe); 1486 goto clean_plane; 1487 } 1488 1489 format_list = pipe_hw->cap->sblk->format_list; 1490 num_formats = pipe_hw->cap->sblk->num_formats; 1491 1492 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1493 format_list, num_formats, 1494 supported_format_modifiers, type, NULL); 1495 if (ret) 1496 goto clean_plane; 1497 1498 pdpu->catalog = kms->catalog; 1499 1500 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); 1501 if (ret) 1502 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1503 1504 drm_plane_create_alpha_property(plane); 1505 drm_plane_create_blend_mode_property(plane, 1506 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1507 BIT(DRM_MODE_BLEND_PREMULTI) | 1508 BIT(DRM_MODE_BLEND_COVERAGE)); 1509 1510 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1511 1512 if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1513 supported_rotations |= DRM_MODE_ROTATE_MASK; 1514 1515 drm_plane_create_rotation_property(plane, 1516 DRM_MODE_ROTATE_0, supported_rotations); 1517 1518 drm_plane_enable_fb_damage_clips(plane); 1519 1520 /* success! finalize initialization */ 1521 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1522 1523 mutex_init(&pdpu->lock); 1524 1525 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1526 pipe, plane->base.id); 1527 return plane; 1528 1529 clean_plane: 1530 kfree(pdpu); 1531 return ERR_PTR(ret); 1532 } 1533