1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_damage_helper.h> 17 #include <drm/drm_framebuffer.h> 18 #include <drm/drm_gem_atomic_helper.h> 19 20 #include "msm_drv.h" 21 #include "dpu_kms.h" 22 #include "dpu_formats.h" 23 #include "dpu_hw_sspp.h" 24 #include "dpu_trace.h" 25 #include "dpu_crtc.h" 26 #include "dpu_vbif.h" 27 #include "dpu_plane.h" 28 29 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ 30 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 31 32 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 33 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 34 35 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 36 #define PHASE_STEP_SHIFT 21 37 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 38 #define PHASE_RESIDUAL 15 39 40 #define SHARP_STRENGTH_DEFAULT 32 41 #define SHARP_EDGE_THR_DEFAULT 112 42 #define SHARP_SMOOTH_THR_DEFAULT 8 43 #define SHARP_NOISE_THR_DEFAULT 2 44 45 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 46 #define DPU_ZPOS_MAX 255 47 48 /* 49 * Default Preload Values 50 */ 51 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 52 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 53 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2 54 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4 55 56 #define DEFAULT_REFRESH_RATE 60 57 58 static const uint32_t qcom_compressed_supported_formats[] = { 59 DRM_FORMAT_ABGR8888, 60 DRM_FORMAT_ARGB8888, 61 DRM_FORMAT_XBGR8888, 62 DRM_FORMAT_XRGB8888, 63 DRM_FORMAT_ARGB2101010, 64 DRM_FORMAT_XRGB2101010, 65 DRM_FORMAT_BGR565, 66 67 DRM_FORMAT_NV12, 68 DRM_FORMAT_P010, 69 }; 70 71 /* 72 * struct dpu_plane - local dpu plane structure 73 * @aspace: address space pointer 74 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 75 * @catalog: Points to dpu catalog structure 76 * @revalidate: force revalidation of all the plane properties 77 */ 78 struct dpu_plane { 79 struct drm_plane base; 80 81 struct mutex lock; 82 83 enum dpu_sspp pipe; 84 85 uint32_t color_fill; 86 bool is_error; 87 bool is_rt_pipe; 88 const struct dpu_mdss_cfg *catalog; 89 }; 90 91 static const uint64_t supported_format_modifiers[] = { 92 DRM_FORMAT_MOD_QCOM_COMPRESSED, 93 DRM_FORMAT_MOD_LINEAR, 94 DRM_FORMAT_MOD_INVALID 95 }; 96 97 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 98 99 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 100 { 101 struct msm_drm_private *priv = plane->dev->dev_private; 102 103 return to_dpu_kms(priv->kms); 104 } 105 106 /** 107 * _dpu_plane_calc_bw - calculate bandwidth required for a plane 108 * @catalog: Points to dpu catalog structure 109 * @fmt: Pointer to source buffer format 110 * @mode: Pointer to drm display mode 111 * @pipe_cfg: Pointer to pipe configuration 112 * Result: Updates calculated bandwidth in the plane state. 113 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) 114 * Prefill BW Equation: line src bytes * line_time 115 */ 116 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, 117 const struct dpu_format *fmt, 118 const struct drm_display_mode *mode, 119 struct dpu_sw_pipe_cfg *pipe_cfg) 120 { 121 int src_width, src_height, dst_height, fps; 122 u64 plane_prefill_bw; 123 u64 plane_bw; 124 u32 hw_latency_lines; 125 u64 scale_factor; 126 int vbp, vpw, vfp; 127 128 src_width = drm_rect_width(&pipe_cfg->src_rect); 129 src_height = drm_rect_height(&pipe_cfg->src_rect); 130 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 131 fps = drm_mode_vrefresh(mode); 132 vbp = mode->vtotal - mode->vsync_end; 133 vpw = mode->vsync_end - mode->vsync_start; 134 vfp = mode->vsync_start - mode->vdisplay; 135 hw_latency_lines = catalog->perf->min_prefill_lines; 136 scale_factor = src_height > dst_height ? 137 mult_frac(src_height, 1, dst_height) : 1; 138 139 plane_bw = 140 src_width * mode->vtotal * fps * fmt->bpp * 141 scale_factor; 142 143 plane_prefill_bw = 144 src_width * hw_latency_lines * fps * fmt->bpp * 145 scale_factor * mode->vtotal; 146 147 if ((vbp+vpw) > hw_latency_lines) 148 do_div(plane_prefill_bw, (vbp+vpw)); 149 else if ((vbp+vpw+vfp) < hw_latency_lines) 150 do_div(plane_prefill_bw, (vbp+vpw+vfp)); 151 else 152 do_div(plane_prefill_bw, hw_latency_lines); 153 154 155 return max(plane_bw, plane_prefill_bw); 156 } 157 158 /** 159 * _dpu_plane_calc_clk - calculate clock required for a plane 160 * @mode: Pointer to drm display mode 161 * @pipe_cfg: Pointer to pipe configuration 162 * Result: Updates calculated clock in the plane state. 163 * Clock equation: dst_w * v_total * fps * (src_h / dst_h) 164 */ 165 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, 166 struct dpu_sw_pipe_cfg *pipe_cfg) 167 { 168 int dst_width, src_height, dst_height, fps; 169 u64 plane_clk; 170 171 src_height = drm_rect_height(&pipe_cfg->src_rect); 172 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 173 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 174 fps = drm_mode_vrefresh(mode); 175 176 plane_clk = 177 dst_width * mode->vtotal * fps; 178 179 if (src_height > dst_height) { 180 plane_clk *= src_height; 181 do_div(plane_clk, dst_height); 182 } 183 184 return plane_clk; 185 } 186 187 /** 188 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 189 * @plane: Pointer to drm plane 190 * @pipe: Pointer to software pipe 191 * @lut_usage: LUT usecase 192 * @fmt: Pointer to source buffer format 193 * @src_width: width of source buffer 194 * Return: fill level corresponding to the source buffer/format or 0 if error 195 */ 196 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 197 struct dpu_sw_pipe *pipe, 198 enum dpu_qos_lut_usage lut_usage, 199 const struct dpu_format *fmt, u32 src_width) 200 { 201 struct dpu_plane *pdpu; 202 u32 fixed_buff_size; 203 u32 total_fl; 204 205 if (!fmt || !pipe || !src_width || !fmt->bpp) { 206 DPU_ERROR("invalid arguments\n"); 207 return 0; 208 } 209 210 if (lut_usage == DPU_QOS_LUT_USAGE_NRT) 211 return 0; 212 213 pdpu = to_dpu_plane(plane); 214 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; 215 216 /* FIXME: in multirect case account for the src_width of all the planes */ 217 218 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 219 if (fmt->chroma_sample == DPU_CHROMA_420) { 220 /* NV12 */ 221 total_fl = (fixed_buff_size / 2) / 222 ((src_width + 32) * fmt->bpp); 223 } else { 224 /* non NV12 */ 225 total_fl = (fixed_buff_size / 2) * 2 / 226 ((src_width + 32) * fmt->bpp); 227 } 228 } else { 229 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 230 total_fl = (fixed_buff_size / 2) * 2 / 231 ((src_width + 32) * fmt->bpp); 232 } else { 233 total_fl = (fixed_buff_size) * 2 / 234 ((src_width + 32) * fmt->bpp); 235 } 236 } 237 238 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", 239 pipe->sspp->idx - SSPP_VIG0, 240 (char *)&fmt->base.pixel_format, 241 src_width, total_fl); 242 243 return total_fl; 244 } 245 246 /** 247 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 248 * @plane: Pointer to drm plane 249 * @pipe: Pointer to software pipe 250 * @fmt: Pointer to source buffer format 251 * @pipe_cfg: Pointer to pipe configuration 252 */ 253 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 254 struct dpu_sw_pipe *pipe, 255 const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) 256 { 257 struct dpu_plane *pdpu = to_dpu_plane(plane); 258 struct dpu_hw_qos_cfg cfg; 259 u32 total_fl, lut_usage; 260 261 if (!pdpu->is_rt_pipe) { 262 lut_usage = DPU_QOS_LUT_USAGE_NRT; 263 } else { 264 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 265 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 266 else 267 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 268 } 269 270 total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt, 271 drm_rect_width(&pipe_cfg->src_rect)); 272 273 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); 274 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage]; 275 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage]; 276 277 if (pipe->sspp->idx != SSPP_CURSOR0 && 278 pipe->sspp->idx != SSPP_CURSOR1 && 279 pdpu->is_rt_pipe) 280 cfg.danger_safe_en = true; 281 282 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 283 pdpu->pipe - SSPP_VIG0, 284 cfg.danger_safe_en, 285 pdpu->is_rt_pipe); 286 287 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, 288 (fmt) ? fmt->base.pixel_format : 0, 289 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); 290 291 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 292 pdpu->pipe - SSPP_VIG0, 293 fmt ? (char *)&fmt->base.pixel_format : NULL, 294 pdpu->is_rt_pipe, total_fl, cfg.creq_lut); 295 296 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 297 (fmt) ? fmt->base.pixel_format : 0, 298 (fmt) ? fmt->fetch_mode : 0, 299 cfg.danger_lut, 300 cfg.safe_lut); 301 302 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 303 pdpu->pipe - SSPP_VIG0, 304 fmt ? (char *)&fmt->base.pixel_format : NULL, 305 fmt ? fmt->fetch_mode : -1, 306 cfg.danger_lut, 307 cfg.safe_lut); 308 309 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); 310 } 311 312 /** 313 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 314 * @plane: Pointer to drm plane 315 * @pipe: Pointer to software pipe 316 * @enable: true to enable QoS control 317 */ 318 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 319 struct dpu_sw_pipe *pipe, 320 bool enable) 321 { 322 struct dpu_plane *pdpu = to_dpu_plane(plane); 323 324 if (!pdpu->is_rt_pipe) 325 enable = false; 326 327 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", 328 pdpu->pipe - SSPP_VIG0, 329 enable, 330 pdpu->is_rt_pipe); 331 332 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, 333 enable); 334 } 335 336 /** 337 * _dpu_plane_set_ot_limit - set OT limit for the given plane 338 * @plane: Pointer to drm plane 339 * @pipe: Pointer to software pipe 340 * @pipe_cfg: Pointer to pipe configuration 341 * @frame_rate: CRTC's frame rate 342 */ 343 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 344 struct dpu_sw_pipe *pipe, 345 struct dpu_sw_pipe_cfg *pipe_cfg, 346 int frame_rate) 347 { 348 struct dpu_plane *pdpu = to_dpu_plane(plane); 349 struct dpu_vbif_set_ot_params ot_params; 350 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 351 352 memset(&ot_params, 0, sizeof(ot_params)); 353 ot_params.xin_id = pipe->sspp->cap->xin_id; 354 ot_params.num = pipe->sspp->idx - SSPP_NONE; 355 ot_params.width = drm_rect_width(&pipe_cfg->src_rect); 356 ot_params.height = drm_rect_height(&pipe_cfg->src_rect); 357 ot_params.is_wfd = !pdpu->is_rt_pipe; 358 ot_params.frame_rate = frame_rate; 359 ot_params.vbif_idx = VBIF_RT; 360 ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; 361 ot_params.rd = true; 362 363 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 364 } 365 366 /** 367 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane 368 * @plane: Pointer to drm plane 369 * @pipe: Pointer to software pipe 370 */ 371 static void _dpu_plane_set_qos_remap(struct drm_plane *plane, 372 struct dpu_sw_pipe *pipe) 373 { 374 struct dpu_plane *pdpu = to_dpu_plane(plane); 375 struct dpu_vbif_set_qos_params qos_params; 376 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 377 378 memset(&qos_params, 0, sizeof(qos_params)); 379 qos_params.vbif_idx = VBIF_RT; 380 qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; 381 qos_params.xin_id = pipe->sspp->cap->xin_id; 382 qos_params.num = pipe->sspp->idx - SSPP_VIG0; 383 qos_params.is_rt = pdpu->is_rt_pipe; 384 385 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 386 qos_params.num, 387 qos_params.vbif_idx, 388 qos_params.xin_id, qos_params.is_rt, 389 qos_params.clk_ctrl); 390 391 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 392 } 393 394 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, 395 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 396 struct dpu_hw_scaler3_cfg *scale_cfg, 397 const struct dpu_format *fmt, 398 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, 399 unsigned int rotation) 400 { 401 uint32_t i; 402 bool inline_rotation = rotation & DRM_MODE_ROTATE_90; 403 404 /* 405 * For inline rotation cases, scaler config is post-rotation, 406 * so swap the dimensions here. However, pixel extension will 407 * need pre-rotation settings. 408 */ 409 if (inline_rotation) 410 swap(src_w, src_h); 411 412 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 413 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 414 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 415 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 416 417 418 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 419 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 420 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 421 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 422 423 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 424 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 425 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 426 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 427 428 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 429 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 430 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 431 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 432 433 for (i = 0; i < DPU_MAX_PLANES; i++) { 434 scale_cfg->src_width[i] = src_w; 435 scale_cfg->src_height[i] = src_h; 436 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 437 scale_cfg->src_width[i] /= chroma_subsmpl_h; 438 scale_cfg->src_height[i] /= chroma_subsmpl_v; 439 } 440 441 if (pipe_hw->cap->features & 442 BIT(DPU_SSPP_SCALER_QSEED4)) { 443 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 444 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 445 } else { 446 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 447 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 448 } 449 } 450 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 451 && (src_w == dst_w)) 452 return; 453 454 scale_cfg->dst_width = dst_w; 455 scale_cfg->dst_height = dst_h; 456 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 457 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 458 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 459 scale_cfg->lut_flag = 0; 460 scale_cfg->blend_cfg = 1; 461 scale_cfg->enable = 1; 462 } 463 464 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, 465 struct dpu_hw_pixel_ext *pixel_ext, 466 uint32_t src_w, uint32_t src_h, 467 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 468 { 469 int i; 470 471 for (i = 0; i < DPU_MAX_PLANES; i++) { 472 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 473 src_w /= chroma_subsmpl_h; 474 src_h /= chroma_subsmpl_v; 475 } 476 477 pixel_ext->num_ext_pxls_top[i] = src_h; 478 pixel_ext->num_ext_pxls_left[i] = src_w; 479 } 480 } 481 482 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 483 { 484 /* S15.16 format */ 485 0x00012A00, 0x00000000, 0x00019880, 486 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 487 0x00012A00, 0x00020480, 0x00000000, 488 }, 489 /* signed bias */ 490 { 0xfff0, 0xff80, 0xff80,}, 491 { 0x0, 0x0, 0x0,}, 492 /* unsigned clamp */ 493 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 494 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 495 }; 496 497 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 498 { 499 /* S15.16 format */ 500 0x00012A00, 0x00000000, 0x00019880, 501 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 502 0x00012A00, 0x00020480, 0x00000000, 503 }, 504 /* signed bias */ 505 { 0xffc0, 0xfe00, 0xfe00,}, 506 { 0x0, 0x0, 0x0,}, 507 /* unsigned clamp */ 508 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 509 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 510 }; 511 512 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, 513 const struct dpu_format *fmt) 514 { 515 const struct dpu_csc_cfg *csc_ptr; 516 517 if (!DPU_FORMAT_IS_YUV(fmt)) 518 return NULL; 519 520 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) 521 csc_ptr = &dpu_csc10_YUV2RGB_601L; 522 else 523 csc_ptr = &dpu_csc_YUV2RGB_601L; 524 525 return csc_ptr; 526 } 527 528 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 529 const struct dpu_format *fmt, bool color_fill, 530 struct dpu_sw_pipe_cfg *pipe_cfg, 531 unsigned int rotation) 532 { 533 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 534 const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); 535 struct dpu_hw_scaler3_cfg scaler3_cfg; 536 struct dpu_hw_pixel_ext pixel_ext; 537 u32 src_width = drm_rect_width(&pipe_cfg->src_rect); 538 u32 src_height = drm_rect_height(&pipe_cfg->src_rect); 539 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect); 540 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect); 541 542 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); 543 memset(&pixel_ext, 0, sizeof(pixel_ext)); 544 545 /* don't chroma subsample if decimating */ 546 /* update scaler. calculate default config for QSEED3 */ 547 _dpu_plane_setup_scaler3(pipe_hw, 548 src_width, 549 src_height, 550 dst_width, 551 dst_height, 552 &scaler3_cfg, fmt, 553 info->hsub, info->vsub, 554 rotation); 555 556 /* configure pixel extension based on scalar config */ 557 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, 558 src_width, src_height, info->hsub, info->vsub); 559 560 if (pipe_hw->ops.setup_pe) 561 pipe_hw->ops.setup_pe(pipe_hw, 562 &pixel_ext); 563 564 /** 565 * when programmed in multirect mode, scalar block will be 566 * bypassed. Still we need to update alpha and bitwidth 567 * ONLY for RECT0 568 */ 569 if (pipe_hw->ops.setup_scaler && 570 pipe->multirect_index != DPU_SSPP_RECT_1) 571 pipe_hw->ops.setup_scaler(pipe_hw, 572 &scaler3_cfg, 573 fmt); 574 } 575 576 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, 577 struct dpu_sw_pipe *pipe, 578 struct drm_rect *dst_rect, 579 u32 fill_color, 580 const struct dpu_format *fmt) 581 { 582 struct dpu_sw_pipe_cfg pipe_cfg; 583 584 /* update sspp */ 585 if (!pipe->sspp->ops.setup_solidfill) 586 return; 587 588 pipe->sspp->ops.setup_solidfill(pipe, fill_color); 589 590 /* override scaler/decimation if solid fill */ 591 pipe_cfg.dst_rect = *dst_rect; 592 593 pipe_cfg.src_rect.x1 = 0; 594 pipe_cfg.src_rect.y1 = 0; 595 pipe_cfg.src_rect.x2 = 596 drm_rect_width(&pipe_cfg.dst_rect); 597 pipe_cfg.src_rect.y2 = 598 drm_rect_height(&pipe_cfg.dst_rect); 599 600 if (pipe->sspp->ops.setup_format) 601 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); 602 603 if (pipe->sspp->ops.setup_rects) 604 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 605 606 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); 607 } 608 609 /** 610 * _dpu_plane_color_fill - enables color fill on plane 611 * @pdpu: Pointer to DPU plane object 612 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 613 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 614 */ 615 static void _dpu_plane_color_fill(struct dpu_plane *pdpu, 616 uint32_t color, uint32_t alpha) 617 { 618 const struct dpu_format *fmt; 619 const struct drm_plane *plane = &pdpu->base; 620 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 621 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); 622 623 DPU_DEBUG_PLANE(pdpu, "\n"); 624 625 /* 626 * select fill format to match user property expectation, 627 * h/w only supports RGB variants 628 */ 629 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 630 /* should not happen ever */ 631 if (!fmt) 632 return; 633 634 /* update sspp */ 635 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, 636 fill_color, fmt); 637 638 if (pstate->r_pipe.sspp) 639 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, 640 fill_color, fmt); 641 } 642 643 static int dpu_plane_prepare_fb(struct drm_plane *plane, 644 struct drm_plane_state *new_state) 645 { 646 struct drm_framebuffer *fb = new_state->fb; 647 struct dpu_plane *pdpu = to_dpu_plane(plane); 648 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 649 struct dpu_hw_fmt_layout layout; 650 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 651 int ret; 652 653 if (!new_state->fb) 654 return 0; 655 656 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 657 658 /* cache aspace */ 659 pstate->aspace = kms->base.aspace; 660 661 /* 662 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 663 * we can use msm_atomic_prepare_fb() instead of doing the 664 * implicit fence and fb prepare by hand here. 665 */ 666 drm_gem_plane_helper_prepare_fb(plane, new_state); 667 668 if (pstate->aspace) { 669 ret = msm_framebuffer_prepare(new_state->fb, 670 pstate->aspace, pstate->needs_dirtyfb); 671 if (ret) { 672 DPU_ERROR("failed to prepare framebuffer\n"); 673 return ret; 674 } 675 } 676 677 /* validate framebuffer layout before commit */ 678 ret = dpu_format_populate_layout(pstate->aspace, 679 new_state->fb, &layout); 680 if (ret) { 681 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 682 return ret; 683 } 684 685 return 0; 686 } 687 688 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 689 struct drm_plane_state *old_state) 690 { 691 struct dpu_plane *pdpu = to_dpu_plane(plane); 692 struct dpu_plane_state *old_pstate; 693 694 if (!old_state || !old_state->fb) 695 return; 696 697 old_pstate = to_dpu_plane_state(old_state); 698 699 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 700 701 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace, 702 old_pstate->needs_dirtyfb); 703 } 704 705 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 706 const struct dpu_sspp_sub_blks *sblk, 707 struct drm_rect src, const struct dpu_format *fmt) 708 { 709 size_t num_formats; 710 const u32 *supported_formats; 711 712 if (!sblk->rotation_cfg) { 713 DPU_ERROR("invalid rotation cfg\n"); 714 return -EINVAL; 715 } 716 717 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) { 718 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n", 719 src.y2, sblk->rotation_cfg->rot_maxheight); 720 return -EINVAL; 721 } 722 723 supported_formats = sblk->rotation_cfg->rot_format_list; 724 num_formats = sblk->rotation_cfg->rot_num_formats; 725 726 if (!DPU_FORMAT_IS_UBWC(fmt) || 727 !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats)) 728 return -EINVAL; 729 730 return 0; 731 } 732 733 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, 734 struct dpu_sw_pipe *pipe, 735 struct dpu_sw_pipe_cfg *pipe_cfg, 736 const struct dpu_format *fmt) 737 { 738 uint32_t min_src_size; 739 740 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 741 742 if (DPU_FORMAT_IS_YUV(fmt) && 743 (!(pipe->sspp->cap->features & DPU_SSPP_SCALER) || 744 !(pipe->sspp->cap->features & DPU_SSPP_CSC_ANY))) { 745 DPU_DEBUG_PLANE(pdpu, 746 "plane doesn't have scaler/csc for yuv\n"); 747 return -EINVAL; 748 } 749 750 /* check src bounds */ 751 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || 752 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { 753 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 754 DRM_RECT_ARG(&pipe_cfg->src_rect)); 755 return -E2BIG; 756 } 757 758 /* valid yuv image */ 759 if (DPU_FORMAT_IS_YUV(fmt) && 760 (pipe_cfg->src_rect.x1 & 0x1 || 761 pipe_cfg->src_rect.y1 & 0x1 || 762 drm_rect_width(&pipe_cfg->src_rect) & 0x1 || 763 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { 764 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 765 DRM_RECT_ARG(&pipe_cfg->src_rect)); 766 return -EINVAL; 767 } 768 769 /* min dst support */ 770 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || 771 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { 772 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 773 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 774 return -EINVAL; 775 } 776 777 return 0; 778 } 779 780 static int dpu_plane_atomic_check(struct drm_plane *plane, 781 struct drm_atomic_state *state) 782 { 783 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 784 plane); 785 int ret = 0, min_scale; 786 struct dpu_plane *pdpu = to_dpu_plane(plane); 787 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 788 struct dpu_sw_pipe *pipe = &pstate->pipe; 789 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 790 const struct drm_crtc_state *crtc_state = NULL; 791 const struct dpu_format *fmt; 792 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 793 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 794 struct drm_rect fb_rect = { 0 }; 795 uint32_t max_linewidth; 796 unsigned int rotation; 797 uint32_t supported_rotations; 798 const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; 799 const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; 800 801 if (new_plane_state->crtc) 802 crtc_state = drm_atomic_get_new_crtc_state(state, 803 new_plane_state->crtc); 804 805 min_scale = FRAC_16_16(1, sblk->maxupscale); 806 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 807 min_scale, 808 sblk->maxdwnscale << 16, 809 true, true); 810 if (ret) { 811 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 812 return ret; 813 } 814 if (!new_plane_state->visible) 815 return 0; 816 817 pipe->multirect_index = DPU_SSPP_RECT_SOLO; 818 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 819 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 820 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 821 r_pipe->sspp = NULL; 822 823 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; 824 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { 825 DPU_ERROR("> %d plane stages assigned\n", 826 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); 827 return -EINVAL; 828 } 829 830 pipe_cfg->src_rect = new_plane_state->src; 831 832 /* state->src is 16.16, src_rect is not */ 833 pipe_cfg->src_rect.x1 >>= 16; 834 pipe_cfg->src_rect.x2 >>= 16; 835 pipe_cfg->src_rect.y1 >>= 16; 836 pipe_cfg->src_rect.y2 >>= 16; 837 838 pipe_cfg->dst_rect = new_plane_state->dst; 839 840 fb_rect.x2 = new_plane_state->fb->width; 841 fb_rect.y2 = new_plane_state->fb->height; 842 843 /* Ensure fb size is supported */ 844 if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || 845 drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) { 846 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", 847 DRM_RECT_ARG(&fb_rect)); 848 return -E2BIG; 849 } 850 851 fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); 852 853 max_linewidth = pdpu->catalog->caps->max_linewidth; 854 855 if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { 856 /* 857 * In parallel multirect case only the half of the usual width 858 * is supported for tiled formats. If we are here, we know that 859 * full width is more than max_linewidth, thus each rect is 860 * wider than allowed. 861 */ 862 if (DPU_FORMAT_IS_UBWC(fmt)) { 863 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", 864 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 865 return -E2BIG; 866 } 867 868 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 869 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 870 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 871 return -E2BIG; 872 } 873 874 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || 875 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || 876 (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && 877 !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || 878 DPU_FORMAT_IS_YUV(fmt)) { 879 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", 880 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 881 return -E2BIG; 882 } 883 884 /* 885 * Use multirect for wide plane. We do not support dynamic 886 * assignment of SSPPs, so we know the configuration. 887 */ 888 pipe->multirect_index = DPU_SSPP_RECT_0; 889 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 890 891 r_pipe->sspp = pipe->sspp; 892 r_pipe->multirect_index = DPU_SSPP_RECT_1; 893 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 894 895 *r_pipe_cfg = *pipe_cfg; 896 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 897 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 898 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 899 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 900 } 901 902 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); 903 if (ret) 904 return ret; 905 906 if (r_pipe->sspp) { 907 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt); 908 if (ret) 909 return ret; 910 } 911 912 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 913 914 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 915 supported_rotations |= DRM_MODE_ROTATE_90; 916 917 rotation = drm_rotation_simplify(new_plane_state->rotation, 918 supported_rotations); 919 920 if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 921 (rotation & DRM_MODE_ROTATE_90)) { 922 ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); 923 if (ret) 924 return ret; 925 } 926 927 pstate->rotation = rotation; 928 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 929 930 return 0; 931 } 932 933 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) 934 { 935 const struct dpu_format *format = 936 to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb)); 937 const struct dpu_csc_cfg *csc_ptr; 938 939 if (!pipe->sspp || !pipe->sspp->ops.setup_csc) 940 return; 941 942 csc_ptr = _dpu_plane_get_csc(pipe, format); 943 if (!csc_ptr) 944 return; 945 946 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 947 csc_ptr->csc_mv[0], 948 csc_ptr->csc_mv[1], 949 csc_ptr->csc_mv[2]); 950 951 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); 952 953 } 954 955 void dpu_plane_flush(struct drm_plane *plane) 956 { 957 struct dpu_plane *pdpu; 958 struct dpu_plane_state *pstate; 959 960 if (!plane || !plane->state) { 961 DPU_ERROR("invalid plane\n"); 962 return; 963 } 964 965 pdpu = to_dpu_plane(plane); 966 pstate = to_dpu_plane_state(plane->state); 967 968 /* 969 * These updates have to be done immediately before the plane flush 970 * timing, and may not be moved to the atomic_update/mode_set functions. 971 */ 972 if (pdpu->is_error) 973 /* force white frame with 100% alpha pipe output on error */ 974 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 975 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 976 /* force 100% alpha */ 977 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 978 else { 979 dpu_plane_flush_csc(pdpu, &pstate->pipe); 980 dpu_plane_flush_csc(pdpu, &pstate->r_pipe); 981 } 982 983 /* flag h/w flush complete */ 984 if (plane->state) 985 pstate->pending = false; 986 } 987 988 /** 989 * dpu_plane_set_error: enable/disable error condition 990 * @plane: pointer to drm_plane structure 991 * @error: error value to set 992 */ 993 void dpu_plane_set_error(struct drm_plane *plane, bool error) 994 { 995 struct dpu_plane *pdpu; 996 997 if (!plane) 998 return; 999 1000 pdpu = to_dpu_plane(plane); 1001 pdpu->is_error = error; 1002 } 1003 1004 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, 1005 struct dpu_sw_pipe *pipe, 1006 struct dpu_sw_pipe_cfg *pipe_cfg, 1007 const struct dpu_format *fmt, 1008 int frame_rate, 1009 struct dpu_hw_fmt_layout *layout) 1010 { 1011 uint32_t src_flags; 1012 struct dpu_plane *pdpu = to_dpu_plane(plane); 1013 struct drm_plane_state *state = plane->state; 1014 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1015 1016 if (layout && pipe->sspp->ops.setup_sourceaddress) { 1017 trace_dpu_plane_set_scanout(pipe, layout); 1018 pipe->sspp->ops.setup_sourceaddress(pipe, layout); 1019 } 1020 1021 /* override for color fill */ 1022 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1023 _dpu_plane_set_qos_ctrl(plane, pipe, false); 1024 1025 /* skip remaining processing on color fill */ 1026 return; 1027 } 1028 1029 if (pipe->sspp->ops.setup_rects) { 1030 pipe->sspp->ops.setup_rects(pipe, 1031 pipe_cfg); 1032 } 1033 1034 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); 1035 1036 if (pipe->sspp->ops.setup_multirect) 1037 pipe->sspp->ops.setup_multirect( 1038 pipe); 1039 1040 if (pipe->sspp->ops.setup_format) { 1041 unsigned int rotation = pstate->rotation; 1042 1043 src_flags = 0x0; 1044 1045 if (rotation & DRM_MODE_REFLECT_X) 1046 src_flags |= DPU_SSPP_FLIP_LR; 1047 1048 if (rotation & DRM_MODE_REFLECT_Y) 1049 src_flags |= DPU_SSPP_FLIP_UD; 1050 1051 if (rotation & DRM_MODE_ROTATE_90) 1052 src_flags |= DPU_SSPP_ROT_90; 1053 1054 /* update format */ 1055 pipe->sspp->ops.setup_format(pipe, fmt, src_flags); 1056 1057 if (pipe->sspp->ops.setup_cdp) { 1058 const struct dpu_perf_cfg *perf = pdpu->catalog->perf; 1059 1060 pipe->sspp->ops.setup_cdp(pipe, fmt, 1061 perf->cdp_cfg[DPU_PERF_CDP_USAGE_RT].rd_enable); 1062 } 1063 } 1064 1065 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); 1066 1067 if (pipe->sspp->idx != SSPP_CURSOR0 && 1068 pipe->sspp->idx != SSPP_CURSOR1) 1069 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); 1070 1071 if (pstate->needs_qos_remap) 1072 _dpu_plane_set_qos_remap(plane, pipe); 1073 } 1074 1075 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 1076 { 1077 struct dpu_plane *pdpu = to_dpu_plane(plane); 1078 struct drm_plane_state *state = plane->state; 1079 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1080 struct dpu_sw_pipe *pipe = &pstate->pipe; 1081 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1082 struct drm_crtc *crtc = state->crtc; 1083 struct drm_framebuffer *fb = state->fb; 1084 bool is_rt_pipe; 1085 const struct dpu_format *fmt = 1086 to_dpu_format(msm_framebuffer_format(fb)); 1087 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1088 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1089 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 1090 struct msm_gem_address_space *aspace = kms->base.aspace; 1091 struct dpu_hw_fmt_layout layout; 1092 bool layout_valid = false; 1093 int ret; 1094 1095 ret = dpu_format_populate_layout(aspace, fb, &layout); 1096 if (ret) 1097 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 1098 else 1099 layout_valid = true; 1100 1101 pstate->pending = true; 1102 1103 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 1104 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); 1105 pdpu->is_rt_pipe = is_rt_pipe; 1106 1107 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 1108 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 1109 crtc->base.id, DRM_RECT_ARG(&state->dst), 1110 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 1111 1112 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, 1113 drm_mode_vrefresh(&crtc->mode), 1114 layout_valid ? &layout : NULL); 1115 1116 if (r_pipe->sspp) { 1117 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, 1118 drm_mode_vrefresh(&crtc->mode), 1119 layout_valid ? &layout : NULL); 1120 } 1121 1122 if (pstate->needs_qos_remap) 1123 pstate->needs_qos_remap = false; 1124 1125 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, 1126 &crtc->mode, pipe_cfg); 1127 1128 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); 1129 1130 if (r_pipe->sspp) { 1131 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); 1132 1133 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); 1134 } 1135 } 1136 1137 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1138 { 1139 struct drm_plane_state *state = plane->state; 1140 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1141 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1142 1143 trace_dpu_plane_disable(DRMID(plane), false, 1144 pstate->pipe.multirect_mode); 1145 1146 if (r_pipe->sspp) { 1147 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 1148 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1149 1150 if (r_pipe->sspp->ops.setup_multirect) 1151 r_pipe->sspp->ops.setup_multirect(r_pipe); 1152 } 1153 1154 pstate->pending = true; 1155 } 1156 1157 static void dpu_plane_atomic_update(struct drm_plane *plane, 1158 struct drm_atomic_state *state) 1159 { 1160 struct dpu_plane *pdpu = to_dpu_plane(plane); 1161 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 1162 plane); 1163 1164 pdpu->is_error = false; 1165 1166 DPU_DEBUG_PLANE(pdpu, "\n"); 1167 1168 if (!new_state->visible) { 1169 _dpu_plane_atomic_disable(plane); 1170 } else { 1171 dpu_plane_sspp_atomic_update(plane); 1172 } 1173 } 1174 1175 static void dpu_plane_destroy(struct drm_plane *plane) 1176 { 1177 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1178 struct dpu_plane_state *pstate; 1179 1180 DPU_DEBUG_PLANE(pdpu, "\n"); 1181 1182 if (pdpu) { 1183 pstate = to_dpu_plane_state(plane->state); 1184 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false); 1185 1186 if (pstate->r_pipe.sspp) 1187 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false); 1188 1189 mutex_destroy(&pdpu->lock); 1190 1191 /* this will destroy the states as well */ 1192 drm_plane_cleanup(plane); 1193 1194 kfree(pdpu); 1195 } 1196 } 1197 1198 static void dpu_plane_destroy_state(struct drm_plane *plane, 1199 struct drm_plane_state *state) 1200 { 1201 __drm_atomic_helper_plane_destroy_state(state); 1202 kfree(to_dpu_plane_state(state)); 1203 } 1204 1205 static struct drm_plane_state * 1206 dpu_plane_duplicate_state(struct drm_plane *plane) 1207 { 1208 struct dpu_plane *pdpu; 1209 struct dpu_plane_state *pstate; 1210 struct dpu_plane_state *old_state; 1211 1212 if (!plane) { 1213 DPU_ERROR("invalid plane\n"); 1214 return NULL; 1215 } else if (!plane->state) { 1216 DPU_ERROR("invalid plane state\n"); 1217 return NULL; 1218 } 1219 1220 old_state = to_dpu_plane_state(plane->state); 1221 pdpu = to_dpu_plane(plane); 1222 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1223 if (!pstate) { 1224 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1225 return NULL; 1226 } 1227 1228 DPU_DEBUG_PLANE(pdpu, "\n"); 1229 1230 pstate->pending = false; 1231 1232 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1233 1234 return &pstate->base; 1235 } 1236 1237 static const char * const multirect_mode_name[] = { 1238 [DPU_SSPP_MULTIRECT_NONE] = "none", 1239 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel", 1240 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx", 1241 }; 1242 1243 static const char * const multirect_index_name[] = { 1244 [DPU_SSPP_RECT_SOLO] = "solo", 1245 [DPU_SSPP_RECT_0] = "rect_0", 1246 [DPU_SSPP_RECT_1] = "rect_1", 1247 }; 1248 1249 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode) 1250 { 1251 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name))) 1252 return "unknown"; 1253 1254 return multirect_mode_name[mode]; 1255 } 1256 1257 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index) 1258 { 1259 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name))) 1260 return "unknown"; 1261 1262 return multirect_index_name[index]; 1263 } 1264 1265 static void dpu_plane_atomic_print_state(struct drm_printer *p, 1266 const struct drm_plane_state *state) 1267 { 1268 const struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1269 const struct dpu_sw_pipe *pipe = &pstate->pipe; 1270 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 1271 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 1272 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 1273 1274 drm_printf(p, "\tstage=%d\n", pstate->stage); 1275 1276 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); 1277 drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); 1278 drm_printf(p, "\tmultirect_index[0]=%s\n", 1279 dpu_get_multirect_index(pipe->multirect_index)); 1280 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); 1281 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); 1282 1283 if (r_pipe->sspp) { 1284 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); 1285 drm_printf(p, "\tmultirect_mode[1]=%s\n", 1286 dpu_get_multirect_mode(r_pipe->multirect_mode)); 1287 drm_printf(p, "\tmultirect_index[1]=%s\n", 1288 dpu_get_multirect_index(r_pipe->multirect_index)); 1289 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); 1290 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); 1291 } 1292 } 1293 1294 static void dpu_plane_reset(struct drm_plane *plane) 1295 { 1296 struct dpu_plane *pdpu; 1297 struct dpu_plane_state *pstate; 1298 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1299 1300 if (!plane) { 1301 DPU_ERROR("invalid plane\n"); 1302 return; 1303 } 1304 1305 pdpu = to_dpu_plane(plane); 1306 DPU_DEBUG_PLANE(pdpu, "\n"); 1307 1308 /* remove previous state, if present */ 1309 if (plane->state) { 1310 dpu_plane_destroy_state(plane, plane->state); 1311 plane->state = NULL; 1312 } 1313 1314 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1315 if (!pstate) { 1316 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1317 return; 1318 } 1319 1320 /* 1321 * Set the SSPP here until we have proper virtualized DPU planes. 1322 * This is the place where the state is allocated, so fill it fully. 1323 */ 1324 pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1325 pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; 1326 pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1327 1328 pstate->r_pipe.sspp = NULL; 1329 1330 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1331 } 1332 1333 #ifdef CONFIG_DEBUG_FS 1334 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1335 { 1336 struct dpu_plane *pdpu = to_dpu_plane(plane); 1337 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 1338 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1339 1340 if (!pdpu->is_rt_pipe) 1341 return; 1342 1343 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1344 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); 1345 if (pstate->r_pipe.sspp) 1346 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); 1347 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1348 } 1349 #endif 1350 1351 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1352 uint32_t format, uint64_t modifier) 1353 { 1354 if (modifier == DRM_FORMAT_MOD_LINEAR) 1355 return true; 1356 1357 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) 1358 return dpu_find_format(format, qcom_compressed_supported_formats, 1359 ARRAY_SIZE(qcom_compressed_supported_formats)); 1360 1361 return false; 1362 } 1363 1364 static const struct drm_plane_funcs dpu_plane_funcs = { 1365 .update_plane = drm_atomic_helper_update_plane, 1366 .disable_plane = drm_atomic_helper_disable_plane, 1367 .destroy = dpu_plane_destroy, 1368 .reset = dpu_plane_reset, 1369 .atomic_duplicate_state = dpu_plane_duplicate_state, 1370 .atomic_destroy_state = dpu_plane_destroy_state, 1371 .atomic_print_state = dpu_plane_atomic_print_state, 1372 .format_mod_supported = dpu_plane_format_mod_supported, 1373 }; 1374 1375 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1376 .prepare_fb = dpu_plane_prepare_fb, 1377 .cleanup_fb = dpu_plane_cleanup_fb, 1378 .atomic_check = dpu_plane_atomic_check, 1379 .atomic_update = dpu_plane_atomic_update, 1380 }; 1381 1382 /* initialize plane */ 1383 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1384 uint32_t pipe, enum drm_plane_type type, 1385 unsigned long possible_crtcs) 1386 { 1387 struct drm_plane *plane = NULL; 1388 const uint32_t *format_list; 1389 struct dpu_plane *pdpu; 1390 struct msm_drm_private *priv = dev->dev_private; 1391 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1392 struct dpu_hw_sspp *pipe_hw; 1393 uint32_t num_formats; 1394 uint32_t supported_rotations; 1395 int ret = -EINVAL; 1396 1397 /* create and zero local structure */ 1398 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1399 if (!pdpu) { 1400 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1401 ret = -ENOMEM; 1402 return ERR_PTR(ret); 1403 } 1404 1405 /* cache local stuff for later */ 1406 plane = &pdpu->base; 1407 pdpu->pipe = pipe; 1408 1409 /* initialize underlying h/w driver */ 1410 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); 1411 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { 1412 DPU_ERROR("[%u]SSPP is invalid\n", pipe); 1413 goto clean_plane; 1414 } 1415 1416 format_list = pipe_hw->cap->sblk->format_list; 1417 num_formats = pipe_hw->cap->sblk->num_formats; 1418 1419 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1420 format_list, num_formats, 1421 supported_format_modifiers, type, NULL); 1422 if (ret) 1423 goto clean_plane; 1424 1425 pdpu->catalog = kms->catalog; 1426 1427 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX); 1428 if (ret) 1429 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1430 1431 drm_plane_create_alpha_property(plane); 1432 drm_plane_create_blend_mode_property(plane, 1433 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1434 BIT(DRM_MODE_BLEND_PREMULTI) | 1435 BIT(DRM_MODE_BLEND_COVERAGE)); 1436 1437 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1438 1439 if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1440 supported_rotations |= DRM_MODE_ROTATE_MASK; 1441 1442 drm_plane_create_rotation_property(plane, 1443 DRM_MODE_ROTATE_0, supported_rotations); 1444 1445 drm_plane_enable_fb_damage_clips(plane); 1446 1447 /* success! finalize initialization */ 1448 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1449 1450 mutex_init(&pdpu->lock); 1451 1452 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, 1453 pipe, plane->base.id); 1454 return plane; 1455 1456 clean_plane: 1457 kfree(pdpu); 1458 return ERR_PTR(ret); 1459 } 1460