1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 10 #include <linux/debugfs.h> 11 #include <linux/dma-buf.h> 12 13 #include <drm/drm_atomic_uapi.h> 14 15 #include "msm_drv.h" 16 #include "dpu_kms.h" 17 #include "dpu_formats.h" 18 #include "dpu_hw_sspp.h" 19 #include "dpu_hw_catalog_format.h" 20 #include "dpu_trace.h" 21 #include "dpu_crtc.h" 22 #include "dpu_vbif.h" 23 #include "dpu_plane.h" 24 25 #define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\ 26 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 27 28 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ 29 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) 30 31 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 32 #define PHASE_STEP_SHIFT 21 33 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT)) 34 #define PHASE_RESIDUAL 15 35 36 #define SHARP_STRENGTH_DEFAULT 32 37 #define SHARP_EDGE_THR_DEFAULT 112 38 #define SHARP_SMOOTH_THR_DEFAULT 8 39 #define SHARP_NOISE_THR_DEFAULT 2 40 41 #define DPU_NAME_SIZE 12 42 43 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) 44 #define DPU_ZPOS_MAX 255 45 46 /* multirect rect index */ 47 enum { 48 R0, 49 R1, 50 R_MAX 51 }; 52 53 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 54 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 55 56 #define DEFAULT_REFRESH_RATE 60 57 58 /** 59 * enum dpu_plane_qos - Different qos configurations for each pipe 60 * 61 * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. 62 * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. 63 * this configuration is mutually exclusive from VBLANK_CTRL. 64 * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. 65 */ 66 enum dpu_plane_qos { 67 DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), 68 DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), 69 DPU_PLANE_QOS_PANIC_CTRL = BIT(2), 70 }; 71 72 /* 73 * struct dpu_plane - local dpu plane structure 74 * @aspace: address space pointer 75 * @csc_ptr: Points to dpu_csc_cfg structure to use for current 76 * @mplane_list: List of multirect planes of the same pipe 77 * @catalog: Points to dpu catalog structure 78 * @revalidate: force revalidation of all the plane properties 79 */ 80 struct dpu_plane { 81 struct drm_plane base; 82 83 struct mutex lock; 84 85 enum dpu_sspp pipe; 86 uint32_t features; /* capabilities from catalog */ 87 88 struct dpu_hw_pipe *pipe_hw; 89 struct dpu_hw_pipe_cfg pipe_cfg; 90 struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; 91 uint32_t color_fill; 92 bool is_error; 93 bool is_rt_pipe; 94 bool is_virtual; 95 struct list_head mplane_list; 96 struct dpu_mdss_cfg *catalog; 97 98 struct dpu_csc_cfg *csc_ptr; 99 100 const struct dpu_sspp_sub_blks *pipe_sblk; 101 char pipe_name[DPU_NAME_SIZE]; 102 103 /* debugfs related stuff */ 104 struct dentry *debugfs_root; 105 struct dpu_debugfs_regset32 debugfs_src; 106 struct dpu_debugfs_regset32 debugfs_scaler; 107 struct dpu_debugfs_regset32 debugfs_csc; 108 bool debugfs_default_scale; 109 }; 110 111 static const uint64_t supported_format_modifiers[] = { 112 DRM_FORMAT_MOD_QCOM_COMPRESSED, 113 DRM_FORMAT_MOD_LINEAR, 114 DRM_FORMAT_MOD_INVALID 115 }; 116 117 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base) 118 119 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) 120 { 121 struct msm_drm_private *priv = plane->dev->dev_private; 122 123 return to_dpu_kms(priv->kms); 124 } 125 126 /** 127 * _dpu_plane_calc_fill_level - calculate fill level of the given source format 128 * @plane: Pointer to drm plane 129 * @fmt: Pointer to source buffer format 130 * @src_wdith: width of source buffer 131 * Return: fill level corresponding to the source buffer/format or 0 if error 132 */ 133 static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 134 const struct dpu_format *fmt, u32 src_width) 135 { 136 struct dpu_plane *pdpu, *tmp; 137 struct dpu_plane_state *pstate; 138 u32 fixed_buff_size; 139 u32 total_fl; 140 141 if (!fmt || !plane->state || !src_width || !fmt->bpp) { 142 DPU_ERROR("invalid arguments\n"); 143 return 0; 144 } 145 146 pdpu = to_dpu_plane(plane); 147 pstate = to_dpu_plane_state(plane->state); 148 fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size; 149 150 list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) { 151 if (!tmp->base.state->visible) 152 continue; 153 DPU_DEBUG("plane%d/%d src_width:%d/%d\n", 154 pdpu->base.base.id, tmp->base.base.id, 155 src_width, 156 drm_rect_width(&tmp->pipe_cfg.src_rect)); 157 src_width = max_t(u32, src_width, 158 drm_rect_width(&tmp->pipe_cfg.src_rect)); 159 } 160 161 if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { 162 if (fmt->chroma_sample == DPU_CHROMA_420) { 163 /* NV12 */ 164 total_fl = (fixed_buff_size / 2) / 165 ((src_width + 32) * fmt->bpp); 166 } else { 167 /* non NV12 */ 168 total_fl = (fixed_buff_size / 2) * 2 / 169 ((src_width + 32) * fmt->bpp); 170 } 171 } else { 172 if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { 173 total_fl = (fixed_buff_size / 2) * 2 / 174 ((src_width + 32) * fmt->bpp); 175 } else { 176 total_fl = (fixed_buff_size) * 2 / 177 ((src_width + 32) * fmt->bpp); 178 } 179 } 180 181 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n", 182 plane->base.id, pdpu->pipe - SSPP_VIG0, 183 (char *)&fmt->base.pixel_format, 184 src_width, total_fl); 185 186 return total_fl; 187 } 188 189 /** 190 * _dpu_plane_get_qos_lut - get LUT mapping based on fill level 191 * @tbl: Pointer to LUT table 192 * @total_fl: fill level 193 * Return: LUT setting corresponding to the fill level 194 */ 195 static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, 196 u32 total_fl) 197 { 198 int i; 199 200 if (!tbl || !tbl->nentry || !tbl->entries) 201 return 0; 202 203 for (i = 0; i < tbl->nentry; i++) 204 if (total_fl <= tbl->entries[i].fl) 205 return tbl->entries[i].lut; 206 207 /* if last fl is zero, use as default */ 208 if (!tbl->entries[i-1].fl) 209 return tbl->entries[i-1].lut; 210 211 return 0; 212 } 213 214 /** 215 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane 216 * @plane: Pointer to drm plane 217 * @fb: Pointer to framebuffer associated with the given plane 218 */ 219 static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 220 struct drm_framebuffer *fb) 221 { 222 struct dpu_plane *pdpu = to_dpu_plane(plane); 223 const struct dpu_format *fmt = NULL; 224 u64 qos_lut; 225 u32 total_fl = 0, lut_usage; 226 227 if (!pdpu->is_rt_pipe) { 228 lut_usage = DPU_QOS_LUT_USAGE_NRT; 229 } else { 230 fmt = dpu_get_dpu_format_ext( 231 fb->format->format, 232 fb->modifier); 233 total_fl = _dpu_plane_calc_fill_level(plane, fmt, 234 drm_rect_width(&pdpu->pipe_cfg.src_rect)); 235 236 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) 237 lut_usage = DPU_QOS_LUT_USAGE_LINEAR; 238 else 239 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; 240 } 241 242 qos_lut = _dpu_plane_get_qos_lut( 243 &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); 244 245 pdpu->pipe_qos_cfg.creq_lut = qos_lut; 246 247 trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, 248 (fmt) ? fmt->base.pixel_format : 0, 249 pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); 250 251 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", 252 plane->base.id, 253 pdpu->pipe - SSPP_VIG0, 254 fmt ? (char *)&fmt->base.pixel_format : NULL, 255 pdpu->is_rt_pipe, total_fl, qos_lut); 256 257 pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg); 258 } 259 260 /** 261 * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane 262 * @plane: Pointer to drm plane 263 * @fb: Pointer to framebuffer associated with the given plane 264 */ 265 static void _dpu_plane_set_danger_lut(struct drm_plane *plane, 266 struct drm_framebuffer *fb) 267 { 268 struct dpu_plane *pdpu = to_dpu_plane(plane); 269 const struct dpu_format *fmt = NULL; 270 u32 danger_lut, safe_lut; 271 272 if (!pdpu->is_rt_pipe) { 273 danger_lut = pdpu->catalog->perf.danger_lut_tbl 274 [DPU_QOS_LUT_USAGE_NRT]; 275 safe_lut = pdpu->catalog->perf.safe_lut_tbl 276 [DPU_QOS_LUT_USAGE_NRT]; 277 } else { 278 fmt = dpu_get_dpu_format_ext( 279 fb->format->format, 280 fb->modifier); 281 282 if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { 283 danger_lut = pdpu->catalog->perf.danger_lut_tbl 284 [DPU_QOS_LUT_USAGE_LINEAR]; 285 safe_lut = pdpu->catalog->perf.safe_lut_tbl 286 [DPU_QOS_LUT_USAGE_LINEAR]; 287 } else { 288 danger_lut = pdpu->catalog->perf.danger_lut_tbl 289 [DPU_QOS_LUT_USAGE_MACROTILE]; 290 safe_lut = pdpu->catalog->perf.safe_lut_tbl 291 [DPU_QOS_LUT_USAGE_MACROTILE]; 292 } 293 } 294 295 pdpu->pipe_qos_cfg.danger_lut = danger_lut; 296 pdpu->pipe_qos_cfg.safe_lut = safe_lut; 297 298 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 299 (fmt) ? fmt->base.pixel_format : 0, 300 (fmt) ? fmt->fetch_mode : 0, 301 pdpu->pipe_qos_cfg.danger_lut, 302 pdpu->pipe_qos_cfg.safe_lut); 303 304 DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", 305 plane->base.id, 306 pdpu->pipe - SSPP_VIG0, 307 fmt ? (char *)&fmt->base.pixel_format : NULL, 308 fmt ? fmt->fetch_mode : -1, 309 pdpu->pipe_qos_cfg.danger_lut, 310 pdpu->pipe_qos_cfg.safe_lut); 311 312 pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, 313 &pdpu->pipe_qos_cfg); 314 } 315 316 /** 317 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane 318 * @plane: Pointer to drm plane 319 * @enable: true to enable QoS control 320 * @flags: QoS control mode (enum dpu_plane_qos) 321 */ 322 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, 323 bool enable, u32 flags) 324 { 325 struct dpu_plane *pdpu = to_dpu_plane(plane); 326 327 if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { 328 pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; 329 pdpu->pipe_qos_cfg.danger_vblank = 330 pdpu->pipe_sblk->danger_vblank; 331 pdpu->pipe_qos_cfg.vblank_en = enable; 332 } 333 334 if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { 335 /* this feature overrules previous VBLANK_CTRL */ 336 pdpu->pipe_qos_cfg.vblank_en = false; 337 pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ 338 } 339 340 if (flags & DPU_PLANE_QOS_PANIC_CTRL) 341 pdpu->pipe_qos_cfg.danger_safe_en = enable; 342 343 if (!pdpu->is_rt_pipe) { 344 pdpu->pipe_qos_cfg.vblank_en = false; 345 pdpu->pipe_qos_cfg.danger_safe_en = false; 346 } 347 348 DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", 349 plane->base.id, 350 pdpu->pipe - SSPP_VIG0, 351 pdpu->pipe_qos_cfg.danger_safe_en, 352 pdpu->pipe_qos_cfg.vblank_en, 353 pdpu->pipe_qos_cfg.creq_vblank, 354 pdpu->pipe_qos_cfg.danger_vblank, 355 pdpu->is_rt_pipe); 356 357 pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, 358 &pdpu->pipe_qos_cfg); 359 } 360 361 /** 362 * _dpu_plane_set_ot_limit - set OT limit for the given plane 363 * @plane: Pointer to drm plane 364 * @crtc: Pointer to drm crtc 365 */ 366 static void _dpu_plane_set_ot_limit(struct drm_plane *plane, 367 struct drm_crtc *crtc) 368 { 369 struct dpu_plane *pdpu = to_dpu_plane(plane); 370 struct dpu_vbif_set_ot_params ot_params; 371 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 372 373 memset(&ot_params, 0, sizeof(ot_params)); 374 ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; 375 ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; 376 ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect); 377 ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect); 378 ot_params.is_wfd = !pdpu->is_rt_pipe; 379 ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); 380 ot_params.vbif_idx = VBIF_RT; 381 ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 382 ot_params.rd = true; 383 384 dpu_vbif_set_ot_limit(dpu_kms, &ot_params); 385 } 386 387 /** 388 * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane 389 * @plane: Pointer to drm plane 390 */ 391 static void _dpu_plane_set_qos_remap(struct drm_plane *plane) 392 { 393 struct dpu_plane *pdpu = to_dpu_plane(plane); 394 struct dpu_vbif_set_qos_params qos_params; 395 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 396 397 memset(&qos_params, 0, sizeof(qos_params)); 398 qos_params.vbif_idx = VBIF_RT; 399 qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; 400 qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; 401 qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; 402 qos_params.is_rt = pdpu->is_rt_pipe; 403 404 DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", 405 plane->base.id, qos_params.num, 406 qos_params.vbif_idx, 407 qos_params.xin_id, qos_params.is_rt, 408 qos_params.clk_ctrl); 409 410 dpu_vbif_set_qos_remap(dpu_kms, &qos_params); 411 } 412 413 static void _dpu_plane_set_scanout(struct drm_plane *plane, 414 struct dpu_plane_state *pstate, 415 struct dpu_hw_pipe_cfg *pipe_cfg, 416 struct drm_framebuffer *fb) 417 { 418 struct dpu_plane *pdpu = to_dpu_plane(plane); 419 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 420 struct msm_gem_address_space *aspace = kms->base.aspace; 421 int ret; 422 423 ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); 424 if (ret == -EAGAIN) 425 DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); 426 else if (ret) 427 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 428 else if (pdpu->pipe_hw->ops.setup_sourceaddress) { 429 trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, 430 &pipe_cfg->layout, 431 pstate->multirect_index); 432 pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, 433 pstate->multirect_index); 434 } 435 } 436 437 static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 438 struct dpu_plane_state *pstate, 439 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, 440 struct dpu_hw_scaler3_cfg *scale_cfg, 441 const struct dpu_format *fmt, 442 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) 443 { 444 uint32_t i; 445 446 memset(scale_cfg, 0, sizeof(*scale_cfg)); 447 memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext)); 448 449 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = 450 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); 451 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = 452 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h); 453 454 455 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = 456 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; 457 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = 458 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; 459 460 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = 461 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; 462 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = 463 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; 464 465 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = 466 scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; 467 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = 468 scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; 469 470 for (i = 0; i < DPU_MAX_PLANES; i++) { 471 scale_cfg->src_width[i] = src_w; 472 scale_cfg->src_height[i] = src_h; 473 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) { 474 scale_cfg->src_width[i] /= chroma_subsmpl_h; 475 scale_cfg->src_height[i] /= chroma_subsmpl_v; 476 } 477 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; 478 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; 479 pstate->pixel_ext.num_ext_pxls_top[i] = 480 scale_cfg->src_height[i]; 481 pstate->pixel_ext.num_ext_pxls_left[i] = 482 scale_cfg->src_width[i]; 483 } 484 if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) 485 && (src_w == dst_w)) 486 return; 487 488 scale_cfg->dst_width = dst_w; 489 scale_cfg->dst_height = dst_h; 490 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; 491 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; 492 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; 493 scale_cfg->lut_flag = 0; 494 scale_cfg->blend_cfg = 1; 495 scale_cfg->enable = 1; 496 } 497 498 static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) 499 { 500 static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { 501 { 502 /* S15.16 format */ 503 0x00012A00, 0x00000000, 0x00019880, 504 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 505 0x00012A00, 0x00020480, 0x00000000, 506 }, 507 /* signed bias */ 508 { 0xfff0, 0xff80, 0xff80,}, 509 { 0x0, 0x0, 0x0,}, 510 /* unsigned clamp */ 511 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, 512 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, 513 }; 514 static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { 515 { 516 /* S15.16 format */ 517 0x00012A00, 0x00000000, 0x00019880, 518 0x00012A00, 0xFFFF9B80, 0xFFFF3000, 519 0x00012A00, 0x00020480, 0x00000000, 520 }, 521 /* signed bias */ 522 { 0xffc0, 0xfe00, 0xfe00,}, 523 { 0x0, 0x0, 0x0,}, 524 /* unsigned clamp */ 525 { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, 526 { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, 527 }; 528 529 if (!pdpu) { 530 DPU_ERROR("invalid plane\n"); 531 return; 532 } 533 534 if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features) 535 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L; 536 else 537 pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L; 538 539 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", 540 pdpu->csc_ptr->csc_mv[0], 541 pdpu->csc_ptr->csc_mv[1], 542 pdpu->csc_ptr->csc_mv[2]); 543 } 544 545 static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 546 struct dpu_plane_state *pstate, 547 const struct dpu_format *fmt, bool color_fill) 548 { 549 uint32_t chroma_subsmpl_h, chroma_subsmpl_v; 550 551 /* don't chroma subsample if decimating */ 552 chroma_subsmpl_h = 553 drm_format_horz_chroma_subsampling(fmt->base.pixel_format); 554 chroma_subsmpl_v = 555 drm_format_vert_chroma_subsampling(fmt->base.pixel_format); 556 557 /* update scaler. calculate default config for QSEED3 */ 558 _dpu_plane_setup_scaler3(pdpu, pstate, 559 drm_rect_width(&pdpu->pipe_cfg.src_rect), 560 drm_rect_height(&pdpu->pipe_cfg.src_rect), 561 drm_rect_width(&pdpu->pipe_cfg.dst_rect), 562 drm_rect_height(&pdpu->pipe_cfg.dst_rect), 563 &pstate->scaler3_cfg, fmt, 564 chroma_subsmpl_h, chroma_subsmpl_v); 565 } 566 567 /** 568 * _dpu_plane_color_fill - enables color fill on plane 569 * @pdpu: Pointer to DPU plane object 570 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 571 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 572 * Returns: 0 on success 573 */ 574 static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 575 uint32_t color, uint32_t alpha) 576 { 577 const struct dpu_format *fmt; 578 const struct drm_plane *plane = &pdpu->base; 579 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); 580 581 DPU_DEBUG_PLANE(pdpu, "\n"); 582 583 /* 584 * select fill format to match user property expectation, 585 * h/w only supports RGB variants 586 */ 587 fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); 588 589 /* update sspp */ 590 if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { 591 pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, 592 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), 593 pstate->multirect_index); 594 595 /* override scaler/decimation if solid fill */ 596 pdpu->pipe_cfg.src_rect.x1 = 0; 597 pdpu->pipe_cfg.src_rect.y1 = 0; 598 pdpu->pipe_cfg.src_rect.x2 = 599 drm_rect_width(&pdpu->pipe_cfg.dst_rect); 600 pdpu->pipe_cfg.src_rect.y2 = 601 drm_rect_height(&pdpu->pipe_cfg.dst_rect); 602 _dpu_plane_setup_scaler(pdpu, pstate, fmt, true); 603 604 if (pdpu->pipe_hw->ops.setup_format) 605 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, 606 fmt, DPU_SSPP_SOLID_FILL, 607 pstate->multirect_index); 608 609 if (pdpu->pipe_hw->ops.setup_rects) 610 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 611 &pdpu->pipe_cfg, 612 pstate->multirect_index); 613 614 if (pdpu->pipe_hw->ops.setup_pe) 615 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 616 &pstate->pixel_ext); 617 618 if (pdpu->pipe_hw->ops.setup_scaler && 619 pstate->multirect_index != DPU_SSPP_RECT_1) 620 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 621 &pdpu->pipe_cfg, &pstate->pixel_ext, 622 &pstate->scaler3_cfg); 623 } 624 625 return 0; 626 } 627 628 void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) 629 { 630 struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); 631 632 pstate->multirect_index = DPU_SSPP_RECT_SOLO; 633 pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 634 } 635 636 int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) 637 { 638 struct dpu_plane_state *pstate[R_MAX]; 639 const struct drm_plane_state *drm_state[R_MAX]; 640 struct drm_rect src[R_MAX], dst[R_MAX]; 641 struct dpu_plane *dpu_plane[R_MAX]; 642 const struct dpu_format *fmt[R_MAX]; 643 int i, buffer_lines; 644 unsigned int max_tile_height = 1; 645 bool parallel_fetch_qualified = true; 646 bool has_tiled_rect = false; 647 648 for (i = 0; i < R_MAX; i++) { 649 const struct msm_format *msm_fmt; 650 651 drm_state[i] = i ? plane->r1 : plane->r0; 652 msm_fmt = msm_framebuffer_format(drm_state[i]->fb); 653 fmt[i] = to_dpu_format(msm_fmt); 654 655 if (DPU_FORMAT_IS_UBWC(fmt[i])) { 656 has_tiled_rect = true; 657 if (fmt[i]->tile_height > max_tile_height) 658 max_tile_height = fmt[i]->tile_height; 659 } 660 } 661 662 for (i = 0; i < R_MAX; i++) { 663 int width_threshold; 664 665 pstate[i] = to_dpu_plane_state(drm_state[i]); 666 dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); 667 668 if (pstate[i] == NULL) { 669 DPU_ERROR("DPU plane state of plane id %d is NULL\n", 670 drm_state[i]->plane->base.id); 671 return -EINVAL; 672 } 673 674 src[i].x1 = drm_state[i]->src_x >> 16; 675 src[i].y1 = drm_state[i]->src_y >> 16; 676 src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); 677 src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); 678 679 dst[i] = drm_plane_state_dest(drm_state[i]); 680 681 if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || 682 drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { 683 DPU_ERROR_PLANE(dpu_plane[i], 684 "scaling is not supported in multirect mode\n"); 685 return -EINVAL; 686 } 687 688 if (DPU_FORMAT_IS_YUV(fmt[i])) { 689 DPU_ERROR_PLANE(dpu_plane[i], 690 "Unsupported format for multirect mode\n"); 691 return -EINVAL; 692 } 693 694 /** 695 * SSPP PD_MEM is split half - one for each RECT. 696 * Tiled formats need 5 lines of buffering while fetching 697 * whereas linear formats need only 2 lines. 698 * So we cannot support more than half of the supported SSPP 699 * width for tiled formats. 700 */ 701 width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth; 702 if (has_tiled_rect) 703 width_threshold /= 2; 704 705 if (parallel_fetch_qualified && 706 drm_rect_width(&src[i]) > width_threshold) 707 parallel_fetch_qualified = false; 708 709 } 710 711 /* Validate RECT's and set the mode */ 712 713 /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ 714 if (parallel_fetch_qualified) { 715 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 716 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 717 718 goto done; 719 } 720 721 /* TIME_MX Mode */ 722 buffer_lines = 2 * max_tile_height; 723 724 if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || 725 dst[R0].y1 >= dst[R1].y2 + buffer_lines) { 726 pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 727 pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; 728 } else { 729 DPU_ERROR( 730 "No multirect mode possible for the planes (%d - %d)\n", 731 drm_state[R0]->plane->base.id, 732 drm_state[R1]->plane->base.id); 733 return -EINVAL; 734 } 735 736 done: 737 if (dpu_plane[R0]->is_virtual) { 738 pstate[R0]->multirect_index = DPU_SSPP_RECT_1; 739 pstate[R1]->multirect_index = DPU_SSPP_RECT_0; 740 } else { 741 pstate[R0]->multirect_index = DPU_SSPP_RECT_0; 742 pstate[R1]->multirect_index = DPU_SSPP_RECT_1; 743 }; 744 745 DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", 746 pstate[R0]->multirect_mode, pstate[R0]->multirect_index); 747 DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", 748 pstate[R1]->multirect_mode, pstate[R1]->multirect_index); 749 return 0; 750 } 751 752 /** 753 * dpu_plane_get_ctl_flush - get control flush for the given plane 754 * @plane: Pointer to drm plane structure 755 * @ctl: Pointer to hardware control driver 756 * @flush_sspp: Pointer to sspp flush control word 757 */ 758 void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, 759 u32 *flush_sspp) 760 { 761 *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane)); 762 } 763 764 static int dpu_plane_prepare_fb(struct drm_plane *plane, 765 struct drm_plane_state *new_state) 766 { 767 struct drm_framebuffer *fb = new_state->fb; 768 struct dpu_plane *pdpu = to_dpu_plane(plane); 769 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); 770 struct dpu_hw_fmt_layout layout; 771 struct drm_gem_object *obj; 772 struct dma_fence *fence; 773 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 774 int ret; 775 776 if (!new_state->fb) 777 return 0; 778 779 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id); 780 781 /* cache aspace */ 782 pstate->aspace = kms->base.aspace; 783 784 /* 785 * TODO: Need to sort out the msm_framebuffer_prepare() call below so 786 * we can use msm_atomic_prepare_fb() instead of doing the 787 * implicit fence and fb prepare by hand here. 788 */ 789 obj = msm_framebuffer_bo(new_state->fb, 0); 790 fence = reservation_object_get_excl_rcu(obj->resv); 791 if (fence) 792 drm_atomic_set_fence_for_plane(new_state, fence); 793 794 if (pstate->aspace) { 795 ret = msm_framebuffer_prepare(new_state->fb, 796 pstate->aspace); 797 if (ret) { 798 DPU_ERROR("failed to prepare framebuffer\n"); 799 return ret; 800 } 801 } 802 803 /* validate framebuffer layout before commit */ 804 ret = dpu_format_populate_layout(pstate->aspace, 805 new_state->fb, &layout); 806 if (ret) { 807 DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 808 return ret; 809 } 810 811 return 0; 812 } 813 814 static void dpu_plane_cleanup_fb(struct drm_plane *plane, 815 struct drm_plane_state *old_state) 816 { 817 struct dpu_plane *pdpu = to_dpu_plane(plane); 818 struct dpu_plane_state *old_pstate; 819 820 if (!old_state || !old_state->fb) 821 return; 822 823 old_pstate = to_dpu_plane_state(old_state); 824 825 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id); 826 827 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace); 828 } 829 830 static bool dpu_plane_validate_src(struct drm_rect *src, 831 struct drm_rect *fb_rect, 832 uint32_t min_src_size) 833 { 834 /* Ensure fb size is supported */ 835 if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || 836 drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) 837 return false; 838 839 /* Ensure src rect is above the minimum size */ 840 if (drm_rect_width(src) < min_src_size || 841 drm_rect_height(src) < min_src_size) 842 return false; 843 844 /* Ensure src is fully encapsulated in fb */ 845 return drm_rect_intersect(fb_rect, src) && 846 drm_rect_equals(fb_rect, src); 847 } 848 849 static int dpu_plane_atomic_check(struct drm_plane *plane, 850 struct drm_plane_state *state) 851 { 852 int ret = 0, min_scale; 853 struct dpu_plane *pdpu = to_dpu_plane(plane); 854 const struct drm_crtc_state *crtc_state = NULL; 855 const struct dpu_format *fmt; 856 struct drm_rect src, dst, fb_rect = { 0 }; 857 uint32_t min_src_size, max_linewidth; 858 859 if (state->crtc) 860 crtc_state = drm_atomic_get_new_crtc_state(state->state, 861 state->crtc); 862 863 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale); 864 ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale, 865 pdpu->pipe_sblk->maxupscale << 16, 866 true, true); 867 if (ret) { 868 DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret); 869 return ret; 870 } 871 if (!state->visible) 872 return 0; 873 874 src.x1 = state->src_x >> 16; 875 src.y1 = state->src_y >> 16; 876 src.x2 = src.x1 + (state->src_w >> 16); 877 src.y2 = src.y1 + (state->src_h >> 16); 878 879 dst = drm_plane_state_dest(state); 880 881 fb_rect.x2 = state->fb->width; 882 fb_rect.y2 = state->fb->height; 883 884 max_linewidth = pdpu->pipe_sblk->common->maxlinewidth; 885 886 fmt = to_dpu_format(msm_framebuffer_format(state->fb)); 887 888 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 889 890 if (DPU_FORMAT_IS_YUV(fmt) && 891 (!(pdpu->features & DPU_SSPP_SCALER) || 892 !(pdpu->features & (BIT(DPU_SSPP_CSC) 893 | BIT(DPU_SSPP_CSC_10BIT))))) { 894 DPU_ERROR_PLANE(pdpu, 895 "plane doesn't have scaler/csc for yuv\n"); 896 return -EINVAL; 897 898 /* check src bounds */ 899 } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { 900 DPU_ERROR_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", 901 DRM_RECT_ARG(&src)); 902 return -E2BIG; 903 904 /* valid yuv image */ 905 } else if (DPU_FORMAT_IS_YUV(fmt) && 906 (src.x1 & 0x1 || src.y1 & 0x1 || 907 drm_rect_width(&src) & 0x1 || 908 drm_rect_height(&src) & 0x1)) { 909 DPU_ERROR_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", 910 DRM_RECT_ARG(&src)); 911 return -EINVAL; 912 913 /* min dst support */ 914 } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { 915 DPU_ERROR_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 916 DRM_RECT_ARG(&dst)); 917 return -EINVAL; 918 919 /* check decimated source width */ 920 } else if (drm_rect_width(&src) > max_linewidth) { 921 DPU_ERROR_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 922 DRM_RECT_ARG(&src), max_linewidth); 923 return -E2BIG; 924 } 925 926 return 0; 927 } 928 929 void dpu_plane_flush(struct drm_plane *plane) 930 { 931 struct dpu_plane *pdpu; 932 struct dpu_plane_state *pstate; 933 934 if (!plane || !plane->state) { 935 DPU_ERROR("invalid plane\n"); 936 return; 937 } 938 939 pdpu = to_dpu_plane(plane); 940 pstate = to_dpu_plane_state(plane->state); 941 942 /* 943 * These updates have to be done immediately before the plane flush 944 * timing, and may not be moved to the atomic_update/mode_set functions. 945 */ 946 if (pdpu->is_error) 947 /* force white frame with 100% alpha pipe output on error */ 948 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF); 949 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) 950 /* force 100% alpha */ 951 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); 952 else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc) 953 pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr); 954 955 /* flag h/w flush complete */ 956 if (plane->state) 957 pstate->pending = false; 958 } 959 960 /** 961 * dpu_plane_set_error: enable/disable error condition 962 * @plane: pointer to drm_plane structure 963 */ 964 void dpu_plane_set_error(struct drm_plane *plane, bool error) 965 { 966 struct dpu_plane *pdpu; 967 968 if (!plane) 969 return; 970 971 pdpu = to_dpu_plane(plane); 972 pdpu->is_error = error; 973 } 974 975 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 976 { 977 uint32_t src_flags; 978 struct dpu_plane *pdpu = to_dpu_plane(plane); 979 struct drm_plane_state *state = plane->state; 980 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 981 struct drm_crtc *crtc = state->crtc; 982 struct drm_framebuffer *fb = state->fb; 983 const struct dpu_format *fmt = 984 to_dpu_format(msm_framebuffer_format(fb)); 985 986 memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg)); 987 988 _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb); 989 990 pstate->pending = true; 991 992 pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); 993 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 994 995 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT 996 ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), 997 crtc->base.id, DRM_RECT_ARG(&state->dst), 998 (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); 999 1000 pdpu->pipe_cfg.src_rect = state->src; 1001 1002 /* state->src is 16.16, src_rect is not */ 1003 pdpu->pipe_cfg.src_rect.x1 >>= 16; 1004 pdpu->pipe_cfg.src_rect.x2 >>= 16; 1005 pdpu->pipe_cfg.src_rect.y1 >>= 16; 1006 pdpu->pipe_cfg.src_rect.y2 >>= 16; 1007 1008 pdpu->pipe_cfg.dst_rect = state->dst; 1009 1010 _dpu_plane_setup_scaler(pdpu, pstate, fmt, false); 1011 1012 /* override for color fill */ 1013 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { 1014 /* skip remaining processing on color fill */ 1015 return; 1016 } 1017 1018 if (pdpu->pipe_hw->ops.setup_rects) { 1019 pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, 1020 &pdpu->pipe_cfg, 1021 pstate->multirect_index); 1022 } 1023 1024 if (pdpu->pipe_hw->ops.setup_pe && 1025 (pstate->multirect_index != DPU_SSPP_RECT_1)) 1026 pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, 1027 &pstate->pixel_ext); 1028 1029 /** 1030 * when programmed in multirect mode, scalar block will be 1031 * bypassed. Still we need to update alpha and bitwidth 1032 * ONLY for RECT0 1033 */ 1034 if (pdpu->pipe_hw->ops.setup_scaler && 1035 pstate->multirect_index != DPU_SSPP_RECT_1) 1036 pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, 1037 &pdpu->pipe_cfg, &pstate->pixel_ext, 1038 &pstate->scaler3_cfg); 1039 1040 if (pdpu->pipe_hw->ops.setup_multirect) 1041 pdpu->pipe_hw->ops.setup_multirect( 1042 pdpu->pipe_hw, 1043 pstate->multirect_index, 1044 pstate->multirect_mode); 1045 1046 if (pdpu->pipe_hw->ops.setup_format) { 1047 src_flags = 0x0; 1048 1049 /* update format */ 1050 pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, 1051 pstate->multirect_index); 1052 1053 if (pdpu->pipe_hw->ops.setup_cdp) { 1054 struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg; 1055 1056 memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg)); 1057 1058 cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg 1059 [DPU_PERF_CDP_USAGE_RT].rd_enable; 1060 cdp_cfg->ubwc_meta_enable = 1061 DPU_FORMAT_IS_UBWC(fmt); 1062 cdp_cfg->tile_amortize_enable = 1063 DPU_FORMAT_IS_UBWC(fmt) || 1064 DPU_FORMAT_IS_TILE(fmt); 1065 cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; 1066 1067 pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg); 1068 } 1069 1070 /* update csc */ 1071 if (DPU_FORMAT_IS_YUV(fmt)) 1072 _dpu_plane_setup_csc(pdpu); 1073 else 1074 pdpu->csc_ptr = 0; 1075 } 1076 1077 _dpu_plane_set_qos_lut(plane, fb); 1078 _dpu_plane_set_danger_lut(plane, fb); 1079 1080 if (plane->type != DRM_PLANE_TYPE_CURSOR) { 1081 _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); 1082 _dpu_plane_set_ot_limit(plane, crtc); 1083 } 1084 1085 _dpu_plane_set_qos_remap(plane); 1086 } 1087 1088 static void _dpu_plane_atomic_disable(struct drm_plane *plane) 1089 { 1090 struct dpu_plane *pdpu = to_dpu_plane(plane); 1091 struct drm_plane_state *state = plane->state; 1092 struct dpu_plane_state *pstate = to_dpu_plane_state(state); 1093 1094 trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane), 1095 pstate->multirect_mode); 1096 1097 pstate->pending = true; 1098 1099 if (is_dpu_plane_virtual(plane) && 1100 pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect) 1101 pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw, 1102 DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE); 1103 } 1104 1105 static void dpu_plane_atomic_update(struct drm_plane *plane, 1106 struct drm_plane_state *old_state) 1107 { 1108 struct dpu_plane *pdpu = to_dpu_plane(plane); 1109 struct drm_plane_state *state = plane->state; 1110 1111 pdpu->is_error = false; 1112 1113 DPU_DEBUG_PLANE(pdpu, "\n"); 1114 1115 if (!state->visible) { 1116 _dpu_plane_atomic_disable(plane); 1117 } else { 1118 dpu_plane_sspp_atomic_update(plane); 1119 } 1120 } 1121 1122 void dpu_plane_restore(struct drm_plane *plane) 1123 { 1124 struct dpu_plane *pdpu; 1125 1126 if (!plane || !plane->state) { 1127 DPU_ERROR("invalid plane\n"); 1128 return; 1129 } 1130 1131 pdpu = to_dpu_plane(plane); 1132 1133 DPU_DEBUG_PLANE(pdpu, "\n"); 1134 1135 /* last plane state is same as current state */ 1136 dpu_plane_atomic_update(plane, plane->state); 1137 } 1138 1139 static void dpu_plane_destroy(struct drm_plane *plane) 1140 { 1141 struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; 1142 1143 DPU_DEBUG_PLANE(pdpu, "\n"); 1144 1145 if (pdpu) { 1146 _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); 1147 1148 mutex_destroy(&pdpu->lock); 1149 1150 /* this will destroy the states as well */ 1151 drm_plane_cleanup(plane); 1152 1153 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1154 1155 kfree(pdpu); 1156 } 1157 } 1158 1159 static void dpu_plane_destroy_state(struct drm_plane *plane, 1160 struct drm_plane_state *state) 1161 { 1162 __drm_atomic_helper_plane_destroy_state(state); 1163 kfree(to_dpu_plane_state(state)); 1164 } 1165 1166 static struct drm_plane_state * 1167 dpu_plane_duplicate_state(struct drm_plane *plane) 1168 { 1169 struct dpu_plane *pdpu; 1170 struct dpu_plane_state *pstate; 1171 struct dpu_plane_state *old_state; 1172 1173 if (!plane) { 1174 DPU_ERROR("invalid plane\n"); 1175 return NULL; 1176 } else if (!plane->state) { 1177 DPU_ERROR("invalid plane state\n"); 1178 return NULL; 1179 } 1180 1181 old_state = to_dpu_plane_state(plane->state); 1182 pdpu = to_dpu_plane(plane); 1183 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL); 1184 if (!pstate) { 1185 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1186 return NULL; 1187 } 1188 1189 DPU_DEBUG_PLANE(pdpu, "\n"); 1190 1191 pstate->pending = false; 1192 1193 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base); 1194 1195 return &pstate->base; 1196 } 1197 1198 static void dpu_plane_reset(struct drm_plane *plane) 1199 { 1200 struct dpu_plane *pdpu; 1201 struct dpu_plane_state *pstate; 1202 1203 if (!plane) { 1204 DPU_ERROR("invalid plane\n"); 1205 return; 1206 } 1207 1208 pdpu = to_dpu_plane(plane); 1209 DPU_DEBUG_PLANE(pdpu, "\n"); 1210 1211 /* remove previous state, if present */ 1212 if (plane->state) { 1213 dpu_plane_destroy_state(plane, plane->state); 1214 plane->state = 0; 1215 } 1216 1217 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 1218 if (!pstate) { 1219 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1220 return; 1221 } 1222 1223 pstate->base.plane = plane; 1224 1225 plane->state = &pstate->base; 1226 } 1227 1228 #ifdef CONFIG_DEBUG_FS 1229 static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) 1230 { 1231 struct dpu_plane *pdpu = to_dpu_plane(plane); 1232 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1233 1234 if (!pdpu->is_rt_pipe) 1235 return; 1236 1237 pm_runtime_get_sync(&dpu_kms->pdev->dev); 1238 _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); 1239 pm_runtime_put_sync(&dpu_kms->pdev->dev); 1240 } 1241 1242 static ssize_t _dpu_plane_danger_read(struct file *file, 1243 char __user *buff, size_t count, loff_t *ppos) 1244 { 1245 struct dpu_kms *kms = file->private_data; 1246 int len; 1247 char buf[40]; 1248 1249 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); 1250 1251 return simple_read_from_buffer(buff, count, ppos, buf, len); 1252 } 1253 1254 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) 1255 { 1256 struct drm_plane *plane; 1257 1258 drm_for_each_plane(plane, kms->dev) { 1259 if (plane->fb && plane->state) { 1260 dpu_plane_danger_signal_ctrl(plane, enable); 1261 DPU_DEBUG("plane:%d img:%dx%d ", 1262 plane->base.id, plane->fb->width, 1263 plane->fb->height); 1264 DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", 1265 plane->state->src_x >> 16, 1266 plane->state->src_y >> 16, 1267 plane->state->src_w >> 16, 1268 plane->state->src_h >> 16, 1269 plane->state->crtc_x, plane->state->crtc_y, 1270 plane->state->crtc_w, plane->state->crtc_h); 1271 } else { 1272 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); 1273 } 1274 } 1275 } 1276 1277 static ssize_t _dpu_plane_danger_write(struct file *file, 1278 const char __user *user_buf, size_t count, loff_t *ppos) 1279 { 1280 struct dpu_kms *kms = file->private_data; 1281 int disable_panic; 1282 int ret; 1283 1284 ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); 1285 if (ret) 1286 return ret; 1287 1288 if (disable_panic) { 1289 /* Disable panic signal for all active pipes */ 1290 DPU_DEBUG("Disabling danger:\n"); 1291 _dpu_plane_set_danger_state(kms, false); 1292 kms->has_danger_ctrl = false; 1293 } else { 1294 /* Enable panic signal for all active pipes */ 1295 DPU_DEBUG("Enabling danger:\n"); 1296 kms->has_danger_ctrl = true; 1297 _dpu_plane_set_danger_state(kms, true); 1298 } 1299 1300 return count; 1301 } 1302 1303 static const struct file_operations dpu_plane_danger_enable = { 1304 .open = simple_open, 1305 .read = _dpu_plane_danger_read, 1306 .write = _dpu_plane_danger_write, 1307 }; 1308 1309 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1310 { 1311 struct dpu_plane *pdpu = to_dpu_plane(plane); 1312 struct dpu_kms *kms = _dpu_plane_get_kms(plane); 1313 const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap; 1314 const struct dpu_sspp_sub_blks *sblk = cfg->sblk; 1315 1316 /* create overall sub-directory for the pipe */ 1317 pdpu->debugfs_root = 1318 debugfs_create_dir(pdpu->pipe_name, 1319 plane->dev->primary->debugfs_root); 1320 1321 if (!pdpu->debugfs_root) 1322 return -ENOMEM; 1323 1324 /* don't error check these */ 1325 debugfs_create_x32("features", 0600, 1326 pdpu->debugfs_root, &pdpu->features); 1327 1328 /* add register dump support */ 1329 dpu_debugfs_setup_regset32(&pdpu->debugfs_src, 1330 sblk->src_blk.base + cfg->base, 1331 sblk->src_blk.len, 1332 kms); 1333 dpu_debugfs_create_regset32("src_blk", 0400, 1334 pdpu->debugfs_root, &pdpu->debugfs_src); 1335 1336 if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || 1337 cfg->features & BIT(DPU_SSPP_SCALER_QSEED2)) { 1338 dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler, 1339 sblk->scaler_blk.base + cfg->base, 1340 sblk->scaler_blk.len, 1341 kms); 1342 dpu_debugfs_create_regset32("scaler_blk", 0400, 1343 pdpu->debugfs_root, 1344 &pdpu->debugfs_scaler); 1345 debugfs_create_bool("default_scaling", 1346 0600, 1347 pdpu->debugfs_root, 1348 &pdpu->debugfs_default_scale); 1349 } 1350 1351 if (cfg->features & BIT(DPU_SSPP_CSC) || 1352 cfg->features & BIT(DPU_SSPP_CSC_10BIT)) { 1353 dpu_debugfs_setup_regset32(&pdpu->debugfs_csc, 1354 sblk->csc_blk.base + cfg->base, 1355 sblk->csc_blk.len, 1356 kms); 1357 dpu_debugfs_create_regset32("csc_blk", 0400, 1358 pdpu->debugfs_root, &pdpu->debugfs_csc); 1359 } 1360 1361 debugfs_create_u32("xin_id", 1362 0400, 1363 pdpu->debugfs_root, 1364 (u32 *) &cfg->xin_id); 1365 debugfs_create_u32("clk_ctrl", 1366 0400, 1367 pdpu->debugfs_root, 1368 (u32 *) &cfg->clk_ctrl); 1369 debugfs_create_x32("creq_vblank", 1370 0600, 1371 pdpu->debugfs_root, 1372 (u32 *) &sblk->creq_vblank); 1373 debugfs_create_x32("danger_vblank", 1374 0600, 1375 pdpu->debugfs_root, 1376 (u32 *) &sblk->danger_vblank); 1377 1378 debugfs_create_file("disable_danger", 1379 0600, 1380 pdpu->debugfs_root, 1381 kms, &dpu_plane_danger_enable); 1382 1383 return 0; 1384 } 1385 #else 1386 static int _dpu_plane_init_debugfs(struct drm_plane *plane) 1387 { 1388 return 0; 1389 } 1390 #endif 1391 1392 static int dpu_plane_late_register(struct drm_plane *plane) 1393 { 1394 return _dpu_plane_init_debugfs(plane); 1395 } 1396 1397 static void dpu_plane_early_unregister(struct drm_plane *plane) 1398 { 1399 struct dpu_plane *pdpu = to_dpu_plane(plane); 1400 1401 debugfs_remove_recursive(pdpu->debugfs_root); 1402 } 1403 1404 static bool dpu_plane_format_mod_supported(struct drm_plane *plane, 1405 uint32_t format, uint64_t modifier) 1406 { 1407 if (modifier == DRM_FORMAT_MOD_LINEAR) 1408 return true; 1409 1410 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) { 1411 int i; 1412 for (i = 0; i < ARRAY_SIZE(qcom_compressed_supported_formats); i++) { 1413 if (format == qcom_compressed_supported_formats[i]) 1414 return true; 1415 } 1416 } 1417 1418 return false; 1419 } 1420 1421 static const struct drm_plane_funcs dpu_plane_funcs = { 1422 .update_plane = drm_atomic_helper_update_plane, 1423 .disable_plane = drm_atomic_helper_disable_plane, 1424 .destroy = dpu_plane_destroy, 1425 .reset = dpu_plane_reset, 1426 .atomic_duplicate_state = dpu_plane_duplicate_state, 1427 .atomic_destroy_state = dpu_plane_destroy_state, 1428 .late_register = dpu_plane_late_register, 1429 .early_unregister = dpu_plane_early_unregister, 1430 .format_mod_supported = dpu_plane_format_mod_supported, 1431 }; 1432 1433 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { 1434 .prepare_fb = dpu_plane_prepare_fb, 1435 .cleanup_fb = dpu_plane_cleanup_fb, 1436 .atomic_check = dpu_plane_atomic_check, 1437 .atomic_update = dpu_plane_atomic_update, 1438 }; 1439 1440 enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) 1441 { 1442 return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; 1443 } 1444 1445 bool is_dpu_plane_virtual(struct drm_plane *plane) 1446 { 1447 return plane ? to_dpu_plane(plane)->is_virtual : false; 1448 } 1449 1450 /* initialize plane */ 1451 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1452 uint32_t pipe, enum drm_plane_type type, 1453 unsigned long possible_crtcs, u32 master_plane_id) 1454 { 1455 struct drm_plane *plane = NULL, *master_plane = NULL; 1456 const uint32_t *format_list; 1457 struct dpu_plane *pdpu; 1458 struct msm_drm_private *priv = dev->dev_private; 1459 struct dpu_kms *kms = to_dpu_kms(priv->kms); 1460 int zpos_max = DPU_ZPOS_MAX; 1461 uint32_t num_formats; 1462 int ret = -EINVAL; 1463 1464 /* create and zero local structure */ 1465 pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL); 1466 if (!pdpu) { 1467 DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe); 1468 ret = -ENOMEM; 1469 return ERR_PTR(ret); 1470 } 1471 1472 /* cache local stuff for later */ 1473 plane = &pdpu->base; 1474 pdpu->pipe = pipe; 1475 pdpu->is_virtual = (master_plane_id != 0); 1476 INIT_LIST_HEAD(&pdpu->mplane_list); 1477 master_plane = drm_plane_find(dev, NULL, master_plane_id); 1478 if (master_plane) { 1479 struct dpu_plane *mpdpu = to_dpu_plane(master_plane); 1480 1481 list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list); 1482 } 1483 1484 /* initialize underlying h/w driver */ 1485 pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, 1486 master_plane_id != 0); 1487 if (IS_ERR(pdpu->pipe_hw)) { 1488 DPU_ERROR("[%u]SSPP init failed\n", pipe); 1489 ret = PTR_ERR(pdpu->pipe_hw); 1490 goto clean_plane; 1491 } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { 1492 DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); 1493 goto clean_sspp; 1494 } 1495 1496 /* cache features mask for later */ 1497 pdpu->features = pdpu->pipe_hw->cap->features; 1498 pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk; 1499 if (!pdpu->pipe_sblk) { 1500 DPU_ERROR("[%u]invalid sblk\n", pipe); 1501 goto clean_sspp; 1502 } 1503 1504 if (pdpu->is_virtual) { 1505 format_list = pdpu->pipe_sblk->virt_format_list; 1506 num_formats = pdpu->pipe_sblk->virt_num_formats; 1507 } 1508 else { 1509 format_list = pdpu->pipe_sblk->format_list; 1510 num_formats = pdpu->pipe_sblk->num_formats; 1511 } 1512 1513 ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, 1514 format_list, num_formats, 1515 supported_format_modifiers, type, NULL); 1516 if (ret) 1517 goto clean_sspp; 1518 1519 pdpu->catalog = kms->catalog; 1520 1521 if (kms->catalog->mixer_count && 1522 kms->catalog->mixer[0].sblk->maxblendstages) { 1523 zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; 1524 if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) 1525 zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; 1526 } 1527 1528 ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); 1529 if (ret) 1530 DPU_ERROR("failed to install zpos property, rc = %d\n", ret); 1531 1532 /* success! finalize initialization */ 1533 drm_plane_helper_add(plane, &dpu_plane_helper_funcs); 1534 1535 /* save user friendly pipe name for later */ 1536 snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id); 1537 1538 mutex_init(&pdpu->lock); 1539 1540 DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name, 1541 pipe, plane->base.id, master_plane_id); 1542 return plane; 1543 1544 clean_sspp: 1545 if (pdpu && pdpu->pipe_hw) 1546 dpu_hw_sspp_destroy(pdpu->pipe_hw); 1547 clean_plane: 1548 kfree(pdpu); 1549 return ERR_PTR(ret); 1550 } 1551